From 44991eb4bfd63b043b50e880d347a7946d6a9736 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Thu, 12 Jun 2014 17:38:40 +0800 Subject: [PATCH 1/7] ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles For all BG2Q SoCs, 2 cycles is the best/correct value. Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 635a16a64cb4..3f95dc568b23 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -90,6 +90,8 @@ l2: l2-cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-level = <2>; + arm,data-latency = <2 2 2>; + arm,tag-latency = <2 2 2>; }; scu: snoop-control-unit@ad0000 { From 99f3deb8c95c999cd90f324c81d839b154acd244 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Tue, 3 Jun 2014 09:33:09 +0200 Subject: [PATCH 2/7] ARM: dts: berlin: add I2C nodes for BG2Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Marvell Berlin BG2Q has 4 TWSI compatible with the Synopsys DesignWare I2C driver. Add the corresponding nodes. The pin-muxing setup is also done here, since there cannot be another muxing setup if I2C{0,1,2,3} are enabled. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 72 +++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 3f95dc568b23..bf163f48bd7c 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -193,6 +193,32 @@ portd: gpio-port@3 { }; }; + i2c0: i2c@1400 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1400 0x100>; + interrupt-parent = <&aic>; + interrupts = <4>; + clocks = <&chip CLKID_CFG>; + pinctrl-0 = <&twsi0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c1: i2c@1800 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800 0x100>; + interrupt-parent = <&aic>; + interrupts = <5>; + clocks = <&chip CLKID_CFG>; + pinctrl-0 = <&twsi1_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; @@ -303,6 +329,16 @@ chip: chip-control@ea0000 { reg = <0xea0000 0x400>, <0xdd0170 0x10>; clocks = <&refclk>; clock-names = "refclk"; + + twsi0_pmux: twsi0-pmux { + groups = "G6"; + function = "twsi0"; + }; + + twsi1_pmux: twsi1-pmux { + groups = "G7"; + function = "twsi1"; + }; }; apb@fc0000 { @@ -313,6 +349,32 @@ apb@fc0000 { ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; + i2c2: i2c@7000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x100>; + interrupt-parent = <&sic>; + interrupts = <6>; + clocks = <&refclk>; + pinctrl-0 = <&twsi2_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c3: i2c@8000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8000 0x100>; + interrupt-parent = <&sic>; + interrupts = <7>; + clocks = <&refclk>; + pinctrl-0 = <&twsi3_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + uart0: uart@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; @@ -350,6 +412,16 @@ uart1_pmux: uart1-pmux { groups = "GSM14"; function = "uart1"; }; + + twsi2_pmux: twsi2-pmux { + groups = "GSM13"; + function = "twsi2"; + }; + + twsi3_pmux: twsi3-pmux { + groups = "GSM14"; + function = "twsi3"; + }; }; sic: interrupt-controller@e000 { From fbcdc07971cd274e444593a862783e94fbf4f1ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Tue, 3 Jun 2014 09:33:10 +0200 Subject: [PATCH 3/7] ARM: dts: berlin: enable i2c0 and i2c2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the I2C0 and I2C2 for the Marvell Berlin BG2G DMP. I2C1 and I2C3 are also working on this board, but no devices seemed to be there. Signed-off-by: Antoine Ténart Reviewed-by: Andrew Lunn Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index 995150f93795..a357ce02a64e 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -34,6 +34,14 @@ &sdhci2 { status = "okay"; }; +&i2c0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + &uart0 { status = "okay"; }; From 9ab5fb8ad11ad20e100796ca9b2e43f40de796c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Wed, 4 Jun 2014 18:03:43 +0200 Subject: [PATCH 4/7] Documentation: bindings: add the Berlin CPU control doc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the CPU control compatible, needed for the SMP support on Marvell Berlin SoCs. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- .../devicetree/bindings/arm/marvell,berlin.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 94013a9a8769..904de5781f44 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -24,6 +24,22 @@ SoC and board used. Currently known SoC compatibles are: ... } +* Marvell Berlin CPU control bindings + +CPU control register allows various operations on CPUs, like resetting them +independently. + +Required properties: +- compatible: should be "marvell,berlin-cpu-ctrl" +- reg: address and length of the register set + +Example: + +cpu-ctrl@f7dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xf7dd0000 0x10000>; +}; + * Marvell Berlin2 chip control binding Marvell Berlin SoCs have a chip control register set providing several From a2418f4f049f43a8a5764807436125d753ca716a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Wed, 4 Jun 2014 18:03:44 +0200 Subject: [PATCH 5/7] Documentation: bindings: add the marvell,berlin-smp CPU enable method MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the CPU enable method used by Marvell Berlin SoCs. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- .../arm/cpu-enable-method/marvell,berlin-smp | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp new file mode 100644 index 000000000000..cd236b727e2a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp @@ -0,0 +1,41 @@ +======================================================== +Secondary CPU enable-method "marvell,berlin-smp" binding +======================================================== + +This document describes the "marvell,berlin-smp" method for enabling secondary +CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should +be defined in the "cpus" node. + +Enable method name: "marvell,berlin-smp" +Compatible machines: "marvell,berlin2" and "marvell,berlin2q" +Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"marvell,berlin-cpu-ctrl"[1]. + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,berlin-smp"; + + cpu@0 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + + cpu@1 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + }; + }; + +-- +[1] arm/marvell,berlin.txt From 460d02ac9599e91d64522a9380f03d2e2e3086e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Wed, 4 Jun 2014 18:03:45 +0200 Subject: [PATCH 6/7] ARM: dts: berlin: add SMP related nodes and properties for BG2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add required nodes and properties into the Berlin BG2 device tree to take advantage of the newly introduced SMP support. Add the scu and cpu-ctrl nodes along with the CPUs enable-method property. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 2477dac4d643..9d7c810ebd0b 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -22,6 +22,7 @@ / { cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,berlin-smp"; cpu@0 { compatible = "marvell,pj4b"; @@ -78,6 +79,11 @@ local-timer@ad0600 { clocks = <&chip CLKID_TWD>; }; + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; From d19c93670a3dc6d8b37a3256f20eeafff5417f93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Antoine=20T=C3=A9nart?= Date: Wed, 4 Jun 2014 18:03:46 +0200 Subject: [PATCH 7/7] ARM: dts: berlin: add SMP related nodes and properties for BG2Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add required nodes and properties into the Berlin BG2Q device tree to take advantage of the newly introduced SMP support. Add the scu and cpu-ctrl nodes along with the CPUs enable-method property. Signed-off-by: Antoine Ténart Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index bf163f48bd7c..400c40fceccc 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -18,6 +18,7 @@ / { cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,berlin-smp"; cpu@0 { compatible = "arm,cortex-a9"; @@ -113,6 +114,11 @@ gic: interrupt-controller@ad1000 { #interrupt-cells = <3>; }; + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>;