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arm64: dts: qcom: sa8775p: add Display Serial Interface device nodes

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Add device tree nodes for the DSI0 and DSI1 controllers
with their corresponding PHYs found on Qualcomm SA8775P SoC.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: Dmitry Baryshkov <lumag@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250604071851.1438612-2-quic_amakhija@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Ayushi Makhija 2025-06-04 12:48:50 +05:30 committed by Bjorn Andersson
parent 4ba960e75b
commit 73db32b01c
1 changed files with 176 additions and 1 deletions
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177
arch/arm64/boot/dts/qcom/sa8775p.dtsi
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@ -6,6 +6,7 @@
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
@ -4156,6 +4157,22 @@ dpu_intf4_out: endpoint {
remote-endpoint = <&mdss0_dp1_in>;
};
};
port@2 {
reg = <2>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss0_dsi0_in>;
};
};
port@3 {
reg = <3>;
dpu_intf2_out: endpoint {
remote-endpoint = <&mdss0_dsi1_in>;
};
};
};
mdss0_mdp_opp_table: opp-table {
@ -4183,6 +4200,161 @@ opp-650000000 {
};
};
mdss0_dsi0: dsi@ae94000 {
compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x0ae94000 0x0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss0>;
interrupts = <4>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>;
phys = <&mdss0_dsi0_phy>;
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss0_dsi0_out: endpoint{ };
};
};
mdss_dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
mdss0_dsi0_phy: phy@ae94400 {
compatible = "qcom,sa8775p-dsi-phy-5nm";
reg = <0x0 0x0ae94400 0x0 0x200>,
<0x0 0x0ae94600 0x0 0x280>,
<0x0 0x0ae94900 0x0 0x27c>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
mdss0_dsi1: dsi@ae96000 {
compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0 0x0ae96000 0x0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss0>;
interrupts = <5>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
<&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
phys = <&mdss0_dsi1_phy>;
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss0_dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
mdss0_dsi1_out: endpoint { };
};
};
};
mdss0_dsi1_phy: phy@ae96400 {
compatible = "qcom,sa8775p-dsi-phy-5nm";
reg = <0x0 0x0ae96400 0x0 0x200>,
<0x0 0x0ae96600 0x0 0x280>,
<0x0 0x0ae96900 0x0 0x27c>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
mdss0_dp0_phy: phy@aec2a00 {
compatible = "qcom,sa8775p-edp-phy";
@ -4389,7 +4561,10 @@ dispcc0: clock-controller@af00000 {
<&sleep_clk>,
<&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
<&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
<0>, <0>, <0>, <0>;
<&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>,
<&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>,
<&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;