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ASoC: mediatek: mt8196: support audio clock control
Add audio clock wrapper and audio tuner control. Signed-off-by: Darren Ye <darren.ye@mediatek.com> Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com> Link: https://patch.msgid.link/20260430022417.32282-4-Cyril.Chao@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Darren Ye
Mark Brown
parent
33eda2c14f
commit
7384ecab34
581
sound/soc/mediatek/mt8196/mt8196-afe-clk.c
Normal file
581
sound/soc/mediatek/mt8196/mt8196-afe-clk.c
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@ -0,0 +1,581 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* mt8196-afe-clk.c -- Mediatek 8196 afe clock ctrl
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*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include "mt8196-afe-clk.h"
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#include "mt8196-afe-common.h"
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static const char *aud_clks[MT8196_CLK_NUM] = {
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/* vlp clk */
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[MT8196_CLK_VLP_MUX_AUDIOINTBUS] = "top_aud_intbus",
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[MT8196_CLK_VLP_MUX_AUD_ENG1] = "top_aud_eng1",
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[MT8196_CLK_VLP_MUX_AUD_ENG2] = "top_aud_eng2",
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[MT8196_CLK_VLP_MUX_AUDIO_H] = "top_aud_h",
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/* pll */
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[MT8196_CLK_TOP_APLL1_CK] = "apll1",
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[MT8196_CLK_TOP_APLL2_CK] = "apll2",
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/* divider */
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[MT8196_CLK_TOP_APLL12_DIV_I2SIN0] = "apll12_div_i2sin0",
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[MT8196_CLK_TOP_APLL12_DIV_I2SIN1] = "apll12_div_i2sin1",
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[MT8196_CLK_TOP_APLL12_DIV_FMI2S] = "apll12_div_fmi2s",
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[MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M] = "apll12_div_tdmout_m",
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[MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B] = "apll12_div_tdmout_b",
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/* mux */
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[MT8196_CLK_TOP_ADSP_SEL] = "top_adsp",
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};
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int mt8196_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
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{
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int ret;
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(afe->dev, "failed to enable clk\n");
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt8196_afe_enable_clk);
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void mt8196_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
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{
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if (clk)
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clk_disable_unprepare(clk);
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else
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dev_err(afe->dev, "NULL clk\n");
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}
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EXPORT_SYMBOL_GPL(mt8196_afe_disable_clk);
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static int mt8196_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
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unsigned int rate)
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{
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int ret;
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if (clk) {
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ret = clk_set_rate(clk, rate);
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if (ret) {
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dev_err(afe->dev, "failed to set clk rate\n");
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return ret;
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}
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}
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return 0;
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}
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static unsigned int get_top_cg_reg(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8196_AUDIO_26M_EN_ON:
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case MT8196_AUDIO_F3P25M_EN_ON:
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case MT8196_AUDIO_APLL1_EN_ON:
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case MT8196_AUDIO_APLL2_EN_ON:
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return AUDIO_ENGEN_CON0;
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case MT8196_CG_AUDIO_HOPPING_CK:
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case MT8196_CG_AUDIO_F26M_CK:
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case MT8196_CG_APLL1_CK:
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case MT8196_CG_APLL2_CK:
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case MT8196_PDN_APLL_TUNER2:
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case MT8196_PDN_APLL_TUNER1:
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return AUDIO_TOP_CON4;
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_mask(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8196_AUDIO_26M_EN_ON:
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return AUDIO_26M_EN_ON_MASK_SFT;
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case MT8196_AUDIO_F3P25M_EN_ON:
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return AUDIO_F3P25M_EN_ON_MASK_SFT;
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case MT8196_AUDIO_APLL1_EN_ON:
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return AUDIO_APLL1_EN_ON_MASK_SFT;
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case MT8196_AUDIO_APLL2_EN_ON:
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return AUDIO_APLL2_EN_ON_MASK_SFT;
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case MT8196_CG_AUDIO_HOPPING_CK:
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return CG_AUDIO_HOPPING_CK_MASK_SFT;
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case MT8196_CG_AUDIO_F26M_CK:
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return CG_AUDIO_F26M_CK_MASK_SFT;
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case MT8196_CG_APLL1_CK:
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return CG_APLL1_CK_MASK_SFT;
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case MT8196_CG_APLL2_CK:
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return CG_APLL2_CK_MASK_SFT;
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case MT8196_PDN_APLL_TUNER2:
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return PDN_APLL_TUNER2_MASK_SFT;
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case MT8196_PDN_APLL_TUNER1:
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return PDN_APLL_TUNER1_MASK_SFT;
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_on_val(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8196_AUDIO_26M_EN_ON:
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case MT8196_AUDIO_F3P25M_EN_ON:
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case MT8196_AUDIO_APLL1_EN_ON:
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case MT8196_AUDIO_APLL2_EN_ON:
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return get_top_cg_mask(cg_type);
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case MT8196_CG_AUDIO_HOPPING_CK:
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case MT8196_CG_AUDIO_F26M_CK:
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case MT8196_CG_APLL1_CK:
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case MT8196_CG_APLL2_CK:
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case MT8196_PDN_APLL_TUNER2:
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case MT8196_PDN_APLL_TUNER1:
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return 0;
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default:
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return 0;
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}
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}
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static unsigned int get_top_cg_off_val(unsigned int cg_type)
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{
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switch (cg_type) {
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case MT8196_AUDIO_26M_EN_ON:
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case MT8196_AUDIO_F3P25M_EN_ON:
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case MT8196_AUDIO_APLL1_EN_ON:
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case MT8196_AUDIO_APLL2_EN_ON:
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return 0;
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case MT8196_CG_AUDIO_HOPPING_CK:
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case MT8196_CG_AUDIO_F26M_CK:
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case MT8196_CG_APLL1_CK:
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case MT8196_CG_APLL2_CK:
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case MT8196_PDN_APLL_TUNER2:
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case MT8196_PDN_APLL_TUNER1:
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return get_top_cg_mask(cg_type);
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default:
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return get_top_cg_mask(cg_type);
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}
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}
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static int mt8196_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
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{
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int ret;
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unsigned int reg = get_top_cg_reg(cg_type);
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unsigned int mask = get_top_cg_mask(cg_type);
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unsigned int val = get_top_cg_on_val(cg_type);
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if (!afe->regmap) {
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dev_err(afe->dev, "afe regmap is null !!!\n");
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return 0;
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}
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dev_dbg(afe->dev, "reg: 0x%x, mask: 0x%x, val: 0x%x\n", reg, mask, val);
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ret = regmap_update_bits(afe->regmap, reg, mask, val);
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if (ret)
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dev_err(afe->dev, "regmap_update_bits failed: %d\n", ret);
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return ret;
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}
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static int mt8196_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
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{
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int ret;
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unsigned int reg = get_top_cg_reg(cg_type);
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unsigned int mask = get_top_cg_mask(cg_type);
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unsigned int val = get_top_cg_off_val(cg_type);
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if (!afe->regmap) {
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dev_err(afe->dev, "afe regmap is null !!!\n");
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return 0;
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}
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dev_dbg(afe->dev, "reg: 0x%x, mask: 0x%x, val: 0x%x\n", reg, mask, val);
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ret = regmap_update_bits(afe->regmap, reg, mask, val);
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if (ret)
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dev_err(afe->dev, "regmap_update_bits failed: %d\n", ret);
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return ret;
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}
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static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
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{
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struct mt8196_afe_private *afe_priv = afe->platform_priv;
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int apll_rate;
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int ret;
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dev_dbg(afe->dev, "enable: %d\n", enable);
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if (enable) {
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apll_rate = mt8196_get_apll_rate(afe, MT8196_APLL1);
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/* 180.6336 / 4 = 45.1584MHz */
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ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1]);
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if (ret)
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return ret;
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
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MT8196_AUD_ENG1_CLK);
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if (ret)
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return ret;
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ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
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if (ret)
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return ret;
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
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apll_rate);
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if (ret)
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return ret;
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} else {
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
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MT8196_AFE_26M);
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if (ret)
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return ret;
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mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1]);
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
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MT8196_AFE_26M);
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if (ret)
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return ret;
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mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
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}
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return 0;
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}
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static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
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{
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struct mt8196_afe_private *afe_priv = afe->platform_priv;
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int apll_rate;
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int ret;
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dev_dbg(afe->dev, "enable: %d\n", enable);
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if (enable) {
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apll_rate = mt8196_get_apll_rate(afe, MT8196_APLL2);
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/* 196.608 / 4 = 49.152MHz */
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ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2]);
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if (ret)
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return ret;
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
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MT8196_AUD_ENG2_CLK);
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if (ret)
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return ret;
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ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
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if (ret)
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return ret;
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
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apll_rate);
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if (ret)
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return ret;
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} else {
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
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MT8196_AFE_26M);
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if (ret)
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return ret;
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mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2]);
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ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
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MT8196_AFE_26M);
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if (ret)
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return ret;
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mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
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}
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return 0;
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}
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int mt8196_apll1_enable(struct mtk_base_afe *afe)
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{
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int ret;
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/* setting for APLL */
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apll1_mux_setting(afe, true);
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ret = mt8196_afe_enable_top_cg(afe, MT8196_CG_APLL1_CK);
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if (ret)
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goto err_clk_apll1;
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ret = mt8196_afe_enable_top_cg(afe, MT8196_PDN_APLL_TUNER1);
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if (ret)
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goto err_clk_apll1_tuner;
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/* sel 44.1kHz:1, apll_div:7, upper bound:3 */
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regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
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XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
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(0x1 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
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(3 << UPPER_BOUND_SFT));
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/* apll1 freq tuner enable */
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regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
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FREQ_TUNER_EN_MASK_SFT,
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0x1 << FREQ_TUNER_EN_SFT);
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/* audio apll1 on */
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mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
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return 0;
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err_clk_apll1_tuner:
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mt8196_afe_disable_top_cg(afe, MT8196_PDN_APLL_TUNER1);
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err_clk_apll1:
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mt8196_afe_disable_top_cg(afe, MT8196_CG_APLL1_CK);
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return ret;
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}
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void mt8196_apll1_disable(struct mtk_base_afe *afe)
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{
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/* audio apll1 off */
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mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL1_EN_ON);
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/* apll1 freq tuner disable */
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regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
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FREQ_TUNER_EN_MASK_SFT,
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0x0);
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mt8196_afe_disable_top_cg(afe, MT8196_PDN_APLL_TUNER1);
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mt8196_afe_disable_top_cg(afe, MT8196_CG_APLL1_CK);
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apll1_mux_setting(afe, false);
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}
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int mt8196_apll2_enable(struct mtk_base_afe *afe)
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{
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int ret;
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/* setting for APLL */
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apll2_mux_setting(afe, true);
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ret = mt8196_afe_enable_top_cg(afe, MT8196_CG_APLL2_CK);
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if (ret)
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goto err_clk_apll2;
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ret = mt8196_afe_enable_top_cg(afe, MT8196_PDN_APLL_TUNER2);
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if (ret)
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goto err_clk_apll2_tuner;
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/* sel 48kHz: 2, apll_div: 7, upper bound: 3*/
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regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
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XTAL_EN_128FS_SEL_MASK_SFT | APLL_DIV_MASK_SFT | UPPER_BOUND_MASK_SFT,
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(0x2 << XTAL_EN_128FS_SEL_SFT) | (7 << APLL_DIV_SFT) |
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(3 << UPPER_BOUND_SFT));
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/* apll2 freq tuner enable */
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regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
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FREQ_TUNER_EN_MASK_SFT,
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0x1 << FREQ_TUNER_EN_SFT);
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/* audio apll2 on */
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mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
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return 0;
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err_clk_apll2_tuner:
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mt8196_afe_disable_top_cg(afe, MT8196_PDN_APLL_TUNER2);
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err_clk_apll2:
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mt8196_afe_disable_top_cg(afe, MT8196_CG_APLL2_CK);
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return 0;
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}
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void mt8196_apll2_disable(struct mtk_base_afe *afe)
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{
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/* audio apll2 off */
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mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_APLL2_EN_ON);
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/* apll2 freq tuner disable */
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regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
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FREQ_TUNER_EN_MASK_SFT,
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0x0);
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mt8196_afe_disable_top_cg(afe, MT8196_PDN_APLL_TUNER2);
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mt8196_afe_disable_top_cg(afe, MT8196_CG_APLL2_CK);
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apll2_mux_setting(afe, false);
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}
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|
||||
int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll)
|
||||
{
|
||||
struct mt8196_afe_private *afe_priv = afe->platform_priv;
|
||||
int clk_id = 0;
|
||||
|
||||
if (apll < MT8196_APLL1 || apll > MT8196_APLL2) {
|
||||
dev_warn(afe->dev, "invalid clk id %d\n", apll);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (apll == MT8196_APLL1)
|
||||
clk_id = MT8196_CLK_TOP_APLL1_CK;
|
||||
else
|
||||
clk_id = MT8196_CLK_TOP_APLL2_CK;
|
||||
|
||||
return clk_get_rate(afe_priv->clk[clk_id]);
|
||||
}
|
||||
|
||||
/* 48K: select APLL2; 44.1k: select APLL1 */
|
||||
int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
|
||||
{
|
||||
return (rate % 8000) ? MT8196_APLL1 : MT8196_APLL2;
|
||||
}
|
||||
|
||||
int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
|
||||
{
|
||||
if (strcmp(name, APLL1_W_NAME) == 0)
|
||||
return MT8196_APLL1;
|
||||
|
||||
return MT8196_APLL2;
|
||||
}
|
||||
|
||||
static const int mck_div[MT8196_MCK_NUM] = {
|
||||
[MT8196_I2SIN0_MCK] = MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
|
||||
[MT8196_I2SIN1_MCK] = MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
|
||||
[MT8196_FMI2S_MCK] = MT8196_CLK_TOP_APLL12_DIV_FMI2S,
|
||||
[MT8196_TDMOUT_MCK] = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
|
||||
[MT8196_TDMOUT_BCK] = MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
|
||||
};
|
||||
|
||||
int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
|
||||
{
|
||||
struct mt8196_afe_private *afe_priv = afe->platform_priv;
|
||||
int div_clk_id;
|
||||
int ret;
|
||||
|
||||
dev_dbg(afe->dev, "mck_id: %d, rate: %d\n", mck_id, rate);
|
||||
|
||||
if (mck_id >= MT8196_MCK_NUM || mck_id < 0)
|
||||
return -EINVAL;
|
||||
|
||||
div_clk_id = mck_div[mck_id];
|
||||
|
||||
/* enable div, set rate */
|
||||
if (div_clk_id < 0) {
|
||||
dev_err(afe->dev, "invalid div_clk_id %d\n", div_clk_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (div_clk_id == MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B)
|
||||
rate *= 16;
|
||||
|
||||
ret = mt8196_afe_enable_clk(afe, afe_priv->clk[div_clk_id]);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[div_clk_id], rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id)
|
||||
{
|
||||
struct mt8196_afe_private *afe_priv = afe->platform_priv;
|
||||
int div_clk_id;
|
||||
int ret;
|
||||
|
||||
dev_dbg(afe->dev, "mck_id: %d.\n", mck_id);
|
||||
|
||||
if (mck_id < 0) {
|
||||
dev_err(afe->dev, "mck_id = %d < 0\n", mck_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
div_clk_id = mck_div[mck_id];
|
||||
|
||||
if (div_clk_id < 0) {
|
||||
dev_err(afe->dev, "div_clk_id = %d < 0\n",
|
||||
div_clk_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[div_clk_id], MT8196_AFE_26M);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mt8196_afe_disable_clk(afe, afe_priv->clk[div_clk_id]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8196_afe_private *afe_priv = afe->platform_priv;
|
||||
int ret;
|
||||
|
||||
/* bus clock for AFE external access, like DRAM */
|
||||
mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
|
||||
|
||||
/* bus clock for AFE internal access, like AFE SRAM */
|
||||
mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
|
||||
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS],
|
||||
MT8196_AFE_26M);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* enable audio h clock */
|
||||
mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
|
||||
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
|
||||
MT8196_AFE_26M);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* AFE hw clock */
|
||||
/* IPM2.0: USE HOPPING & 26M */
|
||||
/* set in the regmap_register_patch */
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8196_afe_private *afe_priv = afe->platform_priv;
|
||||
|
||||
/* IPM2.0: Use HOPPING & 26M */
|
||||
/* set in the regmap_register_patch */
|
||||
|
||||
mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
|
||||
mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIOINTBUS]);
|
||||
mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_TOP_ADSP_SEL]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
mt8196_afe_enable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
mt8196_afe_disable_top_cg(afe, MT8196_AUDIO_26M_EN_ON);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mt8196_init_clock(struct mtk_base_afe *afe)
|
||||
{
|
||||
struct mt8196_afe_private *afe_priv = afe->platform_priv;
|
||||
int i;
|
||||
|
||||
afe_priv->clk = devm_kcalloc(afe->dev, MT8196_CLK_NUM, sizeof(*afe_priv->clk),
|
||||
GFP_KERNEL);
|
||||
if (!afe_priv->clk)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < MT8196_CLK_NUM; i++) {
|
||||
afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
|
||||
if (IS_ERR(afe_priv->clk[i])) {
|
||||
dev_err(afe->dev, "devm_clk_get %s fail\n", aud_clks[i]);
|
||||
return PTR_ERR(afe_priv->clk[i]);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
64
sound/soc/mediatek/mt8196/mt8196-afe-clk.h
Normal file
64
sound/soc/mediatek/mt8196/mt8196-afe-clk.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* mt8196-afe-clk.h -- Mediatek MT8196 AFE Clock Control definitions
|
||||
*
|
||||
* Copyright (c) 2025 MediaTek Inc.
|
||||
* Author: Darren Ye <darren.ye@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _MT8196_AFE_CLOCK_CTRL_H_
|
||||
#define _MT8196_AFE_CLOCK_CTRL_H_
|
||||
|
||||
#define MT8196_AFE_26M 26000000
|
||||
#define MT8196_AUD_ENG1_CLK 45158400
|
||||
#define MT8196_AUD_ENG2_CLK 49152000
|
||||
|
||||
/* APLL */
|
||||
#define APLL1_W_NAME "APLL1"
|
||||
#define APLL2_W_NAME "APLL2"
|
||||
|
||||
enum {
|
||||
MT8196_APLL1 = 0,
|
||||
MT8196_APLL2,
|
||||
};
|
||||
|
||||
enum {
|
||||
/* vlp clk */
|
||||
MT8196_CLK_VLP_MUX_AUDIOINTBUS,
|
||||
MT8196_CLK_VLP_MUX_AUD_ENG1,
|
||||
MT8196_CLK_VLP_MUX_AUD_ENG2,
|
||||
MT8196_CLK_VLP_MUX_AUDIO_H,
|
||||
/* pll */
|
||||
MT8196_CLK_TOP_APLL1_CK,
|
||||
MT8196_CLK_TOP_APLL2_CK,
|
||||
/* divider */
|
||||
MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
|
||||
MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
|
||||
MT8196_CLK_TOP_APLL12_DIV_FMI2S,
|
||||
MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
|
||||
MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
|
||||
/* mux */
|
||||
MT8196_CLK_TOP_ADSP_SEL,
|
||||
MT8196_CLK_NUM,
|
||||
};
|
||||
|
||||
struct mtk_base_afe;
|
||||
|
||||
int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
|
||||
int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id);
|
||||
int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll);
|
||||
int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
|
||||
int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
|
||||
int mt8196_init_clock(struct mtk_base_afe *afe);
|
||||
int mt8196_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
void mt8196_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
|
||||
int mt8196_apll1_enable(struct mtk_base_afe *afe);
|
||||
void mt8196_apll1_disable(struct mtk_base_afe *afe);
|
||||
int mt8196_apll2_enable(struct mtk_base_afe *afe);
|
||||
void mt8196_apll2_disable(struct mtk_base_afe *afe);
|
||||
int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe);
|
||||
int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe);
|
||||
int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
|
||||
int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user