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ASoC: mediatek: mt8196: add common header
Add header files for register definitions and structures. Signed-off-by: Darren Ye <darren.ye@mediatek.com> Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com> Link: https://patch.msgid.link/20260430022417.32282-3-Cyril.Chao@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Darren Ye
Mark Brown
parent
1aadc0147b
commit
33eda2c14f
205
sound/soc/mediatek/mt8196/mt8196-afe-common.h
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205
sound/soc/mediatek/mt8196/mt8196-afe-common.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8196-afe-common.h -- Mediatek 8196 audio driver definitions
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*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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#ifndef _MT_8196_AFE_COMMON_H_
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#define _MT_8196_AFE_COMMON_H_
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#include <sound/pcm.h>
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#include <sound/soc.h>
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#include "mt8196-reg.h"
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#include "../common/mtk-base-afe.h"
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/* HW IPM 2.0 */
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enum {
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MTK_AFE_IPM2P0_RATE_8K = 0x0,
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MTK_AFE_IPM2P0_RATE_11K = 0x1,
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MTK_AFE_IPM2P0_RATE_12K = 0x2,
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MTK_AFE_IPM2P0_RATE_16K = 0x4,
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MTK_AFE_IPM2P0_RATE_22K = 0x5,
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MTK_AFE_IPM2P0_RATE_24K = 0x6,
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MTK_AFE_IPM2P0_RATE_32K = 0x8,
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MTK_AFE_IPM2P0_RATE_44K = 0x9,
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MTK_AFE_IPM2P0_RATE_48K = 0xa,
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MTK_AFE_IPM2P0_RATE_88K = 0xd,
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MTK_AFE_IPM2P0_RATE_96K = 0xe,
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MTK_AFE_IPM2P0_RATE_176K = 0x11,
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MTK_AFE_IPM2P0_RATE_192K = 0x12,
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MTK_AFE_IPM2P0_RATE_352K = 0x15,
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MTK_AFE_IPM2P0_RATE_384K = 0x16,
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};
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enum {
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MTKAIF_PROTOCOL_1,
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MTKAIF_PROTOCOL_2,
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MTKAIF_PROTOCOL_2_CLK_P2,
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};
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enum {
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MT8196_MEMIF_DL0,
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MT8196_MEMIF_DL1,
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MT8196_MEMIF_DL2,
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MT8196_MEMIF_DL3,
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MT8196_MEMIF_DL4,
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MT8196_MEMIF_DL5,
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MT8196_MEMIF_DL6,
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MT8196_MEMIF_DL7,
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MT8196_MEMIF_DL8,
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MT8196_MEMIF_DL23,
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MT8196_MEMIF_DL24,
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MT8196_MEMIF_DL25,
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MT8196_MEMIF_DL26,
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MT8196_MEMIF_DL_4CH,
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MT8196_MEMIF_DL_24CH,
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MT8196_MEMIF_VUL0,
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MT8196_MEMIF_VUL1,
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MT8196_MEMIF_VUL2,
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MT8196_MEMIF_VUL3,
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MT8196_MEMIF_VUL4,
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MT8196_MEMIF_VUL5,
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MT8196_MEMIF_VUL6,
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MT8196_MEMIF_VUL7,
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MT8196_MEMIF_VUL8,
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MT8196_MEMIF_VUL9,
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MT8196_MEMIF_VUL10,
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MT8196_MEMIF_VUL24,
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MT8196_MEMIF_VUL25,
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MT8196_MEMIF_VUL26,
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MT8196_MEMIF_VUL_CM0,
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MT8196_MEMIF_VUL_CM1,
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MT8196_MEMIF_VUL_CM2,
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MT8196_MEMIF_ETDM_IN0,
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MT8196_MEMIF_ETDM_IN1,
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MT8196_MEMIF_ETDM_IN2,
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MT8196_MEMIF_ETDM_IN3,
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MT8196_MEMIF_ETDM_IN4,
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MT8196_MEMIF_ETDM_IN6,
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MT8196_MEMIF_HDMI,
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MT8196_MEMIF_NUM,
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MT8196_DAI_ADDA = MT8196_MEMIF_NUM,
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MT8196_DAI_ADDA_CH34,
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MT8196_DAI_ADDA_CH56,
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MT8196_DAI_AP_DMIC,
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MT8196_DAI_AP_DMIC_CH34,
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MT8196_DAI_AP_DMIC_MULTICH,
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MT8196_DAI_I2S_IN0,
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MT8196_DAI_I2S_IN1,
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MT8196_DAI_I2S_IN2,
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MT8196_DAI_I2S_IN3,
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MT8196_DAI_I2S_IN4,
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MT8196_DAI_I2S_IN6,
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MT8196_DAI_I2S_OUT0,
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MT8196_DAI_I2S_OUT1,
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MT8196_DAI_I2S_OUT2,
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MT8196_DAI_I2S_OUT3,
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MT8196_DAI_I2S_OUT4,
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MT8196_DAI_I2S_OUT6,
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MT8196_DAI_FM_I2S_MASTER,
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MT8196_DAI_TDM,
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MT8196_DAI_TDM_DPTX,
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MT8196_DAI_NUM,
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};
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#define MT8196_DAI_I2S_MAX_NUM 13 //depends each platform's max i2s num
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/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
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enum {
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MT8196_IRQ_0,
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MT8196_IRQ_1,
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MT8196_IRQ_2,
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MT8196_IRQ_3,
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MT8196_IRQ_4,
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MT8196_IRQ_5,
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MT8196_IRQ_6,
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MT8196_IRQ_7,
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MT8196_IRQ_8,
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MT8196_IRQ_9,
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MT8196_IRQ_10,
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MT8196_IRQ_11,
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MT8196_IRQ_12,
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MT8196_IRQ_13,
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MT8196_IRQ_14,
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MT8196_IRQ_15,
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MT8196_IRQ_16,
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MT8196_IRQ_17,
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MT8196_IRQ_18,
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MT8196_IRQ_19,
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MT8196_IRQ_20,
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MT8196_IRQ_21,
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MT8196_IRQ_22,
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MT8196_IRQ_23,
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MT8196_IRQ_24,
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MT8196_IRQ_25,
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MT8196_IRQ_26,
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MT8196_IRQ_31, /* used only for TDM */
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MT8196_IRQ_NUM,
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};
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/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
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enum {
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MT8196_CUS_IRQ_TDM, /* used only for TDM */
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MT8196_CUS_IRQ_NUM,
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};
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enum {
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/* AUDIO_ENGEN_CON0 */
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MT8196_AUDIO_26M_EN_ON,
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MT8196_AUDIO_F3P25M_EN_ON,
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MT8196_AUDIO_APLL1_EN_ON,
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MT8196_AUDIO_APLL2_EN_ON,
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MT8196_AUDIO_F26M_EN_RST,
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MT8196_MULTI_USER_RST,
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MT8196_MULTI_USER_BYPASS,
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/* AUDIO_TOP_CON4 */
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MT8196_CG_AUDIO_HOPPING_CK,
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MT8196_CG_AUDIO_F26M_CK,
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MT8196_CG_APLL1_CK,
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MT8196_CG_APLL2_CK,
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MT8196_PDN_APLL_TUNER2,
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MT8196_PDN_APLL_TUNER1,
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MT8196_AUDIO_CG_NUM,
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};
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/* MCLK */
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enum {
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MT8196_I2SIN0_MCK,
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MT8196_I2SIN1_MCK,
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MT8196_FMI2S_MCK,
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MT8196_TDMOUT_MCK,
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MT8196_TDMOUT_BCK,
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MT8196_MCK_NUM,
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};
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/* CM*/
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enum {
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CM0,
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CM1,
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CM2,
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CM_NUM,
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};
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struct clk;
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struct mtk_base_afe;
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struct mt8196_afe_private {
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struct clk **clk;
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/* dai */
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void *dai_priv[MT8196_DAI_NUM];
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/* mck */
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int mck_rate[MT8196_MCK_NUM];
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/* channel merge */
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u32 cm_rate[CM_NUM];
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u32 cm_channels;
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};
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int mt8196_dai_adda_register(struct mtk_base_afe *afe);
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int mt8196_dai_i2s_register(struct mtk_base_afe *afe);
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int mt8196_dai_tdm_register(struct mtk_base_afe *afe);
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int mt8196_dai_set_priv(struct mtk_base_afe *afe, int id,
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int priv_size, const void *priv_data);
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#endif
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121
sound/soc/mediatek/mt8196/mt8196-interconnection.h
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121
sound/soc/mediatek/mt8196/mt8196-interconnection.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Mediatek MT8196 audio driver interconnection definition
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*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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#ifndef _MT8196_INTERCONNECTION_H_
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#define _MT8196_INTERCONNECTION_H_
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/* in port define */
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#define I_CONNSYS_I2S_CH1 0
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#define I_CONNSYS_I2S_CH2 1
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#define I_GAIN0_OUT_CH1 6
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#define I_GAIN0_OUT_CH2 7
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#define I_GAIN1_OUT_CH1 8
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#define I_GAIN1_OUT_CH2 9
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#define I_GAIN2_OUT_CH1 10
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#define I_GAIN2_OUT_CH2 11
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#define I_GAIN3_OUT_CH1 12
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#define I_GAIN3_OUT_CH2 13
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#define I_STF_CH1 14
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#define I_ADDA_UL_CH1 16
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#define I_ADDA_UL_CH2 17
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#define I_ADDA_UL_CH3 18
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#define I_ADDA_UL_CH4 19
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#define I_UL_PROX_CH1 20
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#define I_UL_PROX_CH2 21
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#define I_ADDA_UL_CH5 24
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#define I_ADDA_UL_CH6 25
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#define I_DMIC0_CH1 28
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#define I_DMIC0_CH2 29
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#define I_DMIC1_CH1 30
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#define I_DMIC1_CH2 31
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/* in port define >= 32 */
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#define I_32_OFFSET 32
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#define I_DL0_CH1 (32 - I_32_OFFSET)
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#define I_DL0_CH2 (33 - I_32_OFFSET)
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#define I_DL1_CH1 (34 - I_32_OFFSET)
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#define I_DL1_CH2 (35 - I_32_OFFSET)
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#define I_DL2_CH1 (36 - I_32_OFFSET)
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#define I_DL2_CH2 (37 - I_32_OFFSET)
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#define I_DL3_CH1 (38 - I_32_OFFSET)
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#define I_DL3_CH2 (39 - I_32_OFFSET)
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#define I_DL4_CH1 (40 - I_32_OFFSET)
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#define I_DL4_CH2 (41 - I_32_OFFSET)
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#define I_DL5_CH1 (42 - I_32_OFFSET)
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#define I_DL5_CH2 (43 - I_32_OFFSET)
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#define I_DL6_CH1 (44 - I_32_OFFSET)
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#define I_DL6_CH2 (45 - I_32_OFFSET)
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#define I_DL7_CH1 (46 - I_32_OFFSET)
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#define I_DL7_CH2 (47 - I_32_OFFSET)
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#define I_DL8_CH1 (48 - I_32_OFFSET)
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#define I_DL8_CH2 (49 - I_32_OFFSET)
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#define I_DL_4CH_CH1 (50 - I_32_OFFSET)
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#define I_DL_4CH_CH2 (51 - I_32_OFFSET)
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#define I_DL_4CH_CH3 (52 - I_32_OFFSET)
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#define I_DL_4CH_CH4 (53 - I_32_OFFSET)
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#define I_DL_24CH_CH1 (54 - I_32_OFFSET)
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#define I_DL_24CH_CH2 (55 - I_32_OFFSET)
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#define I_DL_24CH_CH3 (56 - I_32_OFFSET)
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#define I_DL_24CH_CH4 (57 - I_32_OFFSET)
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#define I_DL_24CH_CH5 (58 - I_32_OFFSET)
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#define I_DL_24CH_CH6 (59 - I_32_OFFSET)
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#define I_DL_24CH_CH7 (60 - I_32_OFFSET)
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#define I_DL_24CH_CH8 (61 - I_32_OFFSET)
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/* in port define >= 64 */
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#define I_64_OFFSET 64
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#define I_DL23_CH1 (78 - I_64_OFFSET)
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#define I_DL23_CH2 (79 - I_64_OFFSET)
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#define I_DL24_CH1 (80 - I_64_OFFSET)
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#define I_DL24_CH2 (81 - I_64_OFFSET)
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#define I_DL25_CH1 (82 - I_64_OFFSET)
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#define I_DL25_CH2 (83 - I_64_OFFSET)
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#define I_DL26_CH1 (84 - I_64_OFFSET)
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#define I_DL26_CH2 (85 - I_64_OFFSET)
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/* in port define >= 128 */
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#define I_128_OFFSET 128
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#define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET)
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#define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET)
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#define I_PCM_1_CAP_CH1 (132 - I_128_OFFSET)
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#define I_PCM_1_CAP_CH2 (133 - I_128_OFFSET)
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#define I_I2SIN0_CH1 (134 - I_128_OFFSET)
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#define I_I2SIN0_CH2 (135 - I_128_OFFSET)
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#define I_I2SIN1_CH1 (136 - I_128_OFFSET)
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#define I_I2SIN1_CH2 (137 - I_128_OFFSET)
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#define I_I2SIN2_CH1 (138 - I_128_OFFSET)
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#define I_I2SIN2_CH2 (139 - I_128_OFFSET)
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#define I_I2SIN3_CH1 (140 - I_128_OFFSET)
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#define I_I2SIN3_CH2 (141 - I_128_OFFSET)
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#define I_I2SIN4_CH1 (142 - I_128_OFFSET)
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#define I_I2SIN4_CH2 (143 - I_128_OFFSET)
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#define I_I2SIN4_CH3 (144 - I_128_OFFSET)
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#define I_I2SIN4_CH4 (145 - I_128_OFFSET)
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#define I_I2SIN4_CH5 (146 - I_128_OFFSET)
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#define I_I2SIN4_CH6 (147 - I_128_OFFSET)
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#define I_I2SIN4_CH7 (148 - I_128_OFFSET)
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#define I_I2SIN4_CH8 (149 - I_128_OFFSET)
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/* in port define >= 160 */
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#define I_160_OFFSET 160
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#define I_I2SIN6_CH1 (166 - I_160_OFFSET)
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#define I_I2SIN6_CH2 (167 - I_160_OFFSET)
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/* in port define >= 192 */
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#define I_192_OFFSET 192
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#define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET)
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#define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET)
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#define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET)
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#define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET)
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#define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET)
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#define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET)
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#define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET)
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#define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET)
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#endif
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12068
sound/soc/mediatek/mt8196/mt8196-reg.h
Normal file
12068
sound/soc/mediatek/mt8196/mt8196-reg.h
Normal file
File diff suppressed because it is too large
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