github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-23 05:04:02 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amd/display: limit reuse dsc capable bootup timing

Browse Source 
[why]
Previous dcn315 BIOS has known dsc issue, not good for reuse their dsc settings.
this pre-OS dsc issue is fixed in dcn42 bios.
since there is no production bios update for older asic, limit our new code instead.

Reviewed-by: Mohit Bawa <mohit.bawa@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2026-06-26 11:39:04 -04:00 committed by Alex Deucher
parent d5164580a9
commit 72b9404802
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -1945,6 +1945,13 @@ bool dc_validate_boot_timing(const struct dc *dc,
struct display_stream_compressor *dsc = NULL;
struct dcn_dsc_state dsc_state = {0};
if (dc->ctx->dce_version < DCN_VERSION_4_2) {
/*vbios enabled eDP dsc for one of DCN315 only but it has known issue,
since there is no production bios update, block it there*/
DC_LOG_DEBUG("boot timing validation failed due to unsupported DSC on this ASIC\n");
return false;
}
/* Find DSC associated with this timing generator */
if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) {
dsc = dc->res_pool->dscs[tg_inst];