From 72b94048020ce40ea8502ab47cf6c7fb33cbd78f Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 26 Jun 2026 11:39:04 -0400 Subject: [PATCH] drm/amd/display: limit reuse dsc capable bootup timing [why] Previous dcn315 BIOS has known dsc issue, not good for reuse their dsc settings. this pre-OS dsc issue is fixed in dcn42 bios. since there is no production bios update for older asic, limit our new code instead. Reviewed-by: Mohit Bawa Signed-off-by: Charlene Liu Signed-off-by: George Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7934341b4715..dab19a360b02 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1945,6 +1945,13 @@ bool dc_validate_boot_timing(const struct dc *dc, struct display_stream_compressor *dsc = NULL; struct dcn_dsc_state dsc_state = {0}; + if (dc->ctx->dce_version < DCN_VERSION_4_2) { + /*vbios enabled eDP dsc for one of DCN315 only but it has known issue, + since there is no production bios update, block it there*/ + DC_LOG_DEBUG("boot timing validation failed due to unsupported DSC on this ASIC\n"); + return false; + } + /* Find DSC associated with this timing generator */ if (tg_inst < (unsigned int)dc->res_pool->res_cap->num_dsc) { dsc = dc->res_pool->dscs[tg_inst];