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spi: spi-fsl-dspi: Add config and regmaps for S32G platforms

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S32G adds SPI_{T,R}XFR4 and extends SPI_CTAR registers to 5. Add the
new regmaps, configs and bits.

dspi_volatile_ranges gets SPI_{T,R}XFR4 added which affects all
platforms, however they are further limited by dspi_yes_ranges.

Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-6-bea884630cfb@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Larisa Grigore 2025-05-22 15:51:35 +01:00 committed by Mark Brown
parent 1672b06532
commit 70c0b17ee3
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 36 additions and 3 deletions
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39
drivers/spi/spi-fsl-dspi.c
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@ -35,7 +35,7 @@
#define SPI_TCR 0x08
#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(2, 0)) * 4))
#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
#define SPI_CTAR_CPOL BIT(26)
#define SPI_CTAR_CPHA BIT(25)
@ -93,12 +93,14 @@
#define SPI_TXFR1 0x40
#define SPI_TXFR2 0x44
#define SPI_TXFR3 0x48
#define SPI_TXFR4 0x4C
#define SPI_RXFR0 0x7c
#define SPI_RXFR1 0x80
#define SPI_RXFR2 0x84
#define SPI_RXFR3 0x88
#define SPI_RXFR4 0x8C
#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(2, 0)) * 4))
#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
@ -136,6 +138,7 @@ enum {
LX2160A,
MCF5441X,
VF610,
S32G,
};
static const struct regmap_range dspi_yes_ranges[] = {
@ -147,15 +150,29 @@ static const struct regmap_range dspi_yes_ranges[] = {
regmap_reg_range(SPI_SREX, SPI_SREX),
};
static const struct regmap_range s32g_dspi_yes_ranges[] = {
regmap_reg_range(SPI_MCR, SPI_MCR),
regmap_reg_range(SPI_TCR, SPI_CTAR(5)),
regmap_reg_range(SPI_SR, SPI_TXFR4),
regmap_reg_range(SPI_RXFR0, SPI_RXFR4),
regmap_reg_range(SPI_CTARE(0), SPI_CTARE(5)),
regmap_reg_range(SPI_SREX, SPI_SREX),
};
static const struct regmap_access_table dspi_access_table = {
.yes_ranges = dspi_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(dspi_yes_ranges),
};
static const struct regmap_access_table s32g_dspi_access_table = {
.yes_ranges = s32g_dspi_yes_ranges,
.n_yes_ranges = ARRAY_SIZE(s32g_dspi_yes_ranges),
};
static const struct regmap_range dspi_volatile_ranges[] = {
regmap_reg_range(SPI_MCR, SPI_TCR),
regmap_reg_range(SPI_SR, SPI_SR),
regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
regmap_reg_range(SPI_PUSHR, SPI_RXFR4),
regmap_reg_range(SPI_SREX, SPI_SREX),
};
@ -167,6 +184,7 @@ static const struct regmap_access_table dspi_volatile_table = {
enum {
DSPI_REGMAP,
DSPI_XSPI_REGMAP,
S32G_DSPI_XSPI_REGMAP,
DSPI_PUSHR,
};
@ -189,6 +207,15 @@ static const struct regmap_config dspi_regmap_config[] = {
.rd_table = &dspi_access_table,
.wr_table = &dspi_access_table,
},
[S32G_DSPI_XSPI_REGMAP] = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = SPI_SREX,
.volatile_table = &dspi_volatile_table,
.wr_table = &s32g_dspi_access_table,
.rd_table = &s32g_dspi_access_table,
},
[DSPI_PUSHR] = {
.name = "pushr",
.reg_bits = 16,
@ -263,6 +290,12 @@ static const struct fsl_dspi_devtype_data devtype_data[] = {
.fifo_size = 16,
.regmap = &dspi_regmap_config[DSPI_REGMAP],
},
[S32G] = {
.trans_mode = DSPI_XSPI_MODE,
.max_clock_factor = 1,
.fifo_size = 5,
.regmap = &dspi_regmap_config[S32G_DSPI_XSPI_REGMAP],
},
};
struct fsl_dspi_dma {