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pinctrl: qcom: Add SM6350 LPASS LPI TLMM
Add support for the pin controller block on SM6350 Low Power Island. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> [linusw@kernel.org: fixed up Kconfig entry] Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Luca Weiss
Linus Walleij
parent
8e60ee5f94
commit
6ec81ace11
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@ -118,6 +118,15 @@ config PINCTRL_SM6115_LPASS_LPI
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Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
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(Low Power Island) found on the Qualcomm Technologies Inc SM6115 platform.
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config PINCTRL_SM6350_LPASS_LPI
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tristate "Qualcomm SM6350 LPASS LPI pin controller driver"
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depends on ARM64 || COMPILE_TEST
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depends on PINCTRL_LPASS_LPI
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help
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This is the pinctrl, pinmux, pinconf and gpiolib driver for the
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Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
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(Low Power Island) found on the Qualcomm Technologies Inc SM6350 platform.
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config PINCTRL_SM8250_LPASS_LPI
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tristate "Qualcomm SM8250 LPASS LPI pin controller driver"
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depends on ARM64 || COMPILE_TEST
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@ -65,6 +65,7 @@ obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
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obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
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obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
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obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o
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obj-$(CONFIG_PINCTRL_SM6350_LPASS_LPI) += pinctrl-sm6350-lpass-lpi.o
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obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o
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obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o
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obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
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149
drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c
Normal file
149
drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c
Normal file
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@ -0,0 +1,149 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com>
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*/
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#include <linux/gpio/driver.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "pinctrl-lpass-lpi.h"
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enum lpass_lpi_functions {
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LPI_MUX_dmic1_clk,
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LPI_MUX_dmic1_data,
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LPI_MUX_dmic2_clk,
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LPI_MUX_dmic2_data,
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LPI_MUX_dmic3_clk,
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LPI_MUX_dmic3_data,
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LPI_MUX_i2s1_clk,
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LPI_MUX_i2s1_data,
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LPI_MUX_i2s1_ws,
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LPI_MUX_i2s2_clk,
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LPI_MUX_i2s2_data,
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LPI_MUX_i2s2_ws,
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LPI_MUX_qua_mi2s_data,
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LPI_MUX_qua_mi2s_sclk,
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LPI_MUX_qua_mi2s_ws,
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LPI_MUX_swr_rx_clk,
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LPI_MUX_swr_rx_data,
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LPI_MUX_swr_tx_clk,
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LPI_MUX_swr_tx_data,
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LPI_MUX_wsa_swr_clk,
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LPI_MUX_wsa_swr_data,
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LPI_MUX_gpio,
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LPI_MUX__,
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};
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static const struct pinctrl_pin_desc sm6350_lpi_pins[] = {
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PINCTRL_PIN(0, "gpio0"),
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PINCTRL_PIN(1, "gpio1"),
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PINCTRL_PIN(2, "gpio2"),
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PINCTRL_PIN(3, "gpio3"),
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PINCTRL_PIN(4, "gpio4"),
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PINCTRL_PIN(5, "gpio5"),
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PINCTRL_PIN(6, "gpio6"),
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PINCTRL_PIN(7, "gpio7"),
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PINCTRL_PIN(8, "gpio8"),
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PINCTRL_PIN(9, "gpio9"),
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PINCTRL_PIN(10, "gpio10"),
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PINCTRL_PIN(11, "gpio11"),
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PINCTRL_PIN(12, "gpio12"),
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PINCTRL_PIN(13, "gpio13"),
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PINCTRL_PIN(14, "gpio14"),
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};
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static const char * const swr_tx_clk_groups[] = { "gpio0" };
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static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
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static const char * const swr_rx_clk_groups[] = { "gpio3" };
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static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
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static const char * const dmic1_clk_groups[] = { "gpio6" };
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static const char * const dmic1_data_groups[] = { "gpio7" };
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static const char * const dmic2_clk_groups[] = { "gpio8" };
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static const char * const dmic2_data_groups[] = { "gpio9" };
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static const char * const i2s2_clk_groups[] = { "gpio10" };
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static const char * const i2s2_ws_groups[] = { "gpio11" };
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static const char * const dmic3_clk_groups[] = { "gpio12" };
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static const char * const dmic3_data_groups[] = { "gpio13" };
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static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
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static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
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static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
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static const char * const i2s1_clk_groups[] = { "gpio6" };
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static const char * const i2s1_ws_groups[] = { "gpio7" };
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static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
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static const char * const wsa_swr_clk_groups[] = { "gpio10" };
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static const char * const wsa_swr_data_groups[] = { "gpio11" };
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static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
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static const struct lpi_pingroup sm6350_groups[] = {
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LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
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LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
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LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
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LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
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LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
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LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _),
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LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
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LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
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LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
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LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _),
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LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
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LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
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LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
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LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _),
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LPI_PINGROUP_SLEW_SPARE_1(14, 0, swr_tx_data, _, _, _),
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};
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static const struct lpi_function sm6350_functions[] = {
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LPI_FUNCTION(dmic1_clk),
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LPI_FUNCTION(dmic1_data),
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LPI_FUNCTION(dmic2_clk),
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LPI_FUNCTION(dmic2_data),
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LPI_FUNCTION(dmic3_clk),
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LPI_FUNCTION(dmic3_data),
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LPI_FUNCTION(i2s1_clk),
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LPI_FUNCTION(i2s1_data),
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LPI_FUNCTION(i2s1_ws),
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LPI_FUNCTION(i2s2_clk),
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LPI_FUNCTION(i2s2_data),
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LPI_FUNCTION(i2s2_ws),
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LPI_FUNCTION(qua_mi2s_data),
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LPI_FUNCTION(qua_mi2s_sclk),
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LPI_FUNCTION(qua_mi2s_ws),
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LPI_FUNCTION(swr_rx_clk),
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LPI_FUNCTION(swr_rx_data),
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LPI_FUNCTION(swr_tx_clk),
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LPI_FUNCTION(swr_tx_data),
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LPI_FUNCTION(wsa_swr_clk),
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LPI_FUNCTION(wsa_swr_data),
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};
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static const struct lpi_pinctrl_variant_data sm6350_lpi_data = {
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.pins = sm6350_lpi_pins,
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.npins = ARRAY_SIZE(sm6350_lpi_pins),
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.groups = sm6350_groups,
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.ngroups = ARRAY_SIZE(sm6350_groups),
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.functions = sm6350_functions,
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.nfunctions = ARRAY_SIZE(sm6350_functions),
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};
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static const struct of_device_id lpi_pinctrl_of_match[] = {
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{
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.compatible = "qcom,sm6350-lpass-lpi-pinctrl",
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.data = &sm6350_lpi_data,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
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static struct platform_driver lpi_pinctrl_driver = {
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.driver = {
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.name = "qcom-sm6350-lpass-lpi-pinctrl",
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.of_match_table = lpi_pinctrl_of_match,
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},
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.probe = lpi_pinctrl_probe,
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.remove = lpi_pinctrl_remove,
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};
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module_platform_driver(lpi_pinctrl_driver);
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MODULE_DESCRIPTION("Qualcomm SM6350 LPI GPIO pin control driver");
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MODULE_LICENSE("GPL");
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