pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control

On some platforms like SM6350 (Bitra), some pins have their slew
controlled with the SPARE_1 register. Add support for that.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Luca Weiss 2026-04-30 09:10:42 +02:00 committed by Linus Walleij
parent 8e9121cc76
commit 8e60ee5f94
2 changed files with 22 additions and 0 deletions

View File

@ -220,6 +220,8 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
else if (g->slew_base_spare_1)
reg = pctrl->slew_base + LPI_SPARE_1_REG;
else
reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;

View File

@ -16,6 +16,7 @@ struct platform_device;
struct pinctrl_pin_desc;
#define LPI_SLEW_RATE_CTL_REG 0xa000
#define LPI_SPARE_1_REG 0xc000
#define LPI_TLMM_REG_OFFSET 0x1000
#define LPI_SLEW_RATE_MAX 0x03
#define LPI_SLEW_BITS_SIZE 0x02
@ -47,6 +48,7 @@ struct pinctrl_pin_desc;
{ \
.pin = id, \
.slew_offset = soff, \
.slew_base_spare_1 = false, \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
@ -62,6 +64,7 @@ struct pinctrl_pin_desc;
{ \
.pin = id, \
.slew_offset = soff, \
.slew_base_spare_1 = false, \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
@ -73,6 +76,22 @@ struct pinctrl_pin_desc;
.pin_offset = poff, \
}
#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \
{ \
.pin = id, \
.slew_offset = soff, \
.slew_base_spare_1 = true, \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
LPI_MUX_##f2, \
LPI_MUX_##f3, \
LPI_MUX_##f4, \
}, \
.nfuncs = 5, \
.pin_offset = 0, \
}
/*
* Slew rate control is done in the same register as rest of the
* pin configuration.
@ -87,6 +106,7 @@ struct lpi_pingroup {
unsigned int *funcs;
unsigned int nfuncs;
unsigned int pin_offset;
bool slew_base_spare_1;
};
struct lpi_function {