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pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control
On some platforms like SM6350 (Bitra), some pins have their slew controlled with the SPARE_1 register. Add support for that. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
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@ -220,6 +220,8 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
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if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
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reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
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else if (g->slew_base_spare_1)
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reg = pctrl->slew_base + LPI_SPARE_1_REG;
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else
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reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
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@ -16,6 +16,7 @@ struct platform_device;
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struct pinctrl_pin_desc;
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#define LPI_SLEW_RATE_CTL_REG 0xa000
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#define LPI_SPARE_1_REG 0xc000
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#define LPI_TLMM_REG_OFFSET 0x1000
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#define LPI_SLEW_RATE_MAX 0x03
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#define LPI_SLEW_BITS_SIZE 0x02
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@ -47,6 +48,7 @@ struct pinctrl_pin_desc;
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{ \
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.pin = id, \
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.slew_offset = soff, \
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.slew_base_spare_1 = false, \
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.funcs = (int[]){ \
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LPI_MUX_gpio, \
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LPI_MUX_##f1, \
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@ -62,6 +64,7 @@ struct pinctrl_pin_desc;
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{ \
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.pin = id, \
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.slew_offset = soff, \
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.slew_base_spare_1 = false, \
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.funcs = (int[]){ \
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LPI_MUX_gpio, \
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LPI_MUX_##f1, \
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@ -73,6 +76,22 @@ struct pinctrl_pin_desc;
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.pin_offset = poff, \
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}
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#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \
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{ \
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.pin = id, \
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.slew_offset = soff, \
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.slew_base_spare_1 = true, \
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.funcs = (int[]){ \
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LPI_MUX_gpio, \
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LPI_MUX_##f1, \
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LPI_MUX_##f2, \
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LPI_MUX_##f3, \
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LPI_MUX_##f4, \
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}, \
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.nfuncs = 5, \
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.pin_offset = 0, \
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}
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/*
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* Slew rate control is done in the same register as rest of the
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* pin configuration.
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@ -87,6 +106,7 @@ struct lpi_pingroup {
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unsigned int *funcs;
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unsigned int nfuncs;
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unsigned int pin_offset;
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bool slew_base_spare_1;
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};
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struct lpi_function {
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