github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-09-25 09:41:03 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern

Browse Source 
The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain
the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins),
but a regex character class cannot express a multi-digit decimal range.
Replace the bogus character class with an explicit alternation that
enumerates the two-digit decimal values 00..77.

Fixes: 03d4a10040 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/e742b7da70c2bf10650a81e537f1b90d76799416.1783516336.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Michal Simek 2026-07-08 15:12:23 +02:00
parent 959393e81c
commit 6e32cb10cf
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
View File

@ -116,7 +116,7 @@ allOf:
- const: pss_alt_ref_clk
- const: aux_ref_clk
- const: gt_crx_ref_clk
- pattern: "^mio_clk[00-77]+.*$"
- pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$"
- pattern: "gem[0-3]+_emio_clk.*$"
- pattern: "swdt[0-1]+_ext_clk.*$"