From 6e32cb10cf32e60cf40ad0baa37c54969f10101f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:23 +0200 Subject: [PATCH] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins), but a regex character class cannot express a multi-digit decimal range. Replace the bogus character class with an explicit alternation that enumerates the two-digit decimal values 00..77. Fixes: 03d4a1004053 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml") Acked-by: Conor Dooley Link: https://patch.msgid.link/e742b7da70c2bf10650a81e537f1b90d76799416.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index bef109d163a8..b1623c2ab0f6 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -116,7 +116,7 @@ allOf: - const: pss_alt_ref_clk - const: aux_ref_clk - const: gt_crx_ref_clk - - pattern: "^mio_clk[00-77]+.*$" + - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" - pattern: "gem[0-3]+_emio_clk.*$" - pattern: "swdt[0-1]+_ext_clk.*$"