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dt-bindings: clock: renesas,r8a78000-cpg: Add MSIOF clocks

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Add definitions for the functional clock parents of the
Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas
R-Car X5H (R8A78000) SoC:
  - MSO_SCP_MAIN is the functional clock parent for MSIOF[0-3],
  - MSOCK_PERW_BUS is the functional clock parent for MSIOF[4-7].

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/9a5f4e324e3b67d367f850264cbaf7e830cec182.1790325809.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2026-09-25 10:53:29 +02:00
parent cee9395acd
commit 6c09280e00
1 changed files with 2 additions and 0 deletions
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include/dt-bindings/clock/renesas,r8a78000-cpg.h
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@ -10,5 +10,7 @@
#define R8A78000_CPG_SGASYNCD4_PERW_BUS 0
#define R8A78000_CPG_SGASYNCD8_PERW_BUS 1
#define R8A78000_CPG_SGASYNCD16_PERW_BUS 2
#define R8A78000_CPG_MSO_SCP_MAIN 3
#define R8A78000_CPG_MSOCK_PERW_BUS 4
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */