From 6c09280e00e4bb7a43badcec9dec8d41fbb9b5e0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 25 Sep 2026 10:53:29 +0200 Subject: [PATCH] dt-bindings: clock: renesas,r8a78000-cpg: Add MSIOF clocks Add definitions for the functional clock parents of the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car X5H (R8A78000) SoC: - MSO_SCP_MAIN is the functional clock parent for MSIOF[0-3], - MSOCK_PERW_BUS is the functional clock parent for MSIOF[4-7]. Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/9a5f4e324e3b67d367f850264cbaf7e830cec182.1790325809.git.geert+renesas@glider.be --- include/dt-bindings/clock/renesas,r8a78000-cpg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h index 7fd09a3fb353..14b3885f2d99 100644 --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h @@ -10,5 +10,7 @@ #define R8A78000_CPG_SGASYNCD4_PERW_BUS 0 #define R8A78000_CPG_SGASYNCD8_PERW_BUS 1 #define R8A78000_CPG_SGASYNCD16_PERW_BUS 2 +#define R8A78000_CPG_MSO_SCP_MAIN 3 +#define R8A78000_CPG_MSOCK_PERW_BUS 4 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */