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KVM: x86/mmu: parameterize update_permission_bitmask()
Make it possible to apply the computation loop to both guest and shadow PTEs formats; the latter do not have an extended role, so pass the four parameters to the function one by one. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -5658,18 +5658,15 @@ reset_ept_shadow_zero_bits_mask(struct kvm_mmu *context, bool execonly)
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(14 & (access) ? 1 << 14 : 0) | \
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(15 & (access) ? 1 << 15 : 0))
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static void update_permission_bitmask(struct kvm_pagewalk *pw, bool tdp, bool ept)
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static void __update_permission_bitmask(struct kvm_page_format *fmt, bool tdp,
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bool ept, bool cr4_smep, bool cr4_smap,
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bool cr0_wp, bool efer_nx)
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{
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unsigned index;
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const u16 w = ACC_BITS_MASK(ACC_WRITE_MASK);
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const u16 r = ACC_BITS_MASK(ACC_READ_MASK);
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bool cr4_smep = is_cr4_smep(pw);
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bool cr4_smap = is_cr4_smap(pw);
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bool cr0_wp = is_cr0_wp(pw);
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bool efer_nx = is_efer_nx(pw);
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/*
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* In hardware, page fault error codes are generated (as the name
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* suggests) on any kind of page fault. permission_fault() and
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@ -5682,7 +5679,7 @@ static void update_permission_bitmask(struct kvm_pagewalk *pw, bool tdp, bool ep
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* permission_fault() to indicate accesses that are *not* subject to
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* SMAP restrictions.
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*/
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for (index = 0; index < ARRAY_SIZE(pw->fmt.permissions); ++index) {
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for (index = 0; index < ARRAY_SIZE(fmt->permissions); ++index) {
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unsigned pfec = index << 1;
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/*
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@ -5756,10 +5753,17 @@ static void update_permission_bitmask(struct kvm_pagewalk *pw, bool tdp, bool ep
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smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
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}
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pw->fmt.permissions[index] = ff | uf | wf | rf | smapf;
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fmt->permissions[index] = ff | uf | wf | rf | smapf;
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}
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}
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static void update_permission_bitmask(struct kvm_pagewalk *w, bool tdp, bool ept)
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{
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__update_permission_bitmask(&w->fmt, tdp, ept,
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is_cr4_smep(w), is_cr4_smap(w),
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is_cr0_wp(w), is_efer_nx(w));
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}
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/*
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* PKU is an additional mechanism by which the paging controls access to
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* user-mode addresses based on the value in the PKRU register. Protection
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