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KVM: x86/mmu: merge struct rsvd_bits_validate into struct kvm_page_format
This remove one level of indirection, and adds the data for the permission bitmask machinery to struct kvm_mmu. This way, it will be possible to reuse the permission bitmasks for SPTEs as well. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
72f734a435
commit
c71239d463
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@ -487,9 +487,24 @@ struct kvm_pio_request {
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#define PT64_ROOT_MAX_LEVEL 5
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struct rsvd_bits_validate {
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struct kvm_page_format {
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u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
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u64 bad_mt_xwr;
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/*
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* The pkru_mask indicates if protection key checks are needed. It
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* consists of 16 domains indexed by page fault error code bits [4:1],
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* with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
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* Each domain has 2 bits which are ANDed with AD and WD from PKRU.
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*/
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u32 pkru_mask;
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/*
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* Bitmap; bit set = permission fault
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* Array index: page fault error code [4:1]
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* Bit index: pte permissions in ACC_* format
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*/
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u16 permissions[16];
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};
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struct kvm_mmu_root_info {
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@ -516,25 +531,6 @@ struct kvm_page_fault;
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* and 2-level 32-bit). The kvm_pagewalk structure abstracts the details of the
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* current mmu mode.
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*/
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struct kvm_page_format {
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struct rsvd_bits_validate guest_rsvd_check;
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/*
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* The pkru_mask indicates if protection key checks are needed. It
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* consists of 16 domains indexed by page fault error code bits [4:1],
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* with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
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* Each domain has 2 bits which are ANDed with AD and WD from PKRU.
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*/
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u32 pkru_mask;
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/*
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* Bitmap; bit set = permission fault
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* Array index: page fault error code [4:1]
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* Bit index: pte permissions in ACC_* format
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*/
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u16 permissions[16];
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};
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struct kvm_pagewalk {
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unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu);
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u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
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@ -570,7 +566,7 @@ struct kvm_mmu {
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* bits include not only hardware reserved bits but also
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* the bits spte never used.
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*/
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struct rsvd_bits_validate shadow_zero_check;
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struct kvm_page_format fmt;
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};
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enum pmc_type {
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@ -4446,7 +4446,7 @@ static int get_sptes_lockless(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes,
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static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
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{
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u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
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struct rsvd_bits_validate *rsvd_check;
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struct kvm_page_format *rsvd_check;
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int root, leaf, level;
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bool reserved = false;
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@ -4467,7 +4467,7 @@ static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
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if (!is_shadow_present_pte(sptes[leaf]))
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leaf++;
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rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
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rsvd_check = &vcpu->arch.mmu->fmt;
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for (level = root; level >= leaf; level--)
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reserved |= is_rsvd_spte(rsvd_check, sptes[level], level);
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@ -5387,7 +5387,7 @@ static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
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#include "paging_tmpl.h"
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#undef PTTYPE
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static void __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
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static void __reset_rsvds_bits_mask(struct kvm_page_format *fmt,
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u64 pa_bits_rsvd, int level, bool nx,
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bool gbpages, bool pse, bool amd)
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{
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@ -5395,7 +5395,7 @@ static void __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
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u64 nonleaf_bit8_rsvd = 0;
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u64 high_bits_rsvd;
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rsvd_check->bad_mt_xwr = 0;
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fmt->bad_mt_xwr = 0;
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if (!gbpages)
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gbpages_bit_rsvd = rsvd_bits(7, 7);
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@ -5419,59 +5419,59 @@ static void __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
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switch (level) {
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case PT32_ROOT_LEVEL:
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/* no rsvd bits for 2 level 4K page table entries */
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rsvd_check->rsvd_bits_mask[0][1] = 0;
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rsvd_check->rsvd_bits_mask[0][0] = 0;
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rsvd_check->rsvd_bits_mask[1][0] =
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rsvd_check->rsvd_bits_mask[0][0];
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fmt->rsvd_bits_mask[0][1] = 0;
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fmt->rsvd_bits_mask[0][0] = 0;
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fmt->rsvd_bits_mask[1][0] =
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fmt->rsvd_bits_mask[0][0];
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if (!pse) {
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rsvd_check->rsvd_bits_mask[1][1] = 0;
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fmt->rsvd_bits_mask[1][1] = 0;
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break;
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}
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if (is_cpuid_PSE36())
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/* 36bits PSE 4MB page */
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rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
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fmt->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
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else
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/* 32 bits PSE 4MB page */
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rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
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fmt->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
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break;
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case PT32E_ROOT_LEVEL:
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rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
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fmt->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
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high_bits_rsvd |
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rsvd_bits(5, 8) |
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rsvd_bits(1, 2); /* PDPTE */
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rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
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rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
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rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
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fmt->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
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fmt->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
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fmt->rsvd_bits_mask[1][1] = high_bits_rsvd |
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rsvd_bits(13, 20); /* large page */
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rsvd_check->rsvd_bits_mask[1][0] =
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rsvd_check->rsvd_bits_mask[0][0];
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fmt->rsvd_bits_mask[1][0] =
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fmt->rsvd_bits_mask[0][0];
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break;
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case PT64_ROOT_5LEVEL:
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rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
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fmt->rsvd_bits_mask[0][4] = high_bits_rsvd |
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nonleaf_bit8_rsvd |
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rsvd_bits(7, 7);
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rsvd_check->rsvd_bits_mask[1][4] =
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rsvd_check->rsvd_bits_mask[0][4];
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fmt->rsvd_bits_mask[1][4] =
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fmt->rsvd_bits_mask[0][4];
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fallthrough;
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case PT64_ROOT_4LEVEL:
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rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
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fmt->rsvd_bits_mask[0][3] = high_bits_rsvd |
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nonleaf_bit8_rsvd |
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rsvd_bits(7, 7);
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rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
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fmt->rsvd_bits_mask[0][2] = high_bits_rsvd |
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gbpages_bit_rsvd;
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rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
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rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
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rsvd_check->rsvd_bits_mask[1][3] =
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rsvd_check->rsvd_bits_mask[0][3];
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rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
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fmt->rsvd_bits_mask[0][1] = high_bits_rsvd;
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fmt->rsvd_bits_mask[0][0] = high_bits_rsvd;
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fmt->rsvd_bits_mask[1][3] =
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fmt->rsvd_bits_mask[0][3];
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fmt->rsvd_bits_mask[1][2] = high_bits_rsvd |
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gbpages_bit_rsvd |
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rsvd_bits(13, 29);
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rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
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fmt->rsvd_bits_mask[1][1] = high_bits_rsvd |
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rsvd_bits(13, 20); /* large page */
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rsvd_check->rsvd_bits_mask[1][0] =
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rsvd_check->rsvd_bits_mask[0][0];
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fmt->rsvd_bits_mask[1][0] =
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fmt->rsvd_bits_mask[0][0];
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break;
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}
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}
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@ -5479,7 +5479,7 @@ static void __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check,
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static void reset_guest_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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struct kvm_pagewalk *w)
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{
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__reset_rsvds_bits_mask(&w->fmt.guest_rsvd_check,
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__reset_rsvds_bits_mask(&w->fmt,
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vcpu->arch.reserved_gpa_bits,
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w->cpu_role.base.level, is_efer_nx(w),
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guest_cpu_cap_has(vcpu, X86_FEATURE_GBPAGES),
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@ -5487,7 +5487,7 @@ static void reset_guest_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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guest_cpuid_is_amd_compatible(vcpu));
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}
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static void __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
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static void __reset_rsvds_bits_mask_ept(struct kvm_page_format *fmt,
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u64 pa_bits_rsvd, bool execonly,
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int huge_page_level)
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{
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@ -5500,18 +5500,18 @@ static void __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
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if (huge_page_level < PG_LEVEL_2M)
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large_2m_rsvd = rsvd_bits(7, 7);
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rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
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rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
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rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6) | large_1g_rsvd;
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rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6) | large_2m_rsvd;
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rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
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fmt->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
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fmt->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
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fmt->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6) | large_1g_rsvd;
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fmt->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6) | large_2m_rsvd;
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fmt->rsvd_bits_mask[0][0] = high_bits_rsvd;
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/* large page */
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rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
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rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
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rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29) | large_1g_rsvd;
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rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20) | large_2m_rsvd;
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rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
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fmt->rsvd_bits_mask[1][4] = fmt->rsvd_bits_mask[0][4];
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fmt->rsvd_bits_mask[1][3] = fmt->rsvd_bits_mask[0][3];
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fmt->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29) | large_1g_rsvd;
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fmt->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20) | large_2m_rsvd;
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fmt->rsvd_bits_mask[1][0] = fmt->rsvd_bits_mask[0][0];
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bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
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bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
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@ -5522,13 +5522,13 @@ static void __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
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/* bits 0..2 must not be 100 unless VMX capabilities allow it */
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bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
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}
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rsvd_check->bad_mt_xwr = bad_mt_xwr;
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fmt->bad_mt_xwr = bad_mt_xwr;
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}
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static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
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bool execonly, int huge_page_level)
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{
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__reset_rsvds_bits_mask_ept(&vcpu->arch.ngpa_walk.fmt.guest_rsvd_check,
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__reset_rsvds_bits_mask_ept(&vcpu->arch.ngpa_walk.fmt,
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vcpu->arch.reserved_gpa_bits, execonly,
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huge_page_level);
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}
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@ -5550,13 +5550,13 @@ static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
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bool is_amd = true;
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/* KVM doesn't use 2-level page tables for the shadow MMU. */
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bool is_pse = false;
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struct rsvd_bits_validate *shadow_zero_check;
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struct kvm_page_format *fmt;
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int i;
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WARN_ON_ONCE(context->root_role.level < PT32E_ROOT_LEVEL);
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shadow_zero_check = &context->shadow_zero_check;
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__reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
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fmt = &context->fmt;
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__reset_rsvds_bits_mask(fmt, reserved_hpa_bits(),
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context->root_role.level,
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context->root_role.efer_nx,
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guest_cpu_cap_has(vcpu, X86_FEATURE_GBPAGES),
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@ -5572,10 +5572,10 @@ static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
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* Bits in shadow_me_mask but not in shadow_me_value are
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* not allowed to be set.
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*/
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shadow_zero_check->rsvd_bits_mask[0][i] |= shadow_me_mask;
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shadow_zero_check->rsvd_bits_mask[1][i] |= shadow_me_mask;
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shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_value;
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shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_value;
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fmt->rsvd_bits_mask[0][i] |= shadow_me_mask;
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fmt->rsvd_bits_mask[1][i] |= shadow_me_mask;
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fmt->rsvd_bits_mask[0][i] &= ~shadow_me_value;
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fmt->rsvd_bits_mask[1][i] &= ~shadow_me_value;
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}
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}
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@ -5592,18 +5592,18 @@ static inline bool boot_cpu_is_amd(void)
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*/
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static void reset_tdp_shadow_zero_bits_mask(struct kvm_mmu *context)
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{
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struct rsvd_bits_validate *shadow_zero_check;
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struct kvm_page_format *fmt;
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int i;
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shadow_zero_check = &context->shadow_zero_check;
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fmt = &context->fmt;
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if (boot_cpu_is_amd())
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__reset_rsvds_bits_mask(shadow_zero_check, reserved_hpa_bits(),
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__reset_rsvds_bits_mask(fmt, reserved_hpa_bits(),
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context->root_role.level, true,
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boot_cpu_has(X86_FEATURE_GBPAGES),
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false, true);
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else
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__reset_rsvds_bits_mask_ept(shadow_zero_check,
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__reset_rsvds_bits_mask_ept(fmt,
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reserved_hpa_bits(), false,
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max_huge_page_level);
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@ -5611,8 +5611,8 @@ static void reset_tdp_shadow_zero_bits_mask(struct kvm_mmu *context)
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return;
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for (i = context->root_role.level; --i >= 0;) {
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shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
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shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
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fmt->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
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fmt->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
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}
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}
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@ -5623,7 +5623,7 @@ static void reset_tdp_shadow_zero_bits_mask(struct kvm_mmu *context)
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static void
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reset_ept_shadow_zero_bits_mask(struct kvm_mmu *context, bool execonly)
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{
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__reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
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__reset_rsvds_bits_mask_ept(&context->fmt,
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reserved_hpa_bits(), execonly,
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max_huge_page_level);
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}
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@ -138,19 +138,19 @@ static inline int FNAME(is_present_gpte)(struct kvm_pagewalk *w,
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#endif
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}
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static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte)
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static bool FNAME(is_bad_mt_xwr)(struct kvm_page_format *fmt, u64 gpte)
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{
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#if PTTYPE != PTTYPE_EPT
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return false;
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#else
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return __is_bad_mt_xwr(rsvd_check, gpte);
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return __is_bad_mt_xwr(fmt, gpte);
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#endif
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}
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static bool FNAME(is_rsvd_bits_set)(struct kvm_page_format *fmt, u64 gpte, int level)
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{
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return __is_rsvd_bits_set(&fmt->guest_rsvd_check, gpte, level) ||
|
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FNAME(is_bad_mt_xwr)(&fmt->guest_rsvd_check, gpte);
|
||||
return __is_rsvd_bits_set(fmt, gpte, level) ||
|
||||
FNAME(is_bad_mt_xwr)(fmt, gpte);
|
||||
}
|
||||
|
||||
static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
|
||||
|
|
|
|||
|
|
@ -280,9 +280,9 @@ bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
|
|||
if (prefetch && !synchronizing)
|
||||
spte = mark_spte_for_access_track(spte);
|
||||
|
||||
WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level),
|
||||
WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->fmt, spte, level),
|
||||
"spte = 0x%llx, level = %d, rsvd bits = 0x%llx", spte, level,
|
||||
get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level));
|
||||
get_rsvd_bits(&vcpu->arch.mmu->fmt, spte, level));
|
||||
|
||||
/*
|
||||
* Mark the memslot dirty *after* modifying it for access tracking.
|
||||
|
|
|
|||
|
|
@ -378,33 +378,33 @@ static inline bool is_accessed_spte(u64 spte)
|
|||
return spte & shadow_accessed_mask;
|
||||
}
|
||||
|
||||
static inline u64 get_rsvd_bits(struct rsvd_bits_validate *rsvd_check, u64 pte,
|
||||
static inline u64 get_rsvd_bits(struct kvm_page_format *fmt, u64 pte,
|
||||
int level)
|
||||
{
|
||||
int bit7 = (pte >> 7) & 1;
|
||||
|
||||
return rsvd_check->rsvd_bits_mask[bit7][level-1];
|
||||
return fmt->rsvd_bits_mask[bit7][level-1];
|
||||
}
|
||||
|
||||
static inline bool __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check,
|
||||
static inline bool __is_rsvd_bits_set(struct kvm_page_format *fmt,
|
||||
u64 pte, int level)
|
||||
{
|
||||
return pte & get_rsvd_bits(rsvd_check, pte, level);
|
||||
return pte & get_rsvd_bits(fmt, pte, level);
|
||||
}
|
||||
|
||||
static inline bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check,
|
||||
static inline bool __is_bad_mt_xwr(struct kvm_page_format *fmt,
|
||||
u64 pte)
|
||||
{
|
||||
if (pte & VMX_EPT_USER_EXECUTABLE_MASK)
|
||||
pte |= VMX_EPT_EXECUTABLE_MASK;
|
||||
return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
|
||||
return fmt->bad_mt_xwr & BIT_ULL(pte & 0x3f);
|
||||
}
|
||||
|
||||
static __always_inline bool is_rsvd_spte(struct rsvd_bits_validate *rsvd_check,
|
||||
static __always_inline bool is_rsvd_spte(struct kvm_page_format *fmt,
|
||||
u64 spte, int level)
|
||||
{
|
||||
return __is_bad_mt_xwr(rsvd_check, spte) ||
|
||||
__is_rsvd_bits_set(rsvd_check, spte, level);
|
||||
return __is_bad_mt_xwr(fmt, spte) ||
|
||||
__is_rsvd_bits_set(fmt, spte, level);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -8719,7 +8719,7 @@ __init int vmx_hardware_setup(void)
|
|||
|
||||
/*
|
||||
* Setup shadow_me_value/shadow_me_mask to include MKTME KeyID
|
||||
* bits to shadow_zero_check.
|
||||
* bits into the MMU's struct kvm_page_format.
|
||||
*/
|
||||
vmx_setup_me_spte_mask();
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user