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Tenstorrent device tree for v7.2

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Add a riscv,pmu node to the Tenstorrent Blackhole SoC device tree. This
 enables OpenSBI to expose the SBI PMU extension, allowing Linux perf to
 use the 4 programmable counters (mhpmcounter3-6) across 3 event classes:
 instruction commit, microarchitectural, and memory system events.
 
 Extend the RISC-V IOMMU device tree bindings to document the Tenstorrent
 IOMMU used in the Tenstorrent Atlantis SoC. A second register range is
 added which contains M-mode only registers like PMAs and PMPs. The
 binding will be used by OpenSBI and potentially other M-mode software.
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Merge tag 'tenstorrent-dt-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux into soc/dt

Tenstorrent device tree for v7.2

Add a riscv,pmu node to the Tenstorrent Blackhole SoC device tree. This
enables OpenSBI to expose the SBI PMU extension, allowing Linux perf to
use the 4 programmable counters (mhpmcounter3-6) across 3 event classes:
instruction commit, microarchitectural, and memory system events.

Extend the RISC-V IOMMU device tree bindings to document the Tenstorrent
IOMMU used in the Tenstorrent Atlantis SoC. A second register range is
added which contains M-mode only registers like PMAs and PMPs. The
binding will be used by OpenSBI and potentially other M-mode software.

* tag 'tenstorrent-dt-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux:
  dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU
  riscv: dts: tenstorrent: Add PMU node to blackhole for Linux perf support

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-06-09 13:46:11 +02:00
commit 6b2b89b1bc
2 changed files with 99 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
View File

@ -32,22 +32,35 @@ properties:
# should be specified along with 'reg' property providing MMIO location.
compatible:
oneOf:
- items:
- description: Platform (non-PCIe) IOMMU implementations
items:
- enum:
- qemu,riscv-iommu
- tenstorrent,riscv-iommu
- const: riscv,iommu
- items:
- description: PCIe IOMMU implementations
items:
- enum:
- pci1efd,edf1
- const: riscv,pci-iommu
reg:
maxItems: 1
description:
For non-PCI devices this represents base address and size of for the
IOMMU memory mapped registers interface.
For PCI IOMMU hardware implementation this should represent an address
of the IOMMU, as defined in the PCI Bus Binding reference.
minItems: 1
items:
- description:
For non-PCI devices, base address and size of the IOMMU memory
mapped registers interface. For PCI IOMMU hardware
implementation, an address of the IOMMU, as defined in the PCI
Bus Binding reference.
- description:
Region containing platform specific MMRs for machine-mode
configuration, such as PMA and PMP registers.
reg-names:
minItems: 1
items:
- const: base
- const: machine
'#iommu-cells':
const: 1
@ -75,6 +88,26 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- tenstorrent,riscv-iommu
then:
properties:
reg:
minItems: 2
reg-names:
minItems: 2
else:
properties:
reg:
maxItems: 1
reg-names:
maxItems: 1
examples:
- |+
/* Example 1 (IOMMU device with wired interrupts) */
@ -145,3 +178,13 @@ examples:
};
};
};
- |+
/* Example 5 (Tenstorrent IOMMU device with MSIs) */
iommu5: iommu@d2020000 {
compatible = "tenstorrent,riscv-iommu", "riscv,iommu";
reg = <0xd2020000 0x10000>, <0xaa000000 0x10000>;
reg-names = "base", "machine";
msi-parent = <&imsics_smode>;
#iommu-cells = <1>;
};

48
arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
View File

@ -77,6 +77,54 @@ cpu3_intc: interrupt-controller {
};
};
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmevent =
/* SBI_PMU_HW_CPU_CYCLES -> CPU cycles */
<0x00001 0x00000000 0x0001>,
/* SBI_PMU_HW_INSTRUCTIONS -> Instructions executed */
<0x00002 0x00000000 0x0004>,
/* SBI_PMU_HW_CACHE_REFERENCES -> I-cache/ITIM busy | D-cache/DTIM busy */
<0x00003 0x00000000 0x1801>,
/* SBI_PMU_HW_CACHE_MISSES -> I-cache miss | D-cache miss */
<0x00004 0x00000000 0x0302>,
/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
<0x00005 0x00000000 0x4000>,
/*
* SBI_PMU_HW_BRANCH_MISSES ->
* Branch direction misprediction | Branch/jump target misprediction
*/
<0x00006 0x00000000 0x6001>,
/* L1D_READ_MISS -> Data cache miss or MMIO access */
<0x10001 0x00000000 0x0202>,
/* L1D_WRITE_ACCESS -> Data cache write-back */
<0x10002 0x00000000 0x0402>,
/* L1I_READ_MISS -> Instruction cache miss */
<0x10009 0x00000000 0x0102>,
/* LL_READ_MISS -> UTLB miss */
<0x10011 0x00000000 0x2002>,
/* DTLB_READ_MISS -> Data TLB miss */
<0x10019 0x00000000 0x1002>,
/* ITLB_READ_MISS -> Instruction TLB miss */
<0x10021 0x00000000 0x0802>;
riscv,event-to-mhpmcounters =
<0x00001 0x00001 0x01>,
<0x00002 0x00002 0x04>,
<0x00003 0x00006 0x78>,
<0x10001 0x10002 0x78>,
<0x10009 0x10009 0x78>,
<0x10011 0x10011 0x78>,
<0x10019 0x10019 0x78>,
<0x10021 0x10021 0x78>;
riscv,raw-event-to-mhpmcounters =
/* Class 0: Instruction Commit Events, bits 8-25 variant */
<0x0 0x0 0xffffffff 0xfc0000ff 0x78>,
/* Class 1: Microarchitectural Events, bits 8-18 variant */
<0x0 0x1 0xffffffff 0xfff800ff 0x78>,
/* Class 2: Memory System Events, bits 8-13 variant */
<0x0 0x2 0xffffffff 0xffffc0ff 0x78>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;