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arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores

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Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU
topology and PSCI support for enabling CPU cores.

R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters.

Based on a patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ccb55458bd87f8ba70d28c61bcc254f22184824c.1668429870.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-11-14 13:49:01 +01:00
parent f08407210d
commit 68c9c53d45
1 changed files with 65 additions and 5 deletions
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70
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
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@ -18,12 +18,60 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&a76_0>;
};
core1 {
cpu = <&a76_1>;
};
};
cluster1 {
core0 {
cpu = <&a76_2>;
};
core1 {
cpu = <&a76_3>;
};
};
};
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA76_0>;
enable-method = "psci";
};
a76_1: cpu@100 {
compatible = "arm,cortex-a76";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
next-level-cache = <&L3_CA76_0>;
enable-method = "psci";
};
a76_2: cpu@10000 {
compatible = "arm,cortex-a76";
reg = <0x10000>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
next-level-cache = <&L3_CA76_1>;
enable-method = "psci";
};
a76_3: cpu@10100 {
compatible = "arm,cortex-a76";
reg = <0x10100>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
next-level-cache = <&L3_CA76_1>;
enable-method = "psci";
};
L3_CA76_0: cache-controller-0 {
@ -32,6 +80,18 @@ L3_CA76_0: cache-controller-0 {
cache-unified;
cache-level = <3>;
};
L3_CA76_1: cache-controller-1 {
compatible = "cache";
power-domains = <&sysc R8A779G0_PD_A2E0D1>;
cache-unified;
cache-level = <3>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
extal_clk: extal {
@ -1088,7 +1148,7 @@ gic: interrupt-controller@f1000000 {
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
prr: chipid@fff00044 {
@ -1099,9 +1159,9 @@ prr: chipid@fff00044 {
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};