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riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers

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StarFive JH7110 contains a Cadence USB2.0+USB3.0 controller IP block that
may exclusively use pciephy0 for USB3.0 connectivity. Add the register
offsets for the driver to enable/disable USB3.0 on pciephy0.

Signed-off-by: E Shattow <e@freeshell.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
E Shattow 2025-01-02 10:37:36 -08:00 committed by Conor Dooley
parent 57b5369f36
commit 65e8b99126
1 changed files with 2 additions and 0 deletions
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arch/riscv/boot/dts/starfive/jh7110.dtsi
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@ -611,6 +611,8 @@ usbphy0: phy@10200000 {
pciephy0: phy@10210000 {
compatible = "starfive,jh7110-pcie-phy";
reg = <0x0 0x10210000 0x0 0x10000>;
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
#phy-cells = <0>;
};