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riscv: dts: starfive: fml13v01: enable pcie1

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Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.

Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io>
Tested-by: Maud Spierings <maud_spierings@hotmail.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Sandie Cao 2025-02-07 17:36:18 +08:00 committed by Conor Dooley
parent 4bdea6e339
commit 57b5369f36
1 changed files with 34 additions and 0 deletions
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34
arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
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@ -11,6 +11,40 @@ / {
compatible = "deepcomputing,fml13v01", "starfive,jh7110";
};
&pcie1 {
perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
phys = <&pciephy1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_pins>;
status = "okay";
};
&sysgpio {
pcie1_pins: pcie1-0 {
clkreq-pins {
pinmux = <GPIOMUX(29, GPOUT_LOW,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-down;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
wake-pins {
pinmux = <GPIOMUX(28, GPOUT_HIGH,
GPOEN_DISABLE,
GPI_NONE)>;
bias-pull-up;
drive-strength = <2>;
input-enable;
input-schmitt-disable;
slew-rate = <0>;
};
};
};
&usb0 {
dr_mode = "host";
status = "okay";