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Minor improvements in arm64 DTS for v7.3

Browse Source 
Several non-functional (white-space and style) changes to match with DTS
 coding style as reported by recent dt-check-style tool.  Goal is to get
 to no `dt-check-style --mode strict` warnings over time.
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Merge tag 'dt64-cleanup-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

Minor improvements in arm64 DTS for v7.3

Several non-functional (white-space and style) changes to match with DTS
coding style as reported by recent dt-check-style tool.  Goal is to get
to no `dt-check-style --mode strict` warnings over time.

* tag 'dt64-cleanup-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  arm64: dts: Correct white-space style
  arm64: dts: amd: seattle: Remove useless xgbe DTSI include
  arm64: dts: amd: seattle: Remove useless clocks DTSI include

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-08-10 18:01:35 +02:00
commit 658ed6d54e
17 changed files with 128 additions and 145 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

78
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
View File

@ -71,5 +71,81 @@ sdcard0: mmc@0 {
};
&smb0 {
/include/ "amd-seattle-xgbe-b.dtsi"
xgmac0: ethernet@e0700000 {
compatible = "amd,xgbe-seattle-v1a";
reg = <0 0xe0700000 0 0x80000>,
<0 0xe0780000 0 0x80000>,
<0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
<0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
<0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
interrupts = <0 325 4>,
<0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
<0 323 4>;
amd,per-channel-interrupt;
amd,speed-set = <0>;
amd,serdes-blwc = <1>, <1>, <0>;
amd,serdes-cdr-rate = <2>, <2>, <7>;
amd,serdes-pq-skew = <10>, <10>, <18>;
amd,serdes-tx-amp = <0>, <0>, <0>;
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
mac-address = [ 02 A1 A2 A3 A4 A5 ];
clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
dma-coherent;
};
xgmac1: ethernet@e0900000 {
compatible = "amd,xgbe-seattle-v1a";
reg = <0 0xe0900000 0 0x80000>,
<0 0xe0980000 0 0x80000>,
<0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
<0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
<0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
interrupts = <0 324 4>,
<0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
<0 322 4>;
amd,per-channel-interrupt;
amd,speed-set = <0>;
amd,serdes-blwc = <1>, <1>, <0>;
amd,serdes-cdr-rate = <2>, <2>, <7>;
amd,serdes-pq-skew = <10>, <10>, <18>;
amd,serdes-tx-amp = <0>, <0>, <0>;
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
mac-address = [ 02 B1 B2 B3 B4 B5 ];
clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
dma-coherent;
};
xgmac0_smmu: iommu@e0600000 {
compatible = "arm,mmu-401";
reg = <0 0xe0600000 0 0x10000>;
#global-interrupts = <1>;
interrupts = /* Uses combined intr for both
* global and context
*/
<0 336 4>,
<0 336 4>;
#iommu-cells = <2>;
dma-coherent;
};
xgmac1_smmu: iommu@e0800000 {
compatible = "arm,mmu-401";
reg = <0 0xe0800000 0 0x10000>;
#global-interrupts = <1>;
interrupts = /* Uses combined intr for both
* global and context
*/
<0 335 4>,
<0 335 4>;
#iommu-cells = <2>;
dma-coherent;
};
};

43
arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
View File

@ -1,43 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DTS file for AMD Seattle Clocks
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*/
adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "adl3clk_100mhz";
};
ccpclk_375mhz: clock-375000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <375000000>;
clock-output-names = "ccpclk_375mhz";
};
sataclk_333mhz: clock-333000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <333000000>;
clock-output-names = "sataclk_333mhz";
};
dmaclk_500mhz: pcieclk_500mhz: clock-500000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
clock-output-names = "pcieclk_500mhz";
};
xgmacclk0_dma_250mhz: xgmacclk0_ptp_250mhz: xgmacclk1_dma_250mhz: xgmacclk1_ptp_250mhz:
miscclk_250mhz: clock-250000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "miscclk_250mhz";
};

36
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
View File

@ -11,7 +11,41 @@ / {
#address-cells = <2>;
#size-cells = <2>;
/include/ "amd-seattle-clks.dtsi"
adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "adl3clk_100mhz";
};
ccpclk_375mhz: clock-375000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <375000000>;
clock-output-names = "ccpclk_375mhz";
};
sataclk_333mhz: clock-333000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <333000000>;
clock-output-names = "sataclk_333mhz";
};
dmaclk_500mhz: pcieclk_500mhz: clock-500000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
clock-output-names = "pcieclk_500mhz";
};
xgmacclk0_dma_250mhz: xgmacclk0_ptp_250mhz: xgmacclk1_dma_250mhz: xgmacclk1_ptp_250mhz:
miscclk_250mhz: clock-250000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "miscclk_250mhz";
};
gic0: interrupt-controller@e1101000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";

84
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
View File

@ -1,84 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* DTS file for AMD Seattle XGBE (RevB)
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*/
xgmac0: ethernet@e0700000 {
compatible = "amd,xgbe-seattle-v1a";
reg = <0 0xe0700000 0 0x80000>,
<0 0xe0780000 0 0x80000>,
<0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
<0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
<0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
interrupts = <0 325 4>,
<0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
<0 323 4>;
amd,per-channel-interrupt;
amd,speed-set = <0>;
amd,serdes-blwc = <1>, <1>, <0>;
amd,serdes-cdr-rate = <2>, <2>, <7>;
amd,serdes-pq-skew = <10>, <10>, <18>;
amd,serdes-tx-amp = <0>, <0>, <0>;
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
mac-address = [ 02 A1 A2 A3 A4 A5 ];
clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
dma-coherent;
};
xgmac1: ethernet@e0900000 {
compatible = "amd,xgbe-seattle-v1a";
reg = <0 0xe0900000 0 0x80000>,
<0 0xe0980000 0 0x80000>,
<0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
<0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
<0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
interrupts = <0 324 4>,
<0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
<0 322 4>;
amd,per-channel-interrupt;
amd,speed-set = <0>;
amd,serdes-blwc = <1>, <1>, <0>;
amd,serdes-cdr-rate = <2>, <2>, <7>;
amd,serdes-pq-skew = <10>, <10>, <18>;
amd,serdes-tx-amp = <0>, <0>, <0>;
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
mac-address = [ 02 B1 B2 B3 B4 B5 ];
clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
dma-coherent;
};
xgmac0_smmu: iommu@e0600000 {
compatible = "arm,mmu-401";
reg = <0 0xe0600000 0 0x10000>;
#global-interrupts = <1>;
interrupts = /* Uses combined intr for both
* global and context
*/
<0 336 4>,
<0 336 4>;
#iommu-cells = <2>;
dma-coherent;
};
xgmac1_smmu: iommu@e0800000 {
compatible = "arm,mmu-401";
reg = <0 0xe0800000 0 0x10000>;
#global-interrupts = <1>;
interrupts = /* Uses combined intr for both
* global and context
*/
<0 335 4>,
<0 335 4>;
#iommu-cells = <2>;
dma-coherent;
};

2
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
View File

@ -546,7 +546,7 @@ &spdifout_b {
};
&tdmif_a {
pinctrl-0 = <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>, <&tdm_a_dout0_pins> ;
pinctrl-0 = <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>, <&tdm_a_dout0_pins>;
pinctrl-names = "default";
status = "okay";
};

2
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View File

@ -293,7 +293,7 @@ socpll: socpll@17000120 {
clock-output-names = "socpll";
};
socplldiv2: socplldiv2 {
socplldiv2: socplldiv2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&socpll 0>;

2
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -174,7 +174,7 @@ socpll: socpll@17000120 {
clock-output-names = "socpll";
};
socplldiv2: socplldiv2 {
socplldiv2: socplldiv2 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&socpll 0>;

2
arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi
View File

@ -33,6 +33,6 @@ &hpm2 {
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
};
&hpm3 {
&hpm3 {
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
};

2
arch/arm64/boot/dts/broadcom/bcm2712.dtsi
View File

@ -644,7 +644,7 @@ mip1: msi-controller@1000131000 {
brcm,msi-offset = <8>;
};
isp: isp@1000880000 {
isp: isp@1000880000 {
compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe";
reg = <0x10 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
View File

@ -107,7 +107,7 @@ qspi_boot: partition@0 {
reg = <0x0 0x00c00000>;
};
root: partition@c00000 {
root: partition@c00000 {
label = "root";
reg = <0x00c00000 0x03400000>;
};

2
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View File

@ -109,7 +109,7 @@ gpio_exp: pca9555@22 {
*/
};
rtc@68 {
rtc@68 {
/* PT7C4337A from pericom fully compatible with the ds1337 */
compatible = "dallas,ds1337";
reg = <0x68>;

4
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
View File

@ -353,7 +353,7 @@ cp0_mmc0_cd_pins: cp0-mmc0-cd-pins {
marvell,function = "sdio_cd";
};
cp0_pwrbtn_pins: cp0-pwrbtn-pins {
cp0_pwrbtn_pins: cp0-pwrbtn-pins {
marvell,pins = "mpp31";
marvell,function = "gpio";
};
@ -378,7 +378,7 @@ cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
marvell,function = "spi1";
};
cp0_uart2_pins: cp0-uart2-pins {
cp0_uart2_pins: cp0-uart2-pins {
marvell,pins = "mpp50", "mpp51";
marvell,function = "uart2";
};

2
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
View File

@ -1159,7 +1159,7 @@ asrc_out5_ep: endpoint {
};
};
asrc_out6_port: port@c {
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {

2
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View File

@ -1765,7 +1765,7 @@ asrc_out5_ep: endpoint {
};
};
asrc_out6_port: port@c {
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {

2
arch/arm64/boot/dts/nvidia/tegra264.dtsi
View File

@ -2015,7 +2015,7 @@ asrc_out5_ep: endpoint {
};
};
asrc_out6_port: port@c {
asrc_out6_port: port@c {
reg = <0xc>;
asrc_out6_ep: endpoint {

4
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
View File

@ -404,11 +404,11 @@ scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
scmi_vddcore: regulator@11 {
scmi_vddcore: regulator@11 {
reg = <VOLTD_SCMI_STPMIC2_BUCK2>;
regulator-name = "vddcore";
};
scmi_v1v8: regulator@14 {
scmi_v1v8: regulator@14 {
reg = <VOLTD_SCMI_STPMIC2_BUCK5>;
regulator-name = "v1v8";
};

4
arch/arm64/boot/dts/xilinx/versal-net.dtsi
View File

@ -1074,7 +1074,7 @@ usb0: usb@f1e00000 {
#address-cells = <2>;
#size-cells = <2>;
dwc3_0: usb@f1b00000 {
dwc3_0: usb@f1b00000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0 0xf1b00000 0 0x10000>;
@ -1099,7 +1099,7 @@ usb1: usb@f1e10000 {
#address-cells = <2>;
#size-cells = <2>;
dwc3_1: usb@f1c00000 {
dwc3_1: usb@f1c00000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xf1c00000 0x0 0x10000>;