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mtd: spinand: Enable QE on all dies

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The QUAD ENABLE (QE) bit is stored in a per-die configuration
register on some SPI-NAND devices. When a device contains multiple
dies, updating the QE bit only on the currently selected die can
leave the remaining dies operating in non-quad mode.
 
Iterate over all targets and update the QE setting on each die
during initialization to ensure consistent quad I/O operation
across the entire device.

Tested on ISSI IS38SMW04G8B.

Fixes: 7529df4652 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Han Xu 2026-08-13 08:07:24 -05:00 committed by Miquel Raynal
parent b5965c4221
commit 63d6cace2c
1 changed files with 20 additions and 2 deletions
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22
drivers/mtd/nand/spi/core.c
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@ -281,8 +281,26 @@ static int spinand_init_cfg_cache(struct spinand_device *spinand)
static int spinand_init_quad_enable(struct spinand_device *spinand,
bool enable)
{
return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
enable ? CFG_QUAD_ENABLE : 0);
struct nand_device *nand = spinand_to_nand(spinand);
unsigned int target;
int ret;
/*
* QE is a per-die setting on some devices. Program each target
* individually when enabling or disabling quad I/O mode.
*/
for (target = 0; target < nand->memorg.ntargets; target++) {
ret = spinand_select_target(spinand, target);
if (ret)
return ret;
ret = spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
enable ? CFG_QUAD_ENABLE : 0);
if (ret)
return ret;
}
return 0;
}
static int spinand_ecc_enable(struct spinand_device *spinand,