media: rockchip: isp1: increase isp clk margin

"rkisp1: MIPI mis error:" may occur when data_rate equal
to clk_rate_tbl table and actually isp clk is less
than clk rate we set.
So increase margin to fix it.

Change-Id: Icbca32cf02fb522ad74b40adc8253863b80eaec0
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
This commit is contained in:
Nickey Yang 2019-09-19 10:05:22 +08:00 committed by Hu Kejun
parent 4318ff8e62
commit 62a29500ee

View File

@ -206,6 +206,9 @@ static int __isp_pipeline_s_isp_clk(struct rkisp1_pipeline *p)
data_rate >>= 3;
do_div(data_rate, 1000 * 1000);
/* increase 25% margin */
data_rate += data_rate >> 2;
/* compare with isp clock adjustment table */
for (i = 0; i < dev->num_clk_rate_tbl; i++)
if (data_rate <= dev->clk_rate_tbl[i])