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media: rockchip: isp1: increase isp clk margin
"rkisp1: MIPI mis error:" may occur when data_rate equal to clk_rate_tbl table and actually isp clk is less than clk rate we set. So increase margin to fix it. Change-Id: Icbca32cf02fb522ad74b40adc8253863b80eaec0 Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
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@ -206,6 +206,9 @@ static int __isp_pipeline_s_isp_clk(struct rkisp1_pipeline *p)
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data_rate >>= 3;
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do_div(data_rate, 1000 * 1000);
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/* increase 25% margin */
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data_rate += data_rate >> 2;
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/* compare with isp clock adjustment table */
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for (i = 0; i < dev->num_clk_rate_tbl; i++)
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if (data_rate <= dev->clk_rate_tbl[i])
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