From 62a29500ee19ff3b9cc5a893f8f48ae2c0805adc Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Thu, 19 Sep 2019 10:05:22 +0800 Subject: [PATCH] media: rockchip: isp1: increase isp clk margin "rkisp1: MIPI mis error:" may occur when data_rate equal to clk_rate_tbl table and actually isp clk is less than clk rate we set. So increase margin to fix it. Change-Id: Icbca32cf02fb522ad74b40adc8253863b80eaec0 Signed-off-by: Nickey Yang --- drivers/media/platform/rockchip/isp1/dev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/rockchip/isp1/dev.c b/drivers/media/platform/rockchip/isp1/dev.c index 44e5aace5480..6ee9d67912dc 100644 --- a/drivers/media/platform/rockchip/isp1/dev.c +++ b/drivers/media/platform/rockchip/isp1/dev.c @@ -206,6 +206,9 @@ static int __isp_pipeline_s_isp_clk(struct rkisp1_pipeline *p) data_rate >>= 3; do_div(data_rate, 1000 * 1000); + /* increase 25% margin */ + data_rate += data_rate >> 2; + /* compare with isp clock adjustment table */ for (i = 0; i < dev->num_clk_rate_tbl; i++) if (data_rate <= dev->clk_rate_tbl[i])