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arm64: dts: renesas: r9a08g046: Add OPP table

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Add OPP table for RZ/G3L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430125342.439755-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-04-30 13:53:05 +01:00 committed by Geert Uytterhoeven
parent 998dd840cc
commit 60f8dfd33c
1 changed files with 44 additions and 0 deletions
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44
arch/arm64/boot/dts/renesas/r9a08g046.dtsi
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@ -14,6 +14,42 @@ / {
#size-cells = <2>;
interrupt-parent = <&gic>;
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-37500000 {
opp-hz = /bits/ 64 <37500000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -24,6 +60,8 @@ cpu0: cpu@0 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
@ -32,6 +70,8 @@ cpu1: cpu@100 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
@ -40,6 +80,8 @@ cpu2: cpu@200 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
@ -48,6 +90,8 @@ cpu3: cpu@300 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {