github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-11-02 03:39:03 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amdgpu: Use partition switch shadow register

Browse Source 
Control register is access restricted. Use the read-only copy to read
the partition settings.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2026-08-04 11:43:04 +05:30 committed by Alex Deucher
parent ae6552ed04
commit 6028808e37
3 changed files with 9 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
View File

@ -839,19 +839,16 @@ static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev,
soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
}
#define regGFX_IMU_PARTITION_SWITCH 0x5f8c
#define regGFX_IMU_PARTITION_SWITCH_BASE_IDX 1
#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT 0x2
#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL
static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev)
{
u32 reg_data;
/* the register data is expected to be the same on all instances */
reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH);
reg_data = RREG32_SOC15(GC, GET_INST(GC, 0),
regGFX_IMU_PARTITION_SWITCH_SHADOW);
return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP);
return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH_SHADOW,
TOTAL_XCCS_IN_XCP);
}
static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)

2
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
View File

@ -7369,6 +7369,8 @@
#define regGFX_IMU_TIMER1_VALUE 0x40d1
#define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1
#define regGFX_IMU_FUSE_CTRL 0x40e0
#define regGFX_IMU_PARTITION_SWITCH_SHADOW 0x40f8
#define regGFX_IMU_PARTITION_SWITCH_SHADOW_BASE_IDX 1
#define regGFX_IMU_FUSE_CTRL_BASE_IDX 1
#define regGFX_IMU_D_RAM_ADDR 0x40fc
#define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1

4
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
View File

@ -23556,7 +23556,9 @@
//GFX_IMU_I_RAM_DATA
#define GFX_IMU_I_RAM_DATA__DATA__SHIFT 0x0
#define GFX_IMU_I_RAM_DATA__DATA_MASK 0xFFFFFFFFL
//GFX_IMU_PARTITION_SWITCH_SHADOW
#define GFX_IMU_PARTITION_SWITCH_SHADOW__TOTAL_XCCS_IN_XCP__SHIFT 0x2
#define GFX_IMU_PARTITION_SWITCH_SHADOW__TOTAL_XCCS_IN_XCP_MASK 0x0000003CL
// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmhdec
//GRBMH_CNTL