github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-31 11:37:06 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

ARM: dts: imx6ul-var-som: factor out audio support

Browse Source 
Not all boards use the audio codec, so factor out this functionality to a
separate dtsi.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Hugo Villeneuve 2026-03-05 13:06:28 -05:00 committed by Frank Li
parent 38296261b0
commit 5f1733077a
6 changed files with 34 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi Normal file
View File

@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Audio support for Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
&iomuxc {
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
>;
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};

21
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
View File

@ -52,16 +52,6 @@ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
@ -163,17 +153,6 @@ &pxp {
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};

1
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
View File

@ -13,6 +13,7 @@
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-enet1.dtsi"
#include "imx6ul-var-som-audio.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";

1
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
View File

@ -13,6 +13,7 @@
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-sd.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-audio.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";

1
arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
View File

@ -13,6 +13,7 @@
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-enet1.dtsi"
#include "imx6ul-var-som-audio.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";

1
arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
View File

@ -12,6 +12,7 @@
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-sd.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-audio.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";