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ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1)

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ENET1 is currently disabled and not supported/working on the concerto EVK.
Add support for this optional configuration in a separate dtsi, so that it
can be selectively enabled/disabled.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Hugo Villeneuve 2026-03-05 13:06:27 -05:00 committed by Frank Li
parent 04b897252c
commit 38296261b0
8 changed files with 69 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

50
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
View File

@ -44,57 +44,7 @@ &clks {
assigned-clock-rates = <786432000>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <1>;
micrel,rmii-reference-clock-select-25-mhz;
};
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet1_gpio: enet1-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
>;
};
pinctrl_enet1_mdio: enet1-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0

4
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
View File

@ -52,10 +52,6 @@ &can1 {
status = "okay";
};
&fec1 {
status = "disabled";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";

1
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
View File

@ -12,6 +12,7 @@
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-enet1.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";

44
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Ethernet ENET1 support for Variscite VAR-SOM-6UL module with
* the EC configuration option ((ethernet PHY assembled on SOM).
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
};
&mdio_enet2 {
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <1>;
micrel,rmii-reference-clock-select-25-mhz;
};
};

11
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi
View File

@ -26,6 +26,17 @@ mdio_enet2: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <1>;
micrel,rmii-reference-clock-select-25-mhz;
};
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;

6
arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
View File

@ -29,4 +29,10 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */
>;
};
pinctrl_enet1_gpio: enet1-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
>;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
View File

@ -12,6 +12,7 @@
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-enet1.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";

6
arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
View File

@ -27,4 +27,10 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */
>;
};
pinctrl_enet1_gpio: enet1-gpiogrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
>;
};
};