github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-31 11:37:06 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

ARM: dts: imx6ul-var-som: factor out ENET2 ethernet support

Browse Source 
Not all boards use the ethernet ENET2 port, so factor out this
functionality to a separate dtsi. On the concerto board, this
uses the ethernet PHY assembled on it.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Hugo Villeneuve 2026-03-05 13:06:26 -05:00 committed by Frank Li
parent 235c070343
commit 04b897252c
7 changed files with 72 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
View File

@ -37,13 +37,6 @@ reg_gpio_dvfs: reg-gpio-dvfs {
states = <1300000 0x1
1400000 0x0>;
};
rmii_ref_clk: rmii-ref-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "rmii-ref";
};
};
&clks {

50
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi
View File

@ -56,30 +56,6 @@ &fec1 {
status = "disabled";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <0>;
micrel,rmii-reference-clock-select-25-mhz;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -101,32 +77,6 @@ rtc@68 {
};
&iomuxc {
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_enet2_gpio: enet2-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
>;
};
pinctrl_enet2_mdio: enet2-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020

1
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts
View File

@ -11,6 +11,7 @@
#include "imx6ul-var-som.dtsi"
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";

1
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
View File

@ -12,6 +12,7 @@
#include "imx6ul-var-som.dtsi"
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-sd.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";

68
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi Normal file
View File

@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Ethernet ENET2 support for Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
/ {
rmii_ref_clk: rmii-ref-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "rmii-ref";
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio_enet2: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <0>;
micrel,rmii-reference-clock-select-25-mhz;
};
};
};
&iomuxc {
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_enet2_gpio: enet2-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
>;
};
pinctrl_enet2_mdio: enet2-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
>;
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts
View File

@ -11,6 +11,7 @@
#include "imx6ull-var-som.dtsi"
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";

1
arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts
View File

@ -11,6 +11,7 @@
#include "imx6ull-var-som.dtsi"
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-sd.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";