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net: stmmac: remove unused definitions
Potentially unused definitions were discovered using: $ for m in $(grep '#define ' $header | sed -e 's,#define[ ]*\([^ ]*\)[ ].*,\1,;s,(.*,,'); do if ! grep -q $m *.c; then echo $m; fi; done Each was verified, and then removed where truly unused. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vdtwI-00000002Gu6-1HYu@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
Jakub Kicinski
parent
58bc0f0bfc
commit
5a78fd3deb
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@ -30,59 +30,30 @@
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#define MAC_VLAN2 0x00000024 /* VLAN2 Tag */
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/* MAC CTRL defines */
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#define MAC_CONTROL_RA 0x80000000 /* Receive All Mode */
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#define MAC_CONTROL_BLE 0x40000000 /* Endian Mode */
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#define MAC_CONTROL_HBD 0x10000000 /* Heartbeat Disable */
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#define MAC_CONTROL_PS 0x08000000 /* Port Select */
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#define MAC_CONTROL_DRO 0x00800000 /* Disable Receive Own */
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#define MAC_CONTROL_EXT_LOOPBACK 0x00400000 /* Reserved (ext loopback?) */
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#define MAC_CONTROL_OM 0x00200000 /* Loopback Operating Mode */
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#define MAC_CONTROL_F 0x00100000 /* Full Duplex Mode */
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#define MAC_CONTROL_PM 0x00080000 /* Pass All Multicast */
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#define MAC_CONTROL_PR 0x00040000 /* Promiscuous Mode */
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#define MAC_CONTROL_IF 0x00020000 /* Inverse Filtering */
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#define MAC_CONTROL_PB 0x00010000 /* Pass Bad Frames */
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#define MAC_CONTROL_HO 0x00008000 /* Hash Only Filtering Mode */
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#define MAC_CONTROL_HP 0x00002000 /* Hash/Perfect Filtering Mode */
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#define MAC_CONTROL_LCC 0x00001000 /* Late Collision Control */
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#define MAC_CONTROL_DBF 0x00000800 /* Disable Broadcast Frames */
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#define MAC_CONTROL_DRTY 0x00000400 /* Disable Retry */
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#define MAC_CONTROL_ASTP 0x00000100 /* Automatic Pad Stripping */
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#define MAC_CONTROL_BOLMT_10 0x00000000 /* Back Off Limit 10 */
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#define MAC_CONTROL_BOLMT_8 0x00000040 /* Back Off Limit 8 */
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#define MAC_CONTROL_BOLMT_4 0x00000080 /* Back Off Limit 4 */
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#define MAC_CONTROL_BOLMT_1 0x000000c0 /* Back Off Limit 1 */
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#define MAC_CONTROL_DC 0x00000020 /* Deferral Check */
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#define MAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
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#define MAC_CONTROL_RE 0x00000004 /* Receiver Enable */
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#define MAC_CORE_INIT (MAC_CONTROL_HBD)
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/* MAC FLOW CTRL defines */
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#define MAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */
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#define MAC_FLOW_CTRL_PASS 0x00000004 /* Pass Control Frames */
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#define MAC_FLOW_CTRL_ENABLE 0x00000002 /* Flow Control Enable */
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#define MAC_FLOW_CTRL_PAUSE 0x00000001 /* Flow Control Busy ... */
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/* MII ADDR defines */
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#define MAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
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#define MAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
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/*----------------------------------------------------------------------------
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* DMA BLOCK defines
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*---------------------------------------------------------------------------*/
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/* DMA Bus Mode register defines */
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#define DMA_BUS_MODE_DBO 0x00100000 /* Descriptor Byte Ordering */
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#define DMA_BUS_MODE_BLE 0x00000080 /* Big Endian/Little Endian */
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#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
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#define DMA_BUS_MODE_DSL_MASK GENMASK(6, 2) /* Descriptor Skip Length */
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#define DMA_BUS_MODE_BAR_BUS 0x00000002 /* Bar-Bus Arbitration */
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#define DMA_BUS_MODE_DEFAULT 0x00000000
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/* DMA Control register defines */
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#define DMA_CONTROL_SF 0x00200000 /* Store And Forward */
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/* Transmit Threshold Control */
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enum ttc_control {
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DMA_CONTROL_TTC_DEFAULT = 0x00000000, /* Threshold is 32 DWORDS */
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@ -20,15 +20,11 @@
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#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
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#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
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#define GMAC_DEBUG 0x00000024 /* GMAC debug register */
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#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
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#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
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#define GMAC_INT_STATUS_PMT BIT(3)
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#define GMAC_INT_STATUS_MMCIS BIT(4)
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#define GMAC_INT_STATUS_MMCRIS BIT(5)
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#define GMAC_INT_STATUS_MMCTIS BIT(6)
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#define GMAC_INT_STATUS_MMCCSUM BIT(7)
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#define GMAC_INT_STATUS_TSTAMP BIT(9)
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#define GMAC_INT_STATUS_LPIIS BIT(10)
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/* interrupt mask register */
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@ -89,8 +85,6 @@ enum power_event {
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/* GMAC Configuration defines */
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#define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
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#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
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#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
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#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */
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#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
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#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
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@ -102,41 +96,25 @@ enum inter_frame_gap {
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#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */
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#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
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#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
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#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
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#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
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#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
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#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
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#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
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#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
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#define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */
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#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
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#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
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#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
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#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | \
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GMAC_CONTROL_BE | GMAC_CONTROL_DCRS)
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/* GMAC Frame Filter defines */
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#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
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#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
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#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
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#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
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#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
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#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
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#define GMAC_FRAME_FILTER_PCF 0x00000080 /* Pass Control frames */
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#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
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#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
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#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
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#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
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/* GMII ADDR defines */
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#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
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#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
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/* GMAC FLOW CTRL defines */
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#define GMAC_FLOW_CTRL_PT_MASK GENMASK(31, 16) /* Pause Time Mask */
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#define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */
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#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
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#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
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#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
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/* DEBUG Register defines */
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/* MTL TxStatus FIFO */
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@ -145,14 +123,12 @@ enum inter_frame_gap {
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#define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
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/* MTL Tx FIFO Read Controller Status */
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#define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)
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#define GMAC_DEBUG_TRCSTS_IDLE 0
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#define GMAC_DEBUG_TRCSTS_READ 1
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#define GMAC_DEBUG_TRCSTS_TXW 2
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#define GMAC_DEBUG_TRCSTS_WRITE 3
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#define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
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/* MAC Transmit Frame Controller Status */
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#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
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#define GMAC_DEBUG_TFCSTS_IDLE 0
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#define GMAC_DEBUG_TFCSTS_WAIT 1
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#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
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#define GMAC_DEBUG_TFCSTS_XFER 3
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@ -176,9 +152,6 @@ enum inter_frame_gap {
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/*--- DMA BLOCK defines ---*/
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/* DMA Bus Mode register defines */
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#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */
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#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
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#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
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/* Programmable burst length (passed thorugh platform)*/
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#define DMA_BUS_MODE_PBL_MASK GENMASK(13, 8) /* Programmable Burst Len */
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#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
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@ -197,16 +170,9 @@ enum rx_tx_priority_ratio {
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#define DMA_BUS_MODE_AAL 0x02000000
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/* DMA CRS Control and Status Register Mapping */
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#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */
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#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */
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/* DMA Bus Mode register defines */
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#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
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#define DMA_BUS_PR_RATIO_SHIFT 14
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#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
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/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
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/* Disable Drop TCP/IP csum error */
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#define DMA_CONTROL_DT 0x04000000
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#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
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#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
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/* Threshold for Activating the FC */
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@ -238,8 +204,6 @@ enum ttc_control {
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#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
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#define DMA_CONTROL_EFC 0x00000100
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#define DMA_CONTROL_FEF 0x00000080
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#define DMA_CONTROL_FUF 0x00000040
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/* Receive flow control activation field
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* RFA field in DMA control register, bits 23,10:9
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@ -276,20 +240,8 @@ enum ttc_control {
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*/
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#define RFA_FULL_MINUS_1K 0x00000000
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#define RFA_FULL_MINUS_2K 0x00000200
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#define RFA_FULL_MINUS_3K 0x00000400
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#define RFA_FULL_MINUS_4K 0x00000600
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#define RFA_FULL_MINUS_5K 0x00800000
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#define RFA_FULL_MINUS_6K 0x00800200
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#define RFA_FULL_MINUS_7K 0x00800400
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#define RFD_FULL_MINUS_1K 0x00000000
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#define RFD_FULL_MINUS_2K 0x00000800
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#define RFD_FULL_MINUS_3K 0x00001000
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#define RFD_FULL_MINUS_4K 0x00001800
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#define RFD_FULL_MINUS_5K 0x00400000
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#define RFD_FULL_MINUS_6K 0x00400800
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#define RFD_FULL_MINUS_7K 0x00401000
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enum rtc_control {
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DMA_CONTROL_RTC_64 = 0x00000000,
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@ -302,10 +254,6 @@ enum rtc_control {
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#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */
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/* MMC registers offset */
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#define GMAC_MMC_CTRL 0x100
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#define GMAC_MMC_RX_INTR 0x104
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#define GMAC_MMC_TX_INTR 0x108
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#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
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#define GMAC_EXTHASH_BASE 0x500
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/* PTP and timestamping registers */
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@ -24,7 +24,6 @@
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#define DMA_SYS_BUS_MODE 0x00001004
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#define DMA_BUS_MODE_SPH BIT(24)
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#define DMA_BUS_MODE_PBL BIT(16)
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#define DMA_BUS_MODE_RPBL_MASK GENMASK(21, 16)
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#define DMA_BUS_MODE_MB BIT(14)
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@ -32,24 +31,6 @@
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#define DMA_STATUS 0x00001008
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#define DMA_STATUS_MAC BIT(17)
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#define DMA_STATUS_MTL BIT(16)
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#define DMA_STATUS_CHAN7 BIT(7)
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#define DMA_STATUS_CHAN6 BIT(6)
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#define DMA_STATUS_CHAN5 BIT(5)
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#define DMA_STATUS_CHAN4 BIT(4)
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#define DMA_STATUS_CHAN3 BIT(3)
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#define DMA_STATUS_CHAN2 BIT(2)
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#define DMA_STATUS_CHAN1 BIT(1)
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#define DMA_STATUS_CHAN0 BIT(0)
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#define DMA_DEBUG_STATUS_0 0x0000100c
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#define DMA_DEBUG_STATUS_1 0x00001010
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#define DMA_DEBUG_STATUS_2 0x00001014
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#define DMA_DEBUG_STATUS_TS_MASK 0xf
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#define DMA_DEBUG_STATUS_RS_MASK 0xf
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#define DMA_AXI_BUS_MODE 0x00001028
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#define DMA_AXI_EN_LPI BIT(31)
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@ -58,16 +39,10 @@
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#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
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#define DMA_SYS_BUS_MB BIT(14)
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_SYS_BUS_AAL DMA_AXI_AAL
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#define DMA_SYS_BUS_EAME BIT(11)
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#define DMA_SYS_BUS_FB BIT(0)
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#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
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DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
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DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
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DMA_AXI_BLEN4)
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#define DMA_TBS_CTRL 0x00001050
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#define DMA_TBS_FTOS GENMASK(31, 8)
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@ -91,12 +66,9 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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return addr;
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}
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#define DMA_CHAN_REG_NUMBER 17
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#define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x)
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#define DMA_CONTROL_SPH BIT(24)
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#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
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#define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4)
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@ -125,16 +97,8 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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#define DMA_CHAN_INTR_ENA_AIE BIT(15)
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#define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
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#define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
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#define DMA_CHAN_INTR_ENA_CDE BIT(13)
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#define DMA_CHAN_INTR_ENA_FBE BIT(12)
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#define DMA_CHAN_INTR_ENA_ERE BIT(11)
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#define DMA_CHAN_INTR_ENA_ETE BIT(10)
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#define DMA_CHAN_INTR_ENA_RWE BIT(9)
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#define DMA_CHAN_INTR_ENA_RSE BIT(8)
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#define DMA_CHAN_INTR_ENA_RBUE BIT(7)
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#define DMA_CHAN_INTR_ENA_RIE BIT(6)
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#define DMA_CHAN_INTR_ENA_TBUE BIT(2)
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#define DMA_CHAN_INTR_ENA_TSE BIT(1)
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#define DMA_CHAN_INTR_ENA_TIE BIT(0)
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#define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
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@ -173,9 +137,6 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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/* Interrupt status per channel */
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#define DMA_CHAN_STATUS_REB GENMASK(21, 19)
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#define DMA_CHAN_STATUS_REB_SHIFT 19
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#define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
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#define DMA_CHAN_STATUS_TEB_SHIFT 16
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#define DMA_CHAN_STATUS_NIS BIT(15)
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#define DMA_CHAN_STATUS_AIS BIT(14)
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#define DMA_CHAN_STATUS_CDE BIT(13)
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@ -209,11 +170,6 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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DMA_CHAN_STATUS_TI | \
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DMA_CHAN_STATUS_MSK_COMMON)
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#define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
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#define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
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#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
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#define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
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int dwmac4_dma_reset(void __iomem *ioaddr);
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void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan, bool rx, bool tx);
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@ -22,13 +22,9 @@
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#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
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#define DMA_STATUS 0x00001014 /* Status Register */
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#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */
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#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
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#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
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#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
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#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
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#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
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#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
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#define DMA_STATUS_TS_MASK GENMASK(22, 20) /* Transmit Process State */
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#define DMA_STATUS_RS_MASK GENMASK(19, 17) /* Receive Process State */
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#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
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@ -79,9 +75,7 @@
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/* DMA Normal interrupt */
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#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
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#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
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#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
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#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
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#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
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DMA_INTR_ENA_TIE)
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@ -89,14 +83,7 @@
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/* DMA Abnormal interrupt */
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#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
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#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
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#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
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#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
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#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
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#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
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#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
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#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
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#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
|
||||
|
||||
#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
|
||||
DMA_INTR_ENA_UNE)
|
||||
|
|
@ -128,8 +115,6 @@ static inline u32 dma_chan_base_addr(u32 base, u32 chan)
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|||
#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
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||||
#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
|
||||
#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
|
||||
#define DMA_CHAN_MISSED_FRAME_CTR(chan) \
|
||||
dma_chan_base_addr(DMA_MISSED_FRAME_CTR, chan)
|
||||
#define DMA_CHAN_RX_WATCHDOG(chan) \
|
||||
dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
|
||||
|
||||
|
|
@ -145,14 +130,6 @@ static inline u32 dma_chan_base_addr(u32 base, u32 chan)
|
|||
#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
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||||
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
|
||||
|
||||
#define DMA_AXI_OSR_MAX 0xf
|
||||
#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
|
||||
(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
|
||||
#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
|
||||
DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
|
||||
DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
|
||||
DMA_AXI_BLEN4)
|
||||
|
||||
#define DMA_AXI_1KBBE BIT(13)
|
||||
|
||||
#define DMA_AXI_UNDEF BIT(0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user