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net: stmmac: arrange register fields after register offsets
Arrange the register fields to be after their corresponding register offset definitions, which groups all the definitions for a register together. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vdtwD-00000002Gu0-0nTN@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
Jakub Kicinski
parent
8409495bf6
commit
58bc0f0bfc
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@ -16,28 +16,22 @@
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#define DMA_CHANNEL_NB_MAX 1
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#define DMA_BUS_MODE 0x00001000
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#define DMA_SYS_BUS_MODE 0x00001004
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#define DMA_STATUS 0x00001008
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#define DMA_DEBUG_STATUS_0 0x0000100c
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#define DMA_DEBUG_STATUS_1 0x00001010
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#define DMA_DEBUG_STATUS_2 0x00001014
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#define DMA_AXI_BUS_MODE 0x00001028
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#define DMA_TBS_CTRL 0x00001050
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/* DMA Bus Mode bitmap */
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#define DMA_BUS_MODE_DCHE BIT(19)
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#define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16)
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#define DMA_BUS_MODE_INTM_MODE1 0x1
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#define DMA_BUS_MODE_SFT_RESET BIT(0)
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/* DMA SYS Bus Mode bitmap */
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#define DMA_SYS_BUS_MODE 0x00001004
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#define DMA_BUS_MODE_SPH BIT(24)
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#define DMA_BUS_MODE_PBL BIT(16)
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#define DMA_BUS_MODE_RPBL_MASK GENMASK(21, 16)
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#define DMA_BUS_MODE_MB BIT(14)
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#define DMA_BUS_MODE_FB BIT(0)
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/* DMA Interrupt top status */
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#define DMA_STATUS 0x00001008
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#define DMA_STATUS_MAC BIT(17)
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#define DMA_STATUS_MTL BIT(16)
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#define DMA_STATUS_CHAN7 BIT(7)
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@ -49,11 +43,15 @@
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#define DMA_STATUS_CHAN1 BIT(1)
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#define DMA_STATUS_CHAN0 BIT(0)
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/* DMA debug status bitmap */
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#define DMA_DEBUG_STATUS_0 0x0000100c
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#define DMA_DEBUG_STATUS_1 0x00001010
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#define DMA_DEBUG_STATUS_2 0x00001014
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#define DMA_DEBUG_STATUS_TS_MASK 0xf
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#define DMA_DEBUG_STATUS_RS_MASK 0xf
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/* DMA AXI bitmap */
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#define DMA_AXI_BUS_MODE 0x00001028
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#define DMA_AXI_EN_LPI BIT(31)
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#define DMA_AXI_LPI_XIT_FRM BIT(30)
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#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
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@ -70,7 +68,8 @@
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DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
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DMA_AXI_BLEN4)
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/* DMA TBS Control */
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#define DMA_TBS_CTRL 0x00001050
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#define DMA_TBS_FTOS GENMASK(31, 8)
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#define DMA_TBS_FTOV BIT(0)
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#define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV)
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@ -95,8 +94,22 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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#define DMA_CHAN_REG_NUMBER 17
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#define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x)
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#define DMA_CONTROL_SPH BIT(24)
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#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
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#define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4)
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#define DMA_CONTROL_EDSE BIT(28)
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#define DMA_CONTROL_TSE BIT(12)
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#define DMA_CONTROL_OSP BIT(4)
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#define DMA_CONTROL_ST BIT(0)
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#define DMA_CHAN_RX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x8)
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#define DMA_CONTROL_SR BIT(0)
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#define DMA_RBSZ_MASK GENMASK(14, 1)
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#define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x10)
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#define DMA_CHAN_TX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x14)
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#define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x18)
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@ -105,70 +118,9 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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#define DMA_CHAN_RX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x28)
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#define DMA_CHAN_TX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x2c)
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#define DMA_CHAN_RX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x30)
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#define DMA_CHAN_INTR_ENA(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x34)
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#define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
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#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c)
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#define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44)
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#define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4c)
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#define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x50)
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#define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x54)
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#define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x58)
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#define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x5c)
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#define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60)
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/* DMA Control X */
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#define DMA_CONTROL_SPH BIT(24)
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#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
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/* DMA Tx Channel X Control register defines */
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#define DMA_CONTROL_EDSE BIT(28)
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#define DMA_CONTROL_TSE BIT(12)
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#define DMA_CONTROL_OSP BIT(4)
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#define DMA_CONTROL_ST BIT(0)
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/* DMA Rx Channel X Control register defines */
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#define DMA_CONTROL_SR BIT(0)
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#define DMA_RBSZ_MASK GENMASK(14, 1)
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/* Interrupt status per channel */
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#define DMA_CHAN_STATUS_REB GENMASK(21, 19)
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#define DMA_CHAN_STATUS_REB_SHIFT 19
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#define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
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#define DMA_CHAN_STATUS_TEB_SHIFT 16
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#define DMA_CHAN_STATUS_NIS BIT(15)
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#define DMA_CHAN_STATUS_AIS BIT(14)
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#define DMA_CHAN_STATUS_CDE BIT(13)
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#define DMA_CHAN_STATUS_FBE BIT(12)
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#define DMA_CHAN_STATUS_ERI BIT(11)
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#define DMA_CHAN_STATUS_ETI BIT(10)
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#define DMA_CHAN_STATUS_RWT BIT(9)
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#define DMA_CHAN_STATUS_RPS BIT(8)
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#define DMA_CHAN_STATUS_RBU BIT(7)
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#define DMA_CHAN_STATUS_RI BIT(6)
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#define DMA_CHAN_STATUS_TBU BIT(2)
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#define DMA_CHAN_STATUS_TPS BIT(1)
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#define DMA_CHAN_STATUS_TI BIT(0)
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#define DMA_CHAN_STATUS_MSK_COMMON (DMA_CHAN_STATUS_NIS | \
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DMA_CHAN_STATUS_AIS | \
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DMA_CHAN_STATUS_CDE | \
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DMA_CHAN_STATUS_FBE)
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#define DMA_CHAN_STATUS_MSK_RX (DMA_CHAN_STATUS_REB | \
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DMA_CHAN_STATUS_ERI | \
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DMA_CHAN_STATUS_RWT | \
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DMA_CHAN_STATUS_RPS | \
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DMA_CHAN_STATUS_RBU | \
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DMA_CHAN_STATUS_RI | \
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DMA_CHAN_STATUS_MSK_COMMON)
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#define DMA_CHAN_STATUS_MSK_TX (DMA_CHAN_STATUS_ETI | \
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DMA_CHAN_STATUS_TBU | \
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DMA_CHAN_STATUS_TPS | \
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DMA_CHAN_STATUS_TI | \
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DMA_CHAN_STATUS_MSK_COMMON)
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/* Interrupt enable bits per channel */
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#define DMA_CHAN_INTR_ENA_NIE BIT(16)
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#define DMA_CHAN_INTR_ENA_AIE BIT(15)
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#define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
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@ -209,7 +161,54 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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#define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
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#define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
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/* channel 0 specific fields */
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#define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
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#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c)
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#define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44)
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#define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4c)
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#define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x50)
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#define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x54)
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#define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x58)
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#define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x5c)
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#define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60)
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/* Interrupt status per channel */
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#define DMA_CHAN_STATUS_REB GENMASK(21, 19)
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#define DMA_CHAN_STATUS_REB_SHIFT 19
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#define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
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#define DMA_CHAN_STATUS_TEB_SHIFT 16
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#define DMA_CHAN_STATUS_NIS BIT(15)
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#define DMA_CHAN_STATUS_AIS BIT(14)
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#define DMA_CHAN_STATUS_CDE BIT(13)
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#define DMA_CHAN_STATUS_FBE BIT(12)
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#define DMA_CHAN_STATUS_ERI BIT(11)
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#define DMA_CHAN_STATUS_ETI BIT(10)
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#define DMA_CHAN_STATUS_RWT BIT(9)
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#define DMA_CHAN_STATUS_RPS BIT(8)
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#define DMA_CHAN_STATUS_RBU BIT(7)
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#define DMA_CHAN_STATUS_RI BIT(6)
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#define DMA_CHAN_STATUS_TBU BIT(2)
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#define DMA_CHAN_STATUS_TPS BIT(1)
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#define DMA_CHAN_STATUS_TI BIT(0)
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#define DMA_CHAN_STATUS_MSK_COMMON (DMA_CHAN_STATUS_NIS | \
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DMA_CHAN_STATUS_AIS | \
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DMA_CHAN_STATUS_CDE | \
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DMA_CHAN_STATUS_FBE)
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#define DMA_CHAN_STATUS_MSK_RX (DMA_CHAN_STATUS_REB | \
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DMA_CHAN_STATUS_ERI | \
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DMA_CHAN_STATUS_RWT | \
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DMA_CHAN_STATUS_RPS | \
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DMA_CHAN_STATUS_RBU | \
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DMA_CHAN_STATUS_RI | \
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DMA_CHAN_STATUS_MSK_COMMON)
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#define DMA_CHAN_STATUS_MSK_TX (DMA_CHAN_STATUS_ETI | \
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DMA_CHAN_STATUS_TBU | \
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DMA_CHAN_STATUS_TPS | \
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DMA_CHAN_STATUS_TI | \
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DMA_CHAN_STATUS_MSK_COMMON)
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#define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
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#define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
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#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
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@ -13,74 +13,69 @@
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/* DMA CRS Control and Status Register Mapping */
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#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
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#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
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#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
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#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
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#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
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#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
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#define DMA_STATUS 0x00001014 /* Status Register */
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#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */
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#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
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#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
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#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
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#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
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#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
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#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
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#define DMA_STATUS_TS_MASK GENMASK(22, 20) /* Transmit Process State */
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#define DMA_STATUS_RS_MASK GENMASK(19, 17) /* Receive Process State */
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#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
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#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
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#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
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#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
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#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
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#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
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#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
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#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
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#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
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#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
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#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
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#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
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DMA_STATUS_AIS | \
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DMA_STATUS_FBI)
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#define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
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DMA_STATUS_RWT | \
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DMA_STATUS_RPS | \
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DMA_STATUS_RU | \
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DMA_STATUS_RI | \
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DMA_STATUS_OVF | \
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DMA_STATUS_MSK_COMMON)
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#define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \
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DMA_STATUS_UNF | \
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DMA_STATUS_TJT | \
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DMA_STATUS_TU | \
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DMA_STATUS_TPS | \
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DMA_STATUS_TI | \
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DMA_STATUS_MSK_COMMON)
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#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
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#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
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#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
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/* Following DMA defines are channels oriented */
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#define DMA_CHAN_BASE_OFFSET 0x100
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static inline u32 dma_chan_base_addr(u32 base, u32 chan)
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{
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return base + chan * DMA_CHAN_BASE_OFFSET;
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}
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#define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)
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#define DMA_CHAN_XMT_POLL_DEMAND(chan) \
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dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)
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#define DMA_CHAN_RCV_POLL_DEMAND(chan) \
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dma_chan_base_addr(DMA_RCV_POLL_DEMAND, chan)
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#define DMA_CHAN_RCV_BASE_ADDR(chan) \
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dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)
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#define DMA_CHAN_TX_BASE_ADDR(chan) \
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dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)
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#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
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#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
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#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
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#define DMA_CHAN_MISSED_FRAME_CTR(chan) \
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dma_chan_base_addr(DMA_MISSED_FRAME_CTR, chan)
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#define DMA_CHAN_RX_WATCHDOG(chan) \
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dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
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/* SW Reset */
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#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
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/* Rx watchdog register */
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#define DMA_RX_WATCHDOG 0x00001024
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/* AXI Master Bus Mode */
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#define DMA_AXI_BUS_MODE 0x00001028
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#define DMA_AXI_EN_LPI BIT(31)
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#define DMA_AXI_LPI_XIT_FRM BIT(30)
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#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
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#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
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#define DMA_AXI_OSR_MAX 0xf
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#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
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(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
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#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
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DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
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DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
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DMA_AXI_BLEN4)
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_AXI_UNDEF BIT(0)
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#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
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#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
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#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */
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/* DMA Control register defines */
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#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
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#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
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#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
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#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
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/* DMA Normal interrupt */
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#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
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#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
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@ -111,52 +106,60 @@ static inline u32 dma_chan_base_addr(u32 base, u32 chan)
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#define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE)
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#define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE)
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/* DMA Status register defines */
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#define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */
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#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
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#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
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#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
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#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
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#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
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#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
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#define DMA_STATUS_TS_MASK GENMASK(22, 20) /* Transmit Process State */
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#define DMA_STATUS_RS_MASK GENMASK(19, 17) /* Receive Process State */
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#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
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#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
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#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
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#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
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#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
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#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
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#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
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#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
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#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
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#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
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#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
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#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
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#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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#define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */
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#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
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#define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \
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DMA_STATUS_AIS | \
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DMA_STATUS_FBI)
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/* Following DMA defines are channels oriented */
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#define DMA_CHAN_BASE_OFFSET 0x100
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#define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \
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DMA_STATUS_RWT | \
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DMA_STATUS_RPS | \
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DMA_STATUS_RU | \
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DMA_STATUS_RI | \
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DMA_STATUS_OVF | \
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DMA_STATUS_MSK_COMMON)
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static inline u32 dma_chan_base_addr(u32 base, u32 chan)
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{
|
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return base + chan * DMA_CHAN_BASE_OFFSET;
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}
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#define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \
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DMA_STATUS_UNF | \
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DMA_STATUS_TJT | \
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DMA_STATUS_TU | \
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DMA_STATUS_TPS | \
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DMA_STATUS_TI | \
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DMA_STATUS_MSK_COMMON)
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#define DMA_CHAN_BUS_MODE(chan) dma_chan_base_addr(DMA_BUS_MODE, chan)
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#define DMA_CHAN_XMT_POLL_DEMAND(chan) \
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dma_chan_base_addr(DMA_XMT_POLL_DEMAND, chan)
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#define DMA_CHAN_RCV_POLL_DEMAND(chan) \
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dma_chan_base_addr(DMA_RCV_POLL_DEMAND, chan)
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#define DMA_CHAN_RCV_BASE_ADDR(chan) \
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dma_chan_base_addr(DMA_RCV_BASE_ADDR, chan)
|
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#define DMA_CHAN_TX_BASE_ADDR(chan) \
|
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dma_chan_base_addr(DMA_TX_BASE_ADDR, chan)
|
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#define DMA_CHAN_STATUS(chan) dma_chan_base_addr(DMA_STATUS, chan)
|
||||
#define DMA_CHAN_CONTROL(chan) dma_chan_base_addr(DMA_CONTROL, chan)
|
||||
#define DMA_CHAN_INTR_ENA(chan) dma_chan_base_addr(DMA_INTR_ENA, chan)
|
||||
#define DMA_CHAN_MISSED_FRAME_CTR(chan) \
|
||||
dma_chan_base_addr(DMA_MISSED_FRAME_CTR, chan)
|
||||
#define DMA_CHAN_RX_WATCHDOG(chan) \
|
||||
dma_chan_base_addr(DMA_RX_WATCHDOG, chan)
|
||||
|
||||
|
||||
/* Rx watchdog register */
|
||||
#define DMA_RX_WATCHDOG 0x00001024
|
||||
|
||||
/* AXI Master Bus Mode */
|
||||
#define DMA_AXI_BUS_MODE 0x00001028
|
||||
|
||||
#define DMA_AXI_EN_LPI BIT(31)
|
||||
#define DMA_AXI_LPI_XIT_FRM BIT(30)
|
||||
#define DMA_AXI_WR_OSR_LMT GENMASK(23, 20)
|
||||
#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
|
||||
|
||||
#define DMA_AXI_OSR_MAX 0xf
|
||||
#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
|
||||
(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
|
||||
#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
|
||||
DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
|
||||
DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
|
||||
DMA_AXI_BLEN4)
|
||||
|
||||
#define DMA_AXI_1KBBE BIT(13)
|
||||
|
||||
#define DMA_AXI_UNDEF BIT(0)
|
||||
|
||||
#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
|
||||
#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
|
||||
#define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */
|
||||
|
||||
#define NUM_DWMAC100_DMA_REGS 9
|
||||
#define NUM_DWMAC1000_DMA_REGS 23
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user