mirror of
https://github.com/torvalds/linux.git
synced 2026-05-28 00:53:34 +02:00
TI K3 device tree updates for v6.18
Generic fixes and cleanups:
* k3-pinctrl: Fix incorrect macro usage, add missing DeepSleep/drive strength
macros
* k3: Rename rproc reserved-mem nodes to 'memory@addr' and add labels for
reserved-memory
* Long time pending major remoteproc firmware refactoring to allow flexibility
for downstream variants:
- am62x/am62ax: Move Mailbox/Remoteproc nodes to board-level DTS files
- am64/am65/j721e/j721s2/j784s4/j742s2/j7200: Move Remoteproc enablement to
board-level DTS
- am62a/am62/am62p/j722s: Similarly restructure Mailbox/Remoteproc configs
- am65/am64: Refactor IPC firmware carveouts/mailboxes into new SoC
family-specific dtsi files
- j721e/j721s2/j784s4/j742s2/am62/am62p/am62a/am64/am65/j7200/j722s: Refactor
IPC firmware configs into new board-independent dtsi files
- Various boards: Add missing or corrected carveouts/timers/mailbox configs
for IPC firmware alignment
* Multiple-boards: Bootph-all property added for USB PHYs to support DFU boot.
New Boards/SoM/SiP:
* Variscite VAR-SOM-AM62P SoM and carrier boards
* AM6254atl SiP package and SK
SoC specific changes:
AM62P:
* Update eMMC HS400 STRB tuning value
* Split HS400 support away from J722S due to errata
* Add Variscite VAR-SOM-AM62P SoM and Symphony carrier board support
AM62:
* Remove unused DeepSleep USB1 pin config on SK
* Add CSI2 interrupts property on main CSI2RX
* Enable Mailbox & Remoteproc at board level
* PocketBeagle2 + Verdin variants: Add missing IPC firmware carveouts, enable
R5F/M4F
AM62A:
* Fix padcfg length in pad configuration registers
* Remove unused DeepSleep USB1 pin config on SK
* Add CSI2 interrupts property
* Add 1.4GHz OPP entry for phyCORE-AM62Ax
* Enable Mailbox & Remoteproc at board level
* Add missing IPC firmware carveouts for PocketBeagle2 and other boards
AM62D2:
* Add Octal SPI NOR flash (OSPI) support for EVM
* Enable USB0/USB1 interface on EVM
AM625:
* Introduce AM6254atl SiP base SoC support
* Add SK-AM6254atl board
AM64:
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
* Add PA stats property for PEB-C-010 expansion Ethernet card
* phyCORE SoM + SR SoM/Electra board: Add missing IPC firmware configs
AM65:
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
AM69:
* Switch SERDES0 config to PCIe Multilink + USB mode, enabling independent
PCIe1 & PCIe3 link speeds
J7200:
* Refactor IPC firmware configs into new dtsi
* Enable R5F Remoteproc at board level
J721E:
* Add DSI + DPHY-TX nodes
* Add CSI2 interrupts property
* BeagleBone AI64: Switch R5 clusters to split mode, add timer reserves for
IPC FW, Correct carveouts (revert mistaken reordering of C6x carveouts)
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
J721S2:
* Add DSI + DSI PHY nodes
* Add USB0 Type-A overlay for EVM
* Add CSI2 interrupts property
* Ensure PCIe node has proper interrupt-controller #address-cells
fixes dtbs_check warning.
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
* Common processor board: Add DisplayPort-1 enable, I2C4 instance for
display connector
J722S:
* Add bootph-all to usb0_phy_ctrl node (DFU)
* Add JPEG Encoder node (E5010)
* Add CSI2 interrupts properties on main/J722S/AM62P common main
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
J784S4/J742S2:
* Add CSI2 interrupts properties on main-common
* Add DSI & PHY support
* Enable DisplayPort-1 on EVM
* Refactor IPC firmware configs into new dtsi (common & SoC-specific)
* Enable Remoteproc at board level
* J742S2: Override MCU R5 firmware names in dedicated dtsi
Board specific changes:
AM62P Variscite Symphony Board:
* Add support with USB, Eth, Camera, CAN, GPIO expander
AM642-phyBOARD-Electra
* Add PEB-C-010 Ethernet expansion board overlay
* Add PA stats handle
AM642-sr/phyCORE
* Add missing IPC carveouts for R5F/M4F
AM62-Verdin/AM62P-Verdin
* Add missing IPC carveouts for R5F/M4F, mailboxes
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Merge tag 'ti-k3-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 device tree updates for v6.18
Generic fixes and cleanups:
* k3-pinctrl: Fix incorrect macro usage, add missing DeepSleep/drive strength
macros
* k3: Rename rproc reserved-mem nodes to 'memory@addr' and add labels for
reserved-memory
* Long time pending major remoteproc firmware refactoring to allow flexibility
for downstream variants:
- am62x/am62ax: Move Mailbox/Remoteproc nodes to board-level DTS files
- am64/am65/j721e/j721s2/j784s4/j742s2/j7200: Move Remoteproc enablement to
board-level DTS
- am62a/am62/am62p/j722s: Similarly restructure Mailbox/Remoteproc configs
- am65/am64: Refactor IPC firmware carveouts/mailboxes into new SoC
family-specific dtsi files
- j721e/j721s2/j784s4/j742s2/am62/am62p/am62a/am64/am65/j7200/j722s: Refactor
IPC firmware configs into new board-independent dtsi files
- Various boards: Add missing or corrected carveouts/timers/mailbox configs
for IPC firmware alignment
* Multiple-boards: Bootph-all property added for USB PHYs to support DFU boot.
New Boards/SoM/SiP:
* Variscite VAR-SOM-AM62P SoM and carrier boards
* AM6254atl SiP package and SK
SoC specific changes:
AM62P:
* Update eMMC HS400 STRB tuning value
* Split HS400 support away from J722S due to errata
* Add Variscite VAR-SOM-AM62P SoM and Symphony carrier board support
AM62:
* Remove unused DeepSleep USB1 pin config on SK
* Add CSI2 interrupts property on main CSI2RX
* Enable Mailbox & Remoteproc at board level
* PocketBeagle2 + Verdin variants: Add missing IPC firmware carveouts, enable
R5F/M4F
AM62A:
* Fix padcfg length in pad configuration registers
* Remove unused DeepSleep USB1 pin config on SK
* Add CSI2 interrupts property
* Add 1.4GHz OPP entry for phyCORE-AM62Ax
* Enable Mailbox & Remoteproc at board level
* Add missing IPC firmware carveouts for PocketBeagle2 and other boards
AM62D2:
* Add Octal SPI NOR flash (OSPI) support for EVM
* Enable USB0/USB1 interface on EVM
AM625:
* Introduce AM6254atl SiP base SoC support
* Add SK-AM6254atl board
AM64:
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
* Add PA stats property for PEB-C-010 expansion Ethernet card
* phyCORE SoM + SR SoM/Electra board: Add missing IPC firmware configs
AM65:
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
AM69:
* Switch SERDES0 config to PCIe Multilink + USB mode, enabling independent
PCIe1 & PCIe3 link speeds
J7200:
* Refactor IPC firmware configs into new dtsi
* Enable R5F Remoteproc at board level
J721E:
* Add DSI + DPHY-TX nodes
* Add CSI2 interrupts property
* BeagleBone AI64: Switch R5 clusters to split mode, add timer reserves for
IPC FW, Correct carveouts (revert mistaken reordering of C6x carveouts)
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
J721S2:
* Add DSI + DSI PHY nodes
* Add USB0 Type-A overlay for EVM
* Add CSI2 interrupts property
* Ensure PCIe node has proper interrupt-controller #address-cells
fixes dtbs_check warning.
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
* Common processor board: Add DisplayPort-1 enable, I2C4 instance for
display connector
J722S:
* Add bootph-all to usb0_phy_ctrl node (DFU)
* Add JPEG Encoder node (E5010)
* Add CSI2 interrupts properties on main/J722S/AM62P common main
* Refactor IPC firmware configs into new dtsi
* Enable Remoteproc at board level
J784S4/J742S2:
* Add CSI2 interrupts properties on main-common
* Add DSI & PHY support
* Enable DisplayPort-1 on EVM
* Refactor IPC firmware configs into new dtsi (common & SoC-specific)
* Enable Remoteproc at board level
* J742S2: Override MCU R5 firmware names in dedicated dtsi
Board specific changes:
AM62P Variscite Symphony Board:
* Add support with USB, Eth, Camera, CAN, GPIO expander
AM642-phyBOARD-Electra
* Add PEB-C-010 Ethernet expansion board overlay
* Add PA stats handle
AM642-sr/phyCORE
* Add missing IPC carveouts for R5F/M4F
AM62-Verdin/AM62P-Verdin
* Add missing IPC carveouts for R5F/M4F, mailboxes
* tag 'ti-k3-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (78 commits)
arm64: dts: ti: k3-j721s2-evm: Add overlay to enable USB0 Type-A
arm64: dts: ti: k3-am642-phyboard-electra: Add PEB-C-010 Overlay
arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board
arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P
arm64: dts: ti: k3-j722s-evm: Add bootph-all tag to usb0_phy_ctrl node
arm64: dts: ti: k3-am62x-sk-common: Add bootph-all tag to usb0_phy_ctrl node
arm64: dts: ti: k3-am62p5-sk: Add bootph-all tag to usb0_phy_ctrl node
arm64: dts: ti: k3-am62a7-sk: Add bootph-all tag to usb0_phy_ctrl node
arm64: dts: ti: k3-j721e-main: Add DSI and DPHY-TX
arm64: dts: ti: k3-pinctrl: Fix the bug in existing macros
arm64: dts: ti: k3-pinctrl: Add the remaining macros
arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS
arm64: dts: ti: k3-am62p5-sk: Remove the unused cfg in USB1_DRVVBUS
arm64: dts: ti: k3-am62d2-evm: Add support for OSPI flash
arm64: dts: ti: k3-am62d2-evm: Enable USB support
arm64: dts: ti: k3-am62a-main: Fix main padcfg length
arm64: dts: ti: k3-am62p: Update eMMC HS400 STRB value
arm64: dts: ti: k3-am62p/j722s: Remove HS400 support from common
arm64: dts: ti: Add support for AM6254atl SiP SK
...
Link: https://lore.kernel.org/r/20250916175349.pxg6gxd4vg5vfmhx@overvalue
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
57cff2159b
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@ -58,6 +58,13 @@ properties:
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- ti,am62-lp-sk
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- const: ti,am625
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- description: K3 AM6254atl SiP
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items:
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- enum:
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- ti,am6254atl-sk
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- const: ti,am6254atl
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- const: ti,am625
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- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards
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items:
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- enum:
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@ -106,6 +113,12 @@ properties:
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- const: toradex,verdin-am62p # Verdin AM62P Module
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- const: ti,am62p5
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- description: K3 AM62P5 SoC Variscite SOM and Carrier Boards
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items:
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- const: variscite,var-som-am62p-symphony
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- const: variscite,var-som-am62p
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- const: ti,am62p5
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- description: K3 AM642 SoC
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items:
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- enum:
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|
|
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@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am62-pocketbeagle2.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6254atl-sk.dtb
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# Boards with AM62Ax SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
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@ -38,6 +39,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb
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# Boards with AM62Px SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62p5-var-som-symphony.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-ivy.dtb
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@ -69,6 +71,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-peb-c-010.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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@ -131,6 +134,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
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k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo
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# Boards with J722s SoC
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dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb
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@ -206,6 +210,8 @@ k3-am642-phyboard-electra-pcie-usb2-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo
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k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo
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k3-am642-phyboard-electra-peb-c-010-dtbs := \
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k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-peb-c-010.dtbo
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k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
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k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
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k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
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@ -230,6 +236,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtbo
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k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
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k3-j721s2-evm-pcie1-ep.dtbo
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k3-j721s2-evm-usb0-type-a-dtbs := k3-j721s2-common-proc-board.dtb \
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k3-j721s2-evm-usb0-type-a.dtbo
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k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \
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k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo
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k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \
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@ -272,6 +280,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
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k3-j721e-evm-pcie1-ep.dtb \
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k3-j721e-sk-csi2-dual-imx219.dtb \
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k3-j721s2-evm-pcie1-ep.dtb \
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k3-j721s2-evm-usb0-type-a.dtb \
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k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
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k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \
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k3-j742s2-evm-usb0-type-a.dtb \
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@ -7,12 +7,20 @@
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/dts-v1/;
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#include "k3-am625.dtsi"
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#include "k3-am62x-sk-common.dtsi"
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/ {
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compatible = "ti,am62-lp-sk", "ti,am625";
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model = "Texas Instruments AM62x LP SK";
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memory@80000000 {
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/* 2G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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device_type = "memory";
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bootph-pre-ram;
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};
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vmain_pd: regulator-0 {
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/* TPS65988 PD CONTROLLER OUTPUT */
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compatible = "regulator-fixed";
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|
|
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|
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@ -808,6 +808,7 @@ mailbox0_cluster0: mailbox@29000000 {
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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status = "disabled";
|
||||
};
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||||
|
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ecap0: pwm@23100000 {
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|
|
@ -1031,6 +1032,9 @@ ti_csi2rx0: ticsi2rx@30102000 {
|
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cdns_csi2rx0: csi-bridge@30101000 {
|
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compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
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||||
reg = <0x00 0x30101000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
|
||||
<&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
|
|||
|
|
@ -46,31 +46,19 @@ ramoops@9c700000 {
|
|||
pmsg-size = <0x8000>;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@9c800000 {
|
||||
rtos_ipc_memory_region: memory@9c800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c800000 0x00 0x00300000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cb00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@9cc00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cc00000 0x00 0xe00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9da00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
|
|
@ -245,20 +233,6 @@ cpsw3g_phy1: ethernet-phy@1 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pktdma {
|
||||
bootph-all;
|
||||
};
|
||||
|
|
@ -364,13 +338,6 @@ i2c_som_rtc: rtc@52 {
|
|||
};
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
|
@ -399,12 +366,4 @@ &sdhci0 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
#include "k3-am62-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -54,18 +54,6 @@ linux,cma {
|
|||
linux,cma-default;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cb00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@9cc00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cc00000 0x00 0xe00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -78,7 +66,13 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9da00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
|
|
@ -292,13 +286,6 @@ &epwm2 {
|
|||
pinctrl-0 = <&epwm2_pins_default>;
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
|
|
@ -349,13 +336,6 @@ &main_i2c2 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_pmx0 {
|
||||
wkup_uart0_pins_default: wkup-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
|
|
@ -519,3 +499,5 @@ ldo4_reg: ldo4 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-am62-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
52
arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi
Normal file
52
arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on AM62 SoCs
|
||||
*
|
||||
* Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_m4fss_dma_memory_region: memory@9cb00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cb00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: memory@9cc00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cc00000 0x00 0xe00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -189,7 +189,7 @@ reg_usb0_vbus: regulator-usb0-vbus {
|
|||
regulator-name = "USB_1_EN";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -206,7 +206,13 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9da00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
|
|
@ -1316,13 +1322,6 @@ &main_i2c3 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin CAN_1 */
|
||||
&main_mcan0 {
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -1506,3 +1505,5 @@ &wkup_uart0 {
|
|||
pinctrl-0 = <&pinctrl_wkup_uart0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
#include "k3-am62-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -128,6 +128,7 @@ wkup_r5fss0_core0: r5f@78000000 {
|
|||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <121>;
|
||||
ti,sci-proc-ids = <0x01 0xff>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
|
|
|
|||
296
arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
Normal file
296
arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Common dtsi for AM625 SK and derivatives
|
||||
*
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am62x-sk-common.dtsi"
|
||||
|
||||
/ {
|
||||
opp-table {
|
||||
/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vmain_pd: regulator-0 {
|
||||
/* TPS65988 PD CONTROLLER OUTPUT */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmain_pd";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vcc_5v0: regulator-1 {
|
||||
/* Output of LM34936 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: regulator-2 {
|
||||
/* output of LM61460-Q1 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-3 {
|
||||
/* TPS22918DBVR */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-4 {
|
||||
/* Output of TLV71033 */
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_5v0>;
|
||||
gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-5 {
|
||||
/* output of TPS6282518DMQ */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc0_pins_default: main-mmc0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
|
||||
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
|
||||
AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
|
||||
AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
|
||||
AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
|
||||
AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
|
||||
AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
|
||||
AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
|
||||
AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
|
||||
AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii2_pins_default: main-rgmii2-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
|
||||
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
|
||||
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
|
||||
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
|
||||
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
|
||||
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
|
||||
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
|
||||
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
|
||||
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
|
||||
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
|
||||
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
|
||||
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
|
||||
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
|
||||
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
|
||||
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
|
||||
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
|
||||
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
|
||||
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
|
||||
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
|
||||
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
|
||||
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
|
||||
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
exp1: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"PRU_DETECT", "MMC1_SD_EN",
|
||||
"VPP_LDO_EN", "EXP_PS_3V3_En",
|
||||
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
|
||||
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
|
||||
"UART1_FET_BUF_EN", "WL_LT_EN",
|
||||
"GPIO_HDMI_RSTn", "CSI_GPIO1",
|
||||
"CSI_GPIO2", "PRU_3V3_EN",
|
||||
"HDMI_INTn", "PD_I2C_IRQ",
|
||||
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
|
||||
"MCASP1_FET_SEL", "UART1_FET_SEL",
|
||||
"TSINT#", "IO_EXP_TEST_LED";
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
/* PCB provides an internal delay of 2ns */
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
&fss {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bootph-all;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x40000>;
|
||||
};
|
||||
|
||||
partition@6c0000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x6c0000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
bootph-pre-ram;
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -7,310 +7,17 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62x-sk-common.dtsi"
|
||||
#include "k3-am625.dtsi"
|
||||
#include "k3-am625-sk-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am625-sk", "ti,am625";
|
||||
model = "Texas Instruments AM625 SK";
|
||||
|
||||
opp-table {
|
||||
/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
|
||||
};
|
||||
|
||||
vmain_pd: regulator-0 {
|
||||
/* TPS65988 PD CONTROLLER OUTPUT */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmain_pd";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_5v0: regulator-1 {
|
||||
/* Output of LM34936 */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_3v3_sys: regulator-2 {
|
||||
/* output of LM61460-Q1 */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vmain_pd>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vdd_mmc1: regulator-3 {
|
||||
/* TPS22918DBVR */
|
||||
bootph-all;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_mmc1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-4 {
|
||||
/* Output of TLV71033 */
|
||||
bootph-all;
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "tlv71033";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vdd_sd_dv_pins_default>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_5v0>;
|
||||
gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-5 {
|
||||
/* output of TPS6282518DMQ */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_3v3_sys>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
device_type = "memory";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
main_mmc0_pins_default: main-mmc0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
|
||||
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
|
||||
AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
|
||||
AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
|
||||
AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
|
||||
AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
|
||||
AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
|
||||
AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
|
||||
AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
|
||||
AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_rgmii2_pins_default: main-rgmii2-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
|
||||
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
|
||||
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
|
||||
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
|
||||
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
|
||||
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
|
||||
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
|
||||
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
|
||||
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
|
||||
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
|
||||
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
|
||||
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
|
||||
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
|
||||
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
|
||||
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
|
||||
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
|
||||
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
|
||||
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
|
||||
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
|
||||
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
|
||||
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
|
||||
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
|
||||
>;
|
||||
};
|
||||
|
||||
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
|
||||
bootph-all;
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_gpio1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
bootph-all;
|
||||
exp1: gpio@22 {
|
||||
bootph-all;
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
|
||||
"PRU_DETECT", "MMC1_SD_EN",
|
||||
"VPP_LDO_EN", "EXP_PS_3V3_En",
|
||||
"EXP_PS_5V0_En", "EXP_HAT_DETECT",
|
||||
"GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
|
||||
"UART1_FET_BUF_EN", "WL_LT_EN",
|
||||
"GPIO_HDMI_RSTn", "CSI_GPIO1",
|
||||
"CSI_GPIO2", "PRU_3V3_EN",
|
||||
"HDMI_INTn", "PD_I2C_IRQ",
|
||||
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
|
||||
"MCASP1_FET_SEL", "UART1_FET_SEL",
|
||||
"TSINT#", "IO_EXP_TEST_LED";
|
||||
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
bootph-all;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_mmc0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
vmmc-supply = <&vdd_mmc1>;
|
||||
vqmmc-supply = <&vdd_sd_dv>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
cpsw3g_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
||||
&fss {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
||||
flash@0 {
|
||||
bootph-all;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
bootph-all;
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x40000>;
|
||||
};
|
||||
|
||||
partition@6c0000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x6c0000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
bootph-pre-ram;
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tlv320aic3106 {
|
||||
DVDD-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
|
|
|||
15
arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts
Normal file
15
arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* AM6254atl SiP SK: https://www.ti.com/lit/df/sprr482b/sprr482b.zip
|
||||
* Webpage: https://www.ti.com/tool/SK-AM62-SIP
|
||||
*
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am6254atl.dtsi"
|
||||
#include "k3-am625-sk-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments AM6254atl SK";
|
||||
compatible = "ti,am6254atl-sk", "ti,am6254atl", "ti,am625";
|
||||
};
|
||||
23
arch/arm64/boot/dts/ti/k3-am6254atl.dtsi
Normal file
23
arch/arm64/boot/dts/ti/k3-am6254atl.dtsi
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* DTS for AM625 SiP SoC family in Quad core configuration and 512MiB RAM.
|
||||
*
|
||||
* Webpage: https://www.ti.com/product/AM625SIP
|
||||
*
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-am625.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments AM6254atl SiP";
|
||||
compatible = "ti,am6254atl", "ti,am625";
|
||||
|
||||
memory@80000000 {
|
||||
/* 512MiB of integrated RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x20000000>;
|
||||
device_type = "memory";
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -267,7 +267,7 @@ secure_proxy_sa3: mailbox@43600000 {
|
|||
|
||||
main_pmx0: pinctrl@f4000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x00 0xf4000 0x00 0x2ac>;
|
||||
reg = <0x00 0xf4000 0x00 0x25c>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
|
|
@ -804,6 +804,7 @@ mailbox0_cluster0: mailbox@29000000 {
|
|||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster1: mailbox@29010000 {
|
||||
|
|
@ -813,6 +814,7 @@ mailbox0_cluster1: mailbox@29010000 {
|
|||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster2: mailbox@29020000 {
|
||||
|
|
@ -822,6 +824,7 @@ mailbox0_cluster2: mailbox@29020000 {
|
|||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox0_cluster3: mailbox@29030000 {
|
||||
|
|
@ -831,6 +834,7 @@ mailbox0_cluster3: mailbox@29030000 {
|
|||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_mcan0: can@20701000 {
|
||||
|
|
@ -1054,6 +1058,9 @@ ti_csi2rx0: ticsi2rx@30102000 {
|
|||
cdns_csi2rx0: csi-bridge@30101000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30101000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
|
||||
<&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
|
|||
|
|
@ -197,6 +197,7 @@ mcu_r5fss0_core0: r5f@79000000 {
|
|||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <9>;
|
||||
ti,sci-proc-ids = <0x03 0xff>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ memory@80000000 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -59,37 +59,13 @@ linux,cma {
|
|||
linux,cma-default;
|
||||
};
|
||||
|
||||
c7x_0_dma_memory_region: c7x-dma-memory@99800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_memory_region: c7x-memory@99900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
|
|
@ -200,11 +176,13 @@ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
|
|||
};
|
||||
};
|
||||
|
||||
&c7x_0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_c7x_0>;
|
||||
memory-region = <&c7x_0_dma_memory_region>,
|
||||
<&c7x_0_memory_region>;
|
||||
status = "okay";
|
||||
&a53_opp_table {
|
||||
/* Requires VDD_CORE at 0v85 */
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
|
|
@ -237,33 +215,6 @@ &fss {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_c7x_0: mbox-c7x-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
|
@ -379,26 +330,6 @@ &main_pktdma {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
/* main_rti4 is used by C7x DSP */
|
||||
&main_rti4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer2 is used by C7x DSP */
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
|
@ -427,12 +358,4 @@ &sdhci0 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
#include "k3-am62a-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
98
arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi
Normal file
98
arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on AM62A SoCs
|
||||
*
|
||||
* Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
c7x_0_dma_memory_region: memory@99800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_memory_region: memory@99900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@9b800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: memory@9b900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_c7x_0: mbox-c7x-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c7x_0 {
|
||||
mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>;
|
||||
memory-region = <&c7x_0_dma_memory_region>,
|
||||
<&c7x_0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* main_rti4 is used by C7x DSP */
|
||||
&main_rti4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer2 is used by C7x DSP */
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
|
@ -127,6 +127,7 @@ wkup_r5fss0_core0: r5f@78000000 {
|
|||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <121>;
|
||||
ti,sci-proc-ids = <0x01 0xff>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ memory@80000000 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -53,37 +53,13 @@ linux,cma {
|
|||
linux,cma-default;
|
||||
};
|
||||
|
||||
c7x_0_dma_memory_region: c7x-dma-memory@99800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_memory_region: c7x-memory@99900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
|
|
@ -713,11 +689,6 @@ &main_uart1 {
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer2 is used by C7x DSP */
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
status = "okay";
|
||||
ti,vbus-divider;
|
||||
|
|
@ -734,6 +705,10 @@ usb0_hs_ep: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&usb0_phy_ctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -835,65 +810,6 @@ &epwm1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_c7x_0: mbox-c7x-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&c7x_0 {
|
||||
mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>;
|
||||
memory-region = <&c7x_0_dma_memory_region>,
|
||||
<&c7x_0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* main_rti4 is used by C7x DSP */
|
||||
&main_rti4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&fss {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -935,3 +851,5 @@ AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
|
|||
>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-am62a-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ aliases {
|
|||
rtc0 = &wkup_rtc0;
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
spi0 = &ospi0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
@ -39,7 +40,7 @@ memory@80000000 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -58,37 +59,13 @@ secure_tfa_ddr: tfa@80000000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_dma_memory_region: c7x-dma-memory@99800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_memory_region: c7x-memory@99900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x99900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
|
|
@ -100,7 +77,7 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a0000000 {
|
||||
rtos_ipc_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x01000000>;
|
||||
no-map;
|
||||
|
|
@ -367,6 +344,32 @@ usr_led_pins_default: usr-led-default-pins {
|
|||
AM62DX_IOPAD(0x0244, PIN_INPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62DX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (D19) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
ospi0_pins_default: ospi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62DX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */
|
||||
AM62DX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */
|
||||
AM62DX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G19) OSPI0_CSn1 */
|
||||
AM62DX_IOPAD(0x0034, PIN_OUTPUT, 0) /* (K20) OSPI0_CSn2 */
|
||||
AM62DX_IOPAD(0x0038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */
|
||||
AM62DX_IOPAD(0x000c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */
|
||||
AM62DX_IOPAD(0x0010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */
|
||||
AM62DX_IOPAD(0x0014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */
|
||||
AM62DX_IOPAD(0x0018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */
|
||||
AM62DX_IOPAD(0x001c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */
|
||||
AM62DX_IOPAD(0x0020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */
|
||||
AM62DX_IOPAD(0x0024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */
|
||||
AM62DX_IOPAD(0x0028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
|
||||
AM62DX_IOPAD(0x0008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_gpio0 {
|
||||
|
|
@ -499,6 +502,11 @@ &main_uart0 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
status = "okay";
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
usb-role-switch;
|
||||
|
||||
|
|
@ -509,6 +517,16 @@ usb0_hs_ep: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb1_pins_default>;
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_rgmii1_pins_default>,
|
||||
|
|
@ -551,65 +569,81 @@ cpsw3g_phy1: ethernet-phy@3 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
&fss {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
status = "okay";
|
||||
|
||||
mbox_c7x_0: mbox-c7x-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
flash@0{
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <8>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-max-frequency = <25000000>;
|
||||
cdns,tshsl-ns = <60>;
|
||||
cdns,tsd2d-ns = <60>;
|
||||
cdns,tchsh-ns = <60>;
|
||||
cdns,tslch-ns = <60>;
|
||||
cdns,read-delay = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ospi.tiboot3";
|
||||
reg = <0x0 0x80000>;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "ospi.tispl";
|
||||
reg = <0x80000 0x200000>;
|
||||
};
|
||||
|
||||
partition@280000 {
|
||||
label = "ospi.u-boot";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
partition@680000 {
|
||||
label = "ospi.env";
|
||||
reg = <0x680000 0x40000>;
|
||||
};
|
||||
|
||||
partition@6c0000 {
|
||||
label = "ospi.env.backup";
|
||||
reg = <0x6c0000 0x40000>;
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ospi.rootfs";
|
||||
reg = <0x800000 0x37c0000>;
|
||||
};
|
||||
|
||||
partition@3fc0000 {
|
||||
label = "ospi.phypattern";
|
||||
reg = <0x3fc0000 0x40000>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
firmware-name = "am62d-mcu-r5f0_0-fw";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c7x_0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_c7x_0>;
|
||||
memory-region = <&c7x_0_dma_memory_region>,
|
||||
<&c7x_0_memory_region>;
|
||||
firmware-name = "am62d-c71_0-fw";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* main_rti4 is used by C7x DSP */
|
||||
&main_rti4 {
|
||||
status = "reserved";
|
||||
};
|
||||
#include "k3-am62a-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -576,15 +576,12 @@ sdhci0: mmc@fa10000 {
|
|||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
ti,clkbuf-sel = <0x7>;
|
||||
ti,strobe-sel = <0x77>;
|
||||
ti,trm-icp = <0x8>;
|
||||
ti,otap-del-sel-legacy = <0x1>;
|
||||
ti,otap-del-sel-mmc-hs = <0x1>;
|
||||
ti,otap-del-sel-ddr52 = <0x6>;
|
||||
ti,otap-del-sel-hs200 = <0x8>;
|
||||
ti,otap-del-sel-hs400 = <0x5>;
|
||||
ti,itap-del-sel-legacy = <0x10>;
|
||||
ti,itap-del-sel-mmc-hs = <0xa>;
|
||||
ti,itap-del-sel-ddr52 = <0x3>;
|
||||
|
|
@ -1045,6 +1042,9 @@ ti_csi2rx0: ticsi2rx@30102000 {
|
|||
cdns_csi2rx0: csi-bridge@30101000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30101000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
|
||||
<&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
|
|||
|
|
@ -205,6 +205,7 @@ mcu_r5fss0_core0: r5f@79000000 {
|
|||
ti,atcm-enable = <0>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -136,6 +136,7 @@ wkup_r5fss0_core0: r5f@78000000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -74,3 +74,9 @@ &main_gpio1 {
|
|||
gpio-reserved-ranges = <32 10>;
|
||||
ti,ngpio = <52>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
mmc-hs400-1_8v;
|
||||
ti,strobe-sel = <0x66>;
|
||||
ti,otap-del-sel-hs400 = <0x5>;
|
||||
};
|
||||
|
|
|
|||
60
arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
Normal file
60
arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on AM62P SoCs
|
||||
*
|
||||
* Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@9b800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: memory@9b900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -147,7 +147,7 @@ reg_vsodimm: regulator-vsodimm {
|
|||
regulator-name = "+V_SODIMM";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -162,7 +162,13 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0x01e00000>;
|
||||
no-map;
|
||||
|
|
@ -830,24 +836,6 @@ &epwm2 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&main0_alert {
|
||||
temperature = <95000>;
|
||||
};
|
||||
|
|
@ -1426,3 +1414,5 @@ &wkup_uart0 {
|
|||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
#include "k3-am62p-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -44,30 +44,18 @@ memory@80000000 {
|
|||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c800000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0xf00000>;
|
||||
no-map;
|
||||
|
|
@ -360,7 +348,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */
|
|||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */
|
||||
AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -607,6 +595,10 @@ usb0_hs_ep: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&usb0_phy_ctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -699,44 +691,6 @@ partition@3fc0000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_uart0_pins_default>;
|
||||
|
|
@ -808,3 +762,5 @@ &epwm1 {
|
|||
pinctrl-0 = <&main_epwm1_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "k3-am62p-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
500
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
Normal file
500
arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
Normal file
|
|
@ -0,0 +1,500 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Variscite Symphony carrier board for VAR-SOM-AM62P
|
||||
*
|
||||
* Link: https://www.variscite.it/product/single-board-computers/symphony-board/
|
||||
*
|
||||
* Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "k3-am62p5-var-som.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Variscite VAR-SOM-AM62P on Symphony-Board";
|
||||
compatible = "variscite,var-som-am62p-symphony", "variscite,var-som-am62p", "ti,am62p5";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cpsw_port1;
|
||||
ethernet1 = &cpsw_port2;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
mmc2 = &sdhci2;
|
||||
serial0 = &main_uart0;
|
||||
serial2 = &main_uart2;
|
||||
serial5 = &main_uart5;
|
||||
serial6 = &main_uart6;
|
||||
spi5 = &main_spi2;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
clk_ov5640_fixed: clock-24000000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button-back {
|
||||
label = "Back";
|
||||
linux,code = <KEY_BACK>;
|
||||
gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button-home {
|
||||
label = "Home";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button-menu {
|
||||
label = "Menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-heartbeat {
|
||||
label = "Heartbeat";
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_2p8v: regulator-2p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2P8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
vin-supply = <®_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1P8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <®_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_1p5v: regulator-1p5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1P5V";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
vin-supply = <®_3v3>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_sdhc1_vmmc: regulator-sdhc1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "+V3.3_SD";
|
||||
vin-supply = <®_sdhc1_vmmc_int>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
reg_sdhc1_vmmc_int: regulator-sdhc1-int {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "+V3.3_SD_INT";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd1_vmmc>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&main_gpio0 53 GPIO_ACTIVE_HIGH>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "+V3.3_SD_VQMMC";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd1_vqmmc>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
gpios = <&main_gpio0 56 GPIO_ACTIVE_HIGH>;
|
||||
states = <1800000 0x0>,
|
||||
<3300000 0x1>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
reg_ov5640_buf_en: regulator-camera-buf-en {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ov5640_buf_en";
|
||||
gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
transceiver1: can-phy {
|
||||
compatible = "ti,tcan1042";
|
||||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
|
||||
connector {
|
||||
compatible = "gpio-usb-b-connector", "usb-b-connector";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_extcon>;
|
||||
label = "USB-C";
|
||||
id-gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usb_con_hs: endpoint {
|
||||
remote-endpoint = <&typec_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cdns_csi2rx0 {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csi0_port0: port@0 {
|
||||
reg = <0>;
|
||||
status = "okay";
|
||||
|
||||
csi2rx0_in_sensor: endpoint {
|
||||
remote-endpoint = <&csi2_cam0>;
|
||||
bus-type = <4>; /* CSI2 DPHY. */
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rgmii1>,
|
||||
<&pinctrl_rgmii2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mdio1>;
|
||||
status = "okay";
|
||||
|
||||
cpsw3g_phy1: ethernet-phy@5 {
|
||||
compatible = "ethernet-phy-id0283.bc30";
|
||||
reg = <5>;
|
||||
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <100000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port2 {
|
||||
/*
|
||||
* The required RGMII TX and RX 2ns delays are implemented directly
|
||||
* in hardware via passive delay elements on the Symphony PCB.
|
||||
* No delay configuration is needed in software via PHY driver.
|
||||
*/
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&cpsw3g_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_i2c0{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
clocks = <&clk_ov5640_fixed>;
|
||||
clock-names = "xclk";
|
||||
AVDD-supply = <®_2p8v>;
|
||||
DOVDD-supply = <®_1p8v>;
|
||||
DVDD-supply = <®_1p5v>;
|
||||
powerdown-gpios = <&main_gpio0 10 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ov5640>;
|
||||
|
||||
port {
|
||||
csi2_cam0: endpoint {
|
||||
remote-endpoint = <&csi2rx0_in_sensor>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* GPIO expander */
|
||||
pca9534: gpio@20 {
|
||||
compatible = "nxp,pca9534";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pca9534>;
|
||||
interrupt-parent = <&main_gpio1>;
|
||||
interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
|
||||
#gpio-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
usb3-sel-hog {
|
||||
gpio-hog;
|
||||
gpios = <4 0>;
|
||||
output-low;
|
||||
line-name = "usb3_sel";
|
||||
};
|
||||
|
||||
eth-som-vselect-hog {
|
||||
gpio-hog;
|
||||
gpios = <6 0>;
|
||||
output-low;
|
||||
line-name = "eth-vselect";
|
||||
};
|
||||
|
||||
eth-mdio-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <7 0>;
|
||||
output-high;
|
||||
line-name = "eth-mdio-enable";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_mcan0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mcan0>;
|
||||
phys = <&transceiver1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
pinctrl_extcon: main-extcon-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c0: main-i2c0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */
|
||||
AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: main-i2c1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */
|
||||
AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pinctrl_mcan0: main-mcan0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */
|
||||
AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mmc1: main-mmc1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */
|
||||
AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */
|
||||
AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */
|
||||
AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */
|
||||
AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */
|
||||
AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */
|
||||
AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pinctrl_rgmii2: main-rgmii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */
|
||||
AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */
|
||||
AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */
|
||||
AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */
|
||||
AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */
|
||||
AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */
|
||||
AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */
|
||||
AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */
|
||||
AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */
|
||||
AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */
|
||||
AM62PX_IOPAD(0x0168, PIN_INPUT_PULLDOWN, 0) /* (D16) RGMII2_TXC */
|
||||
AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spi2: main-spi2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01b0, PIN_INPUT, 1) /* (G20) MCASP0_ACLKR.SPI2_CLK */
|
||||
AM62PX_IOPAD(0x0194, PIN_OUTPUT, 1) /* (D25) MCASP0_AXR3.SPI2_D0 */
|
||||
AM62PX_IOPAD(0x0198, PIN_INPUT, 1) /* (E25) MCASP0_AXR2.SPI2_D1 */
|
||||
AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (G23) MCASP0_AFSR.GPIO1_13 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart0: main-uart0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
|
||||
AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pinctrl_uart2: main-uart2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (AC25) GPMC0_AD8.UART2_RXD */
|
||||
AM62PX_IOPAD(0x0060, PIN_OUTPUT, 2) /* (AB25) GPMC0_AD9.UART2_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart6: main-uart6-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x009c, PIN_INPUT_PULLUP, 3) /* (AD24) GPMC0_WAIT1.UART6_RXD */
|
||||
AM62PX_IOPAD(0x0244, PIN_OUTPUT, 1) /* (D24) MMC1_SDWP.UART6_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb1: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ov5640: main-ov5640-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0028, PIN_OUTPUT, 7) /* (N20) OSPI0_D7.GPIO0_10 */
|
||||
AM62PX_IOPAD(0x0054, PIN_OUTPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */
|
||||
AM62PX_IOPAD(0x0058, PIN_OUTPUT, 7) /* (W25) GPMC0_AD7.GPIO0_22 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pca9534: main-pca9534-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01f0, PIN_INPUT, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sd1_vmmc: main-sd1-vmmc-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */
|
||||
AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 7) /* (AE22) VOUT0_DATA8.GPIO0_53 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pinctrl_sd1_vqmmc: main-sd1-vqmmc-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AE21) VOUT0_DATA11.GPIO0_56 */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
&main_spi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi2>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
cs-gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/* SD Card */
|
||||
vmmc-supply = <®_sdhc1_vmmc>;
|
||||
vqmmc-supply = <®_sdhc1_vqmmc>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc1>;
|
||||
disable-wp;
|
||||
bootph-all;
|
||||
status="okay";
|
||||
};
|
||||
|
||||
&ti_csi2rx0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
usb-role-switch;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
typec_hs: endpoint {
|
||||
remote-endpoint = <&usb_con_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
status = "okay";
|
||||
};
|
||||
387
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
Normal file
387
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
Normal file
|
|
@ -0,0 +1,387 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Common dtsi for Variscite VAR-SOM-AM62P
|
||||
*
|
||||
* Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
|
||||
*
|
||||
* Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include "k3-am62p5.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "variscite,var-som-am62p", "ti,am62p5";
|
||||
|
||||
wifi_pwrseq: wifi-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
post-power-on-delay-ms = <100>;
|
||||
power-off-delay-us = <10000>;
|
||||
reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
|
||||
<&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
|
||||
};
|
||||
|
||||
mmc_pwrseq: mmc-pwrseq {
|
||||
compatible = "mmc-pwrseq-emmc";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc_pwrseq>;
|
||||
reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
/* 8G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
|
||||
<0x00000008 0x80000000 0x00000001 0x80000000>;
|
||||
device_type = "memory";
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
opp-table {
|
||||
/* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-supported-hw = <0x01 0x0004>;
|
||||
clock-latency-ns = <6000000>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b500000 0x00 0x00300000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b800000 0x00 0x00100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9b900000 0x00 0x00f00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c800000 0x00 0x00100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9c900000 0x00 0x01e00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_tfa_ddr: tfa@9e780000 {
|
||||
reg = <0x00 0x9e780000 0x00 0x80000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
secure_ddr: optee@9e800000 {
|
||||
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
reg_3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "On-module +V3.3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_1v8: regulator-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "On-module +V1.8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <®_3v3>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_3v3_phy: regulator-3v3-phy {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "On-module +V3.3_PHY";
|
||||
gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw3g {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rgmii1>;
|
||||
};
|
||||
|
||||
&cpsw3g_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mdio1>;
|
||||
status = "okay";
|
||||
|
||||
cpsw3g_phy0: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-id0283.bc30";
|
||||
reg = <4>;
|
||||
reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <100000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_port1 {
|
||||
/*
|
||||
* The required RGMII TX and RX 2ns delays are implemented directly
|
||||
* in hardware via passive delay elements on the SOM PCB.
|
||||
* No delay configuration is needed in software via PHY driver.
|
||||
*/
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&cpsw3g_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: main-i2c2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
|
||||
AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: main-i2c3-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
|
||||
AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mdio1: main-mdio1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
|
||||
AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mmc2: main-mmc2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
|
||||
AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
|
||||
AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
|
||||
AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
|
||||
AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
|
||||
AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
|
||||
AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rgmii1: main-rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
|
||||
AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
|
||||
AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
|
||||
AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
|
||||
AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
|
||||
AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
|
||||
AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
|
||||
AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
|
||||
AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
|
||||
AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
|
||||
AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
|
||||
AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
|
||||
>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pinctrl_spi0: main-spi0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
|
||||
AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
|
||||
AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
|
||||
AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: main-uart5-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
|
||||
AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
|
||||
AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
|
||||
AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_bt: main-btgrp-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_restouch: main-restouch-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wifi: main-wifi-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
|
||||
AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_pmx0 {
|
||||
pinctrl_wkup_clkout0: wkup-clkout0-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "nxp,88w8987-bt";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
/* On-module eMMC */
|
||||
ti,driver-strength-ohm = <50>;
|
||||
mmc-pwrseq = <&mmc_pwrseq>;
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci2 {
|
||||
/* On-module WiFi */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
ti,fails-without-test-cd;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_gpio_intr {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&wkup_rtc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_rti0 {
|
||||
/* WKUP RTI0 is used by DM firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* WKUP UART0 is used by DM firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* Main UART1 is used by TIFS firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
|
@ -8,7 +8,6 @@
|
|||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include "k3-am625.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
|
|
@ -29,14 +28,7 @@ chosen {
|
|||
stdout-path = "serial2:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
bootph-pre-ram;
|
||||
device_type = "memory";
|
||||
/* 2G RAM */
|
||||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -58,25 +50,13 @@ linux,cma {
|
|||
linux,cma-default;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cb00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@9cc00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9cc00000 0x00 0xe00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9da00000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@9db00000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0x9db00000 0x00 0xc00000>;
|
||||
no-map;
|
||||
|
|
@ -249,7 +229,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */
|
|||
|
||||
main_usb1_pins_default: main-usb1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */
|
||||
AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -477,37 +457,6 @@ cpsw3g_phy0: ethernet-phy@0 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_r5_0: mbox-r5-0 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
|
@ -530,6 +479,10 @@ usb0_hs_ep: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&usb0_phy_ctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -600,3 +553,5 @@ &epwm1 {
|
|||
pinctrl-0 = <&main_epwm1_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "k3-am62-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -921,6 +921,7 @@ main_r5fss0: r5fss@78000000 {
|
|||
<0x78200000 0x00 0x78200000 0x08000>,
|
||||
<0x78300000 0x00 0x78300000 0x08000>;
|
||||
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss0_core0: r5f@78000000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
|
|
@ -935,6 +936,7 @@ main_r5fss0_core0: r5f@78000000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss0_core1: r5f@78200000 {
|
||||
|
|
@ -950,6 +952,7 @@ main_r5fss0_core1: r5f@78200000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -963,6 +966,7 @@ main_r5fss1: r5fss@78400000 {
|
|||
<0x78600000 0x00 0x78600000 0x08000>,
|
||||
<0x78700000 0x00 0x78700000 0x08000>;
|
||||
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss1_core0: r5f@78400000 {
|
||||
compatible = "ti,am64-r5f";
|
||||
|
|
@ -977,6 +981,7 @@ main_r5fss1_core0: r5f@78400000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss1_core1: r5f@78600000 {
|
||||
|
|
@ -992,6 +997,7 @@ main_r5fss1_core1: r5f@78600000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -41,71 +41,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
main_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
main_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
@ -238,43 +184,6 @@ &cpsw_port1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
|
@ -349,37 +258,6 @@ &main_pktdma {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ospi0_pins_default>;
|
||||
|
|
@ -415,3 +293,5 @@ adc {
|
|||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-am64-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
162
arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi
Normal file
162
arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs
|
||||
*
|
||||
* Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
main_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* main_timer8 is used by r5f0-0 */
|
||||
&main_timer8 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer9 is used by r5f0-1 */
|
||||
&main_timer9 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer10 is used by r5f1-0 */
|
||||
&main_timer10 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer11 is used by r5f1-1 */
|
||||
&main_timer11 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -42,7 +42,7 @@ memory@80000000 {
|
|||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -53,71 +53,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
main_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
main_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: regulator-0 {
|
||||
|
|
@ -727,94 +673,6 @@ partition@3fc0000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* main_timer8 is used by r5f0-0 */
|
||||
&main_timer8 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer9 is used by r5f0-1 */
|
||||
&main_timer9 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer10 is used by r5f1-0 */
|
||||
&main_timer10 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer11 is used by r5f1-1 */
|
||||
&main_timer11 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
|
||||
};
|
||||
|
|
@ -878,3 +736,5 @@ &icssg1_iep0 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&icssg1_iep0_pins_default>;
|
||||
};
|
||||
|
||||
#include "k3-am64-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
158
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
Normal file
158
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Copyright (C) 2025 PHYTEC America LLC
|
||||
* Author: Garrett Giordano <ggiordano@phytec.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/net/ti-dp83869.h>
|
||||
#include "k3-pinctrl.h"
|
||||
|
||||
&{/} {
|
||||
aliases {
|
||||
ethernet3 = "/icssg1-ethernet/ethernet-ports/port@0";
|
||||
ethernet4 = "/icssg1-ethernet/ethernet-ports/port@1";
|
||||
};
|
||||
|
||||
icssg1-ethernet {
|
||||
compatible = "ti,am642-icssg-prueth";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>;
|
||||
|
||||
dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
|
||||
<&main_pktdma 0xc201 15>, /* egress slice 0 */
|
||||
<&main_pktdma 0xc202 15>, /* egress slice 0 */
|
||||
<&main_pktdma 0xc203 15>, /* egress slice 0 */
|
||||
<&main_pktdma 0xc204 15>, /* egress slice 1 */
|
||||
<&main_pktdma 0xc205 15>, /* egress slice 1 */
|
||||
<&main_pktdma 0xc206 15>, /* egress slice 1 */
|
||||
<&main_pktdma 0xc207 15>, /* egress slice 1 */
|
||||
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
|
||||
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
|
||||
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
|
||||
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
|
||||
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
|
||||
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
|
||||
"rx0", "rx1",
|
||||
"rxmgm0", "rxmgm1";
|
||||
|
||||
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
|
||||
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
|
||||
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
|
||||
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
|
||||
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
|
||||
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
|
||||
|
||||
interrupt-parent = <&icssg1_intc>;
|
||||
interrupts = <24 0 2>, <25 1 3>;
|
||||
interrupt-names = "tx_ts0", "tx_ts1";
|
||||
sram = <&oc_sram>;
|
||||
|
||||
ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
|
||||
ti,mii-g-rt = <&icssg1_mii_g_rt>;
|
||||
ti,mii-rt = <&icssg1_mii_rt>;
|
||||
ti,pa-stats = <&icssg1_pa_stats>;
|
||||
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
|
||||
ti,pruss-gp-mux-sel = <2>, /* MII mode */
|
||||
<2>,
|
||||
<2>,
|
||||
<2>, /* MII mode */
|
||||
<2>,
|
||||
<2>;
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
icssg1_emac0: port@0 {
|
||||
reg = <0>;
|
||||
phy-handle = <&icssg1_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
/* Filled in by bootloader */
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
ti,syscon-rgmii-delay = <&main_conf 0x4110>;
|
||||
};
|
||||
|
||||
icssg1_emac1: port@1 {
|
||||
reg = <1>;
|
||||
phy-handle = <&icssg1_phy2>;
|
||||
phy-mode = "rgmii-id";
|
||||
/* Filled in by bootloader */
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
ti,syscon-rgmii-delay = <&main_conf 0x4114>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_pmx0 {
|
||||
icssg1_mdio_pins_default: icssg1-mdio-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */
|
||||
AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */
|
||||
>;
|
||||
};
|
||||
|
||||
icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
|
||||
AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
|
||||
AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
|
||||
AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
|
||||
AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
|
||||
AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
|
||||
AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */
|
||||
AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */
|
||||
AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */
|
||||
AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */
|
||||
AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
|
||||
AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
|
||||
>;
|
||||
};
|
||||
|
||||
icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
|
||||
AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
|
||||
AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
|
||||
AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
|
||||
AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
|
||||
AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
|
||||
AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */
|
||||
AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */
|
||||
AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */
|
||||
AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */
|
||||
AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */
|
||||
AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&icssg1_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&icssg1_mdio_pins_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
icssg1_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
rx-internal-delay-ps = <2000>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
|
||||
icssg1_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
rx-internal-delay-ps = <2000>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
|
||||
ti,min-output-impedance;
|
||||
};
|
||||
};
|
||||
|
|
@ -100,6 +100,7 @@ ethernet {
|
|||
ti,mii-g-rt = <&icssg0_mii_g_rt>;
|
||||
ti,mii-rt = <&icssg0_mii_rt>;
|
||||
ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
|
||||
ti,pa-stats = <&icssg0_pa_stats>;
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ memory@80000000 {
|
|||
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -51,71 +51,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
main_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
main_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_m4fss_memory_region: m4f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: regulator-0 {
|
||||
|
|
@ -642,94 +588,6 @@ partition@3fc0000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_m4fss {
|
||||
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
|
||||
memory-region = <&mcu_m4fss_dma_memory_region>,
|
||||
<&mcu_m4fss_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* main_timer8 is used by r5f0-0 */
|
||||
&main_timer8 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer9 is used by r5f0-1 */
|
||||
&main_timer9 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer10 is used by r5f1-0 */
|
||||
&main_timer10 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
/* main_timer11 is used by r5f1-1 */
|
||||
&main_timer11 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
/* PWM is available on Pin 1 of header J3 */
|
||||
|
|
@ -743,3 +601,5 @@ &eqep0 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_eqep0_pins_default>;
|
||||
};
|
||||
|
||||
#include "k3-am64-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ memory@80000000 {
|
|||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -115,53 +115,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
main_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
main_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_mmc0: regulator-vdd-mmc0 {
|
||||
|
|
@ -263,34 +227,6 @@ ethernet_phy2: ethernet-phy@f {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_default_pins>;
|
||||
|
|
@ -488,30 +424,6 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */
|
|||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
/* SoC default UART console */
|
||||
&main_uart0 {
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -590,3 +502,5 @@ &usbss0 {
|
|||
ti,vbus-divider;
|
||||
ti,usb2-only;
|
||||
};
|
||||
|
||||
#include "k3-am64-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ memory@80000000 {
|
|||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -31,59 +31,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
main_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
main_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
reg_1v8: regulator-1v8 {
|
||||
|
|
@ -130,67 +88,6 @@ eeprom1: eeprom@54 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 2>;
|
||||
ti,mbox-tx = <3 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster6 {
|
||||
status = "okay";
|
||||
|
||||
mbox_m4_0: mbox-m4-0 {
|
||||
ti,mbox-rx = <0 0 2>;
|
||||
ti,mbox-tx = <1 0 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -264,3 +161,5 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0)
|
|||
>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-am64-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ chosen {
|
|||
stdout-path = "serial3:115200n8";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -47,36 +47,18 @@ secure_ddr: secure-ddr@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a2000000 {
|
||||
reg = <0x00 0xa2000000 0x00 0x00200000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
/* To reserve the power-on(PON) reason for watchdog reset */
|
||||
wdt_reset_memory_region: wdt-memory@a2200000 {
|
||||
reg = <0x00 0xa2200000 0x00 0x1000>;
|
||||
|
|
@ -582,38 +564,6 @@ &pcie1_rc {
|
|||
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
|
||||
};
|
||||
|
||||
&mcu_rti1 {
|
||||
memory-region = <&wdt_reset_memory_region>;
|
||||
};
|
||||
|
|
@ -686,3 +636,9 @@ &mcu_r5fss0 {
|
|||
/* lock-step mode not supported on iot2050 boards */
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
#include "k3-am65-ti-ipc-firmware.dtsi"
|
||||
|
||||
&rtos_ipc_memory_region {
|
||||
reg = <0x00 0xa2000000 0x00 0x00200000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -408,6 +408,7 @@ mcu_r5fss0: r5fss@41000000 {
|
|||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,am654-r5f";
|
||||
|
|
@ -422,6 +423,7 @@ mcu_r5fss0_core0: r5f@41000000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
|
|
@ -437,6 +439,7 @@ mcu_r5fss0_core1: r5f@41400000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
64
arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi
Normal file
64
arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs
|
||||
*
|
||||
* Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@a2000000 {
|
||||
reg = <0x00 0xa2000000 0x00 0x00100000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -39,7 +39,7 @@ memory@80000000 {
|
|||
<0x00000008 0x80000000 0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
|
@ -50,35 +50,17 @@ secure_ddr: secure-ddr@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa0100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1000000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xa1100000 0 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a2000000 {
|
||||
reg = <0x00 0xa2000000 0x00 0x00100000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
|
|
@ -521,38 +503,6 @@ &serdes1 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -647,3 +597,5 @@ &dss {
|
|||
&wkup_gpio0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
#include "k3-am65-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ &main_spi0 {
|
|||
pinctrl-0 = <&main_spi0_pins>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells= <0>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
&mcu_spi0 {
|
||||
|
|
|
|||
|
|
@ -50,71 +50,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_memory_region: c7x-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_1_memory_region: c7x-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x1c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vsys_5v0: regulator-1 {
|
||||
|
|
@ -453,100 +399,4 @@ &sdhci1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_wkup_r5_0: mbox-wkup-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_c7x_0: mbox-c7x-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5_0: mbox-main-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c7x_1: mbox-c7x-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&c7x_0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
|
||||
memory-region = <&c7x_0_dma_memory_region>,
|
||||
<&c7x_0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c7x_1 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
|
||||
memory-region = <&c7x_1_dma_memory_region>,
|
||||
<&c7x_1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
#include "k3-j722s-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -49,107 +49,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: c71-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a8000000 {
|
||||
reg = <0x00 0xa8000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_sd_dv: regulator-sd {
|
||||
|
|
@ -243,80 +153,6 @@ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */
|
|||
};
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
interrupts = <436>;
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
interrupts = <432>;
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
interrupts = <428>;
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
interrupts = <420>;
|
||||
status = "okay";
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_cpsw {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii1_pins_default>;
|
||||
|
|
@ -367,30 +203,6 @@ &main_gpio0 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&main_sdhci0 {
|
||||
non-removable;
|
||||
|
|
@ -405,51 +217,6 @@ &main_sdhci1 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&ospi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
|
||||
|
|
@ -599,3 +366,5 @@ som_eeprom_opt: eeprom@51 {
|
|||
pagesize = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-j721s2-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -135,6 +135,34 @@ transceiver4: can-phy3 {
|
|||
max-bitrate = <5000000>;
|
||||
};
|
||||
|
||||
edp0_refclk: clock-edp0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
dp0_pwr_3v3: regulator-dp0-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dp0-pwr";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; /*P0 - DP0_3V3 _EN */
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
dp0: dp0-connector {
|
||||
compatible = "dp-connector";
|
||||
label = "DP0";
|
||||
type = "full-size";
|
||||
dp-pwr-supply = <&dp0_pwr_3v3>;
|
||||
|
||||
port {
|
||||
dp0_connector_in: endpoint {
|
||||
remote-endpoint = <&dp0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
connector-hdmi {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
|
|
@ -615,6 +643,39 @@ exp2: gpio@20 {
|
|||
gpio-line-names = "HDMI_PDn","HDMI_LS_OE",
|
||||
"DP0_3V3_EN","eDP_ENABLE";
|
||||
};
|
||||
|
||||
bridge_dsi_edp: bridge-dsi-edp@2c {
|
||||
compatible = "ti,sn65dsi86";
|
||||
reg = <0x2c>;
|
||||
clock-names = "refclk";
|
||||
clocks = <&edp0_refclk>;
|
||||
enable-gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
|
||||
vpll-supply = <&vsys_io_1v8>;
|
||||
vccio-supply = <&vsys_io_1v8>;
|
||||
vcca-supply = <&vsys_io_1v2>;
|
||||
vcc-supply = <&vsys_io_1v2>;
|
||||
|
||||
dsi_edp_bridge_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dp0_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dp0_out: endpoint {
|
||||
remote-endpoint = <&dp0_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_sdhci1 {
|
||||
|
|
@ -711,6 +772,15 @@ dpi_out0: endpoint {
|
|||
remote-endpoint = <&tfp410_in>;
|
||||
};
|
||||
};
|
||||
|
||||
/* DSI */
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
|
|
@ -768,3 +838,30 @@ &usb0 {
|
|||
phys = <&serdes0_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&dphy_tx0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0_ports {
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -27,107 +27,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: c71-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a8000000 {
|
||||
reg = <0x00 0xa8000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -235,141 +145,4 @@ partition@3fc0000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
#include "k3-j721s2-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -49,149 +49,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: c71-dma-memory@a9000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa9000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: c71-memory@a9100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa9100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_2_dma_memory_region: c71-dma-memory@aa000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xaa000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_2_memory_region: c71-memory@aa100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xaa100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_3_dma_memory_region: c71-dma-memory@ab000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xab000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_3_memory_region: c71-memory@ab100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xab100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: regulator-vusb-main5v0 {
|
||||
|
|
@ -640,90 +508,6 @@ &phy_gmii_sel {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
interrupts = <424>;
|
||||
mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "okay";
|
||||
interrupts = <416>;
|
||||
mbox_c71_2: mbox-c71-2 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_3: mbox-c71-3 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* Firmware usage */
|
||||
status = "reserved";
|
||||
|
|
@ -992,135 +776,6 @@ &mcu_cpsw_port1 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer6 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer7 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer8 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer9 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss2 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss2_core0 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
|
||||
memory-region = <&main_r5fss2_core0_dma_memory_region>,
|
||||
<&main_r5fss2_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss2_core1 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
|
||||
memory-region = <&main_r5fss2_core1_dma_memory_region>,
|
||||
<&main_r5fss2_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_2 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
|
||||
memory-region = <&c71_2_dma_memory_region>,
|
||||
<&c71_2_memory_region>;
|
||||
};
|
||||
|
||||
&c71_3 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
|
||||
memory-region = <&c71_3_dma_memory_region>,
|
||||
<&c71_3_memory_region>;
|
||||
};
|
||||
|
||||
&wkup_gpio_intr {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1321,12 +976,20 @@ &serdes_wiz0 {
|
|||
&serdes0 {
|
||||
status = "okay";
|
||||
|
||||
serdes0_pcie_link: phy@0 {
|
||||
serdes0_pcie1_link: phy@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <3>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
|
||||
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
|
||||
};
|
||||
|
||||
serdes0_pcie3_link: phy@2 {
|
||||
reg = <2>;
|
||||
cdns,num-lanes = <1>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_PCIE>;
|
||||
resets = <&serdes_wiz0 3>;
|
||||
};
|
||||
|
||||
serdes0_usb_link: phy@3 {
|
||||
|
|
@ -1364,7 +1027,7 @@ &pcie0_rc {
|
|||
&pcie1_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phys = <&serdes0_pcie1_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <2>;
|
||||
};
|
||||
|
|
@ -1372,7 +1035,7 @@ &pcie1_rc {
|
|||
&pcie3_rc {
|
||||
status = "okay";
|
||||
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
|
||||
phys = <&serdes0_pcie_link>;
|
||||
phys = <&serdes0_pcie3_link>;
|
||||
phy-names = "pcie-phy";
|
||||
num-lanes = <1>;
|
||||
};
|
||||
|
|
@ -1395,3 +1058,6 @@ &usb0 {
|
|||
phys = <&serdes0_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi"
|
||||
#include "k3-j784s4-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -1516,6 +1516,7 @@ main_r5fss0: r5fss@5c00000 {
|
|||
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
|
||||
<0x5d00000 0x00 0x5d00000 0x20000>;
|
||||
power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss0_core0: r5f@5c00000 {
|
||||
compatible = "ti,j7200-r5f";
|
||||
|
|
@ -1530,6 +1531,7 @@ main_r5fss0_core0: r5f@5c00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss0_core1: r5f@5d00000 {
|
||||
|
|
@ -1545,6 +1547,7 @@ main_r5fss0_core1: r5f@5d00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -612,6 +612,7 @@ mcu_r5fss0: r5fss@41000000 {
|
|||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,j7200-r5f";
|
||||
|
|
@ -626,6 +627,7 @@ mcu_r5fss0_core0: r5f@41000000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
|
|
@ -641,6 +643,7 @@ mcu_r5fss0_core1: r5f@41400000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -29,59 +29,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a4000000 {
|
||||
reg = <0x00 0xa4000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
mux0: mux-controller-0 {
|
||||
|
|
@ -224,77 +182,6 @@ partition@800000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
|
@ -537,3 +424,5 @@ &main_mcan0 {
|
|||
pinctrl-names = "default";
|
||||
phys = <&transceiver0>;
|
||||
};
|
||||
|
||||
#include "k3-j7200-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
130
arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi
Normal file
130
arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on J7200 SoCs
|
||||
*
|
||||
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@a4000000 {
|
||||
reg = <0x00 0xa4000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -51,119 +51,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_dma_memory_region: c66-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_memory_region: c66-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_dma_memory_region: c66-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_memory_region: c66-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@aa000000 {
|
||||
reg = <0x00 0xaa000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys {
|
||||
|
|
@ -865,129 +763,4 @@ &ufs_wrapper {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c66_1: mbox-c66-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c66_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
||||
memory-region = <&c66_0_dma_memory_region>,
|
||||
<&c66_0_memory_region>;
|
||||
};
|
||||
|
||||
&c66_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
|
||||
memory-region = <&c66_1_dma_memory_region>,
|
||||
<&c66_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
#include "k3-j721e-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -608,6 +608,9 @@ ti_csi2rx0: ticsi2rx@4500000 {
|
|||
cdns_csi2rx0: csi-bridge@4504000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x0 0x4504000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
|
||||
<&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -661,6 +664,9 @@ ti_csi2rx1: ticsi2rx@4510000 {
|
|||
cdns_csi2rx1: csi-bridge@4514000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x0 0x4514000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
|
||||
<&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -1881,6 +1887,45 @@ port@4 {
|
|||
};
|
||||
};
|
||||
|
||||
dphy2: phy@4480000 {
|
||||
compatible = "ti,j721e-dphy";
|
||||
reg = <0x00 0x04480000 0x00 0x1000>;
|
||||
clocks = <&k3_clks 296 1>, <&k3_clks 296 3>;
|
||||
clock-names = "psm", "pll_ref";
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
|
||||
assigned-clocks = <&k3_clks 296 3>;
|
||||
assigned-clock-parents = <&k3_clks 296 4>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi0: dsi@4800000 {
|
||||
compatible = "ti,j721e-dsi";
|
||||
reg = <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>;
|
||||
clocks = <&k3_clks 150 1>, <&k3_clks 150 5>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&dphy2>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
|
||||
dsi0_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,j721e-dss";
|
||||
reg =
|
||||
|
|
@ -2176,6 +2221,7 @@ main_r5fss0: r5fss@5c00000 {
|
|||
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
|
||||
<0x5d00000 0x00 0x5d00000 0x20000>;
|
||||
power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss0_core0: r5f@5c00000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
|
|
@ -2190,6 +2236,7 @@ main_r5fss0_core0: r5f@5c00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss0_core1: r5f@5d00000 {
|
||||
|
|
@ -2205,6 +2252,7 @@ main_r5fss0_core1: r5f@5d00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -2216,6 +2264,7 @@ main_r5fss1: r5fss@5e00000 {
|
|||
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
|
||||
<0x5f00000 0x00 0x5f00000 0x20000>;
|
||||
power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss1_core0: r5f@5e00000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
|
|
@ -2230,6 +2279,7 @@ main_r5fss1_core0: r5f@5e00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss1_core1: r5f@5f00000 {
|
||||
|
|
@ -2245,6 +2295,7 @@ main_r5fss1_core1: r5f@5f00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -594,6 +594,7 @@ mcu_r5fss0: r5fss@41000000 {
|
|||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,j721e-r5f";
|
||||
|
|
@ -608,6 +609,7 @@ mcu_r5fss0_core0: r5f@41000000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
|
|
@ -623,6 +625,7 @@ mcu_r5fss0_core1: r5f@41400000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -48,119 +48,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_dma_memory_region: c66-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_memory_region: c66-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_dma_memory_region: c66-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_memory_region: c66-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@aa000000 {
|
||||
reg = <0x00 0xaa000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vusb_main: fixedregulator-vusb-main5v0 {
|
||||
|
|
@ -1279,166 +1177,4 @@ &ufs_wrapper {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c66_1: mbox-c66-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer12 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer13 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer14 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer15 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c66_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
||||
memory-region = <&c66_0_dma_memory_region>,
|
||||
<&c66_0_memory_region>;
|
||||
};
|
||||
|
||||
&c66_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
|
||||
memory-region = <&c66_1_dma_memory_region>,
|
||||
<&c66_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
#include "k3-j721e-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -29,119 +29,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_dma_memory_region: c66-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_memory_region: c66-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_dma_memory_region: c66-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_memory_region: c66-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@aa000000 {
|
||||
reg = <0x00 0xaa000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -484,166 +382,4 @@ partition@800000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c66_1: mbox-c66-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer12 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer13 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer14 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer15 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c66_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
||||
memory-region = <&c66_0_dma_memory_region>,
|
||||
<&c66_0_memory_region>;
|
||||
};
|
||||
|
||||
&c66_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
|
||||
memory-region = <&c66_1_dma_memory_region>,
|
||||
<&c66_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
#include "k3-j721e-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
288
arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi
Normal file
288
arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,288 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on J721E SoCs
|
||||
*
|
||||
* Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
/* Carveout locations are flipped due to caching */
|
||||
c66_1_dma_memory_region: memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_0_memory_region: memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
/* Carveout locations are flipped due to caching */
|
||||
c66_0_dma_memory_region: memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c66_1_memory_region: memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@aa000000 {
|
||||
reg = <0x00 0xaa000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_c66_0: mbox-c66-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c66_1: mbox-c66-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer12 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer13 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer14 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer15 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
status = "okay";
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
status = "okay";
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c66_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
|
||||
memory-region = <&c66_0_dma_memory_region>,
|
||||
<&c66_0_memory_region>;
|
||||
};
|
||||
|
||||
&c66_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
|
||||
memory-region = <&c66_1_dma_memory_region>,
|
||||
<&c66_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
|
@ -93,6 +93,28 @@ vdd_sd_dv: gpio-regulator-TLV71033 {
|
|||
<3300000 0x1>;
|
||||
};
|
||||
|
||||
dp1_pwr_3v3: regulator-dp1-prw {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dp1-pwr";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
dp1: connector-dp1 {
|
||||
compatible = "dp-connector";
|
||||
label = "DP1";
|
||||
type = "full-size";
|
||||
dp-pwr-supply = <&dp1_pwr_3v3>;
|
||||
|
||||
port {
|
||||
dp1_connector_in: endpoint {
|
||||
remote-endpoint = <&dp1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
transceiver1: can-phy1 {
|
||||
compatible = "ti,tcan1043";
|
||||
#phy-cells = <0>;
|
||||
|
|
@ -148,6 +170,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
|
|||
>;
|
||||
};
|
||||
|
||||
main_i2c4_pins_default: main-i2c4-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */
|
||||
J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */
|
||||
>;
|
||||
};
|
||||
|
||||
main_i2c5_pins_default: main-i2c5-default-pins {
|
||||
pinctrl-single,pins = <
|
||||
J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */
|
||||
|
|
@ -370,6 +399,23 @@ exp2: gpio@22 {
|
|||
};
|
||||
};
|
||||
|
||||
&main_i2c4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c4_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
exp4: gpio@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "DP0_PWR_SW_EN", "DP1_PWR_SW_EN", "UB981_PDB",
|
||||
"UB981_GPIO0", "UB981_GPIO1", "UB981_GPIO2",
|
||||
"UB981_GPIO3", "PWR_SW_CNTL_DSI0#";
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c5_pins_default>;
|
||||
|
|
@ -539,3 +585,74 @@ &main_mcan5 {
|
|||
pinctrl-0 = <&main_mcan5_pins_default>;
|
||||
phys = <&transceiver4>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
/*
|
||||
* DSS on J721S2-EVM supports DP on VP0 and DSI on VP2.
|
||||
* These clock assignments are chosen to enable the following outputs:
|
||||
* VP0 - DisplayPort SST
|
||||
* VP2 - DSI
|
||||
*/
|
||||
status = "okay";
|
||||
assigned-clocks = <&k3_clks 158 2>,
|
||||
<&k3_clks 158 14>;
|
||||
assigned-clock-parents = <&k3_clks 158 3>,
|
||||
<&k3_clks 158 16>;
|
||||
};
|
||||
|
||||
&dss_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
dpi2_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&dp1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpi2_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_edp_bridge_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dp1_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dp1_out: endpoint {
|
||||
remote-endpoint = <&dp1_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dphy_tx0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
28
arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso
Normal file
28
arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* DT Overlay for enabling USB0 instance of USB in the Host Mode of operation
|
||||
* with the Type-A Connector on the J7 common processor board.
|
||||
*
|
||||
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
|
||||
*
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&exp_som {
|
||||
p0-hog {
|
||||
/* P0 - USB2.0_MUX_SEL */
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "USB2.0_MUX_SEL";
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
|
@ -1248,6 +1248,9 @@ ti_csi2rx0: ticsi2rx@4500000 {
|
|||
cdns_csi2rx0: csi-bridge@4504000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x04504000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
|
||||
<&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -1301,6 +1304,9 @@ ti_csi2rx1: ticsi2rx@4510000 {
|
|||
cdns_csi2rx1: csi-bridge@4514000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x04514000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
|
||||
<&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -1431,6 +1437,7 @@ pcie1_rc: pcie@2910000 {
|
|||
|
||||
pcie1_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
|
||||
|
|
@ -1795,6 +1802,45 @@ main_spi7: spi@2170000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dphy_tx0: phy@4480000 {
|
||||
compatible = "ti,j721e-dphy";
|
||||
reg = <0x00 0x04480000 0x00 0x00001000>;
|
||||
clocks = <&k3_clks 363 8>, <&k3_clks 363 14>;
|
||||
clock-names = "psm", "pll_ref";
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
|
||||
assigned-clocks = <&k3_clks 363 14>;
|
||||
assigned-clock-parents = <&k3_clks 363 15>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi0: dsi@4800000 {
|
||||
compatible = "ti,j721e-dsi";
|
||||
reg = <0x00 0x04800000 0x00 0x00100000>,
|
||||
<0x00 0x04710000 0x00 0x00000100>;
|
||||
clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
||||
interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&dphy_tx0>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
|
||||
dsi0_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dss: dss@4a00000 {
|
||||
compatible = "ti,j721e-dss";
|
||||
reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
|
||||
|
|
@ -1849,6 +1895,7 @@ main_r5fss0: r5fss@5c00000 {
|
|||
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
|
||||
<0x5d00000 0x00 0x5d00000 0x20000>;
|
||||
power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss0_core0: r5f@5c00000 {
|
||||
compatible = "ti,j721s2-r5f";
|
||||
|
|
@ -1863,6 +1910,7 @@ main_r5fss0_core0: r5f@5c00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss0_core1: r5f@5d00000 {
|
||||
|
|
@ -1878,6 +1926,7 @@ main_r5fss0_core1: r5f@5d00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1889,6 +1938,7 @@ main_r5fss1: r5fss@5e00000 {
|
|||
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
|
||||
<0x5f00000 0x00 0x5f00000 0x20000>;
|
||||
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss1_core0: r5f@5e00000 {
|
||||
compatible = "ti,j721s2-r5f";
|
||||
|
|
@ -1903,6 +1953,7 @@ main_r5fss1_core0: r5f@5e00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss1_core1: r5f@5f00000 {
|
||||
|
|
@ -1918,6 +1969,7 @@ main_r5fss1_core1: r5f@5f00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -690,6 +690,7 @@ mcu_r5fss0: r5fss@41000000 {
|
|||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,j721s2-r5f";
|
||||
|
|
@ -704,6 +705,7 @@ mcu_r5fss0_core0: r5f@41000000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
|
|
@ -719,6 +721,7 @@ mcu_r5fss0_core1: r5f@41400000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -31,107 +31,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: c71-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: c71-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a8000000 {
|
||||
reg = <0x00 0xa8000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
mux0: mux-controller-0 {
|
||||
|
|
@ -152,6 +62,30 @@ transceiver0: can-phy0 {
|
|||
#phy-cells = <0>;
|
||||
max-bitrate = <5000000>;
|
||||
};
|
||||
|
||||
vsys_io_1v8: regulator-vsys-io-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_io_1v2: regulator-vsys-io-1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
edp1_refclk: clock-edp1-refclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
|
|
@ -492,141 +426,31 @@ partition@3fc0000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
&main_i2c4 {
|
||||
bridge_dsi_edp: bridge-dsi-edp@2c {
|
||||
compatible = "ti,sn65dsi86";
|
||||
reg = <0x2c>;
|
||||
clock-names = "refclk";
|
||||
clocks = <&edp1_refclk>;
|
||||
enable-gpios = <&exp_som 5 0>;
|
||||
vpll-supply = <&vsys_io_1v8>;
|
||||
vccio-supply = <&vsys_io_1v8>;
|
||||
vcca-supply = <&vsys_io_1v2>;
|
||||
vcc-supply = <&vsys_io_1v2>;
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
dsi_edp_bridge_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
#include "k3-j721s2-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
253
arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi
Normal file
253
arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,253 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on J721S2 SoCs
|
||||
*
|
||||
* Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@a8000000 {
|
||||
reg = <0x00 0xa8000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
|
|
@ -52,71 +52,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
wkup_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
wkup_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_memory_region: c7x-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_1_memory_region: c7x-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x1c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vmain_pd: regulator-0 {
|
||||
|
|
@ -788,104 +734,6 @@ &sdhci1 {
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_wkup_r5_0: mbox-wkup-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_c7x_0: mbox-c7x-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5_0: mbox-main-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c7x_1: mbox-c7x-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&c7x_0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
|
||||
memory-region = <&c7x_0_dma_memory_region>,
|
||||
<&c7x_0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c7x_1 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
|
||||
memory-region = <&c7x_1_dma_memory_region>,
|
||||
<&c7x_1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <J722S_SERDES0_LANE0_USB>,
|
||||
<J722S_SERDES1_LANE0_PCIE0_LANE0>;
|
||||
|
|
@ -936,6 +784,10 @@ &usb0 {
|
|||
usb-role-switch;
|
||||
};
|
||||
|
||||
&usb0_phy_ctrl {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usb1_pins_default>;
|
||||
|
|
@ -996,3 +848,5 @@ &mcu_i2c0 {
|
|||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "k3-j722s-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -168,6 +168,9 @@ ti_csi2rx1: ticsi2rx@30122000 {
|
|||
cdns_csi2rx1: csi-bridge@30121000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30121000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>,
|
||||
<&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -221,6 +224,9 @@ ti_csi2rx2: ticsi2rx@30142000 {
|
|||
cdns_csi2rx2: csi-bridge@30141000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30141000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>,
|
||||
<&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -274,6 +280,9 @@ ti_csi2rx3: ticsi2rx@30162000 {
|
|||
cdns_csi2rx3: csi-bridge@30161000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x30161000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>,
|
||||
<&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -359,6 +368,7 @@ main_r5fss0_core0: r5f@78400000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -385,6 +395,16 @@ c7x_1: dsp@7e200000 {
|
|||
ti,sci-proc-ids = <0x31 0xff>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
e5010: jpeg-encoder@fd20000 {
|
||||
compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc";
|
||||
reg = <0x00 0xfd20000 0x00 0x100>,
|
||||
<0x00 0xfd20200 0x00 0x200>;
|
||||
reg-names = "core", "mmu";
|
||||
clocks = <&k3_clks 201 0>;
|
||||
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_bcdma_csi {
|
||||
|
|
|
|||
163
arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi
Normal file
163
arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on J722S SoCs
|
||||
*
|
||||
* Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_0_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_1_dma_memory_region: memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c7x_1_memory_region: memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@a5000000 {
|
||||
reg = <0x00 0xa5000000 0x00 0x1c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
|
||||
mbox_wkup_r5_0: mbox-wkup-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
|
||||
mbox_mcu_r5_0: mbox-mcu-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
|
||||
mbox_c7x_0: mbox-c7x-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
|
||||
mbox_main_r5_0: mbox-main-r5-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c7x_1: mbox-c7x-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&wkup_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
|
||||
memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
|
||||
<&wkup_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c7x_0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
|
||||
memory-region = <&c7x_0_dma_memory_region>,
|
||||
<&c7x_0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c7x_1 {
|
||||
mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
|
||||
memory-region = <&c7x_1_dma_memory_region>,
|
||||
<&c7x_1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
17
arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi
Normal file
17
arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/*
|
||||
* Device Tree Source for J742S2 SoC Family
|
||||
*
|
||||
* TRM: https://www.ti.com/lit/pdf/spruje3
|
||||
*
|
||||
* Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
*/
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
firmware-name = "j742s2-mcu-r5f0_0-fw";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
firmware-name = "j742s2-mcu-r5f0_1-fw";
|
||||
};
|
||||
|
|
@ -96,3 +96,4 @@ cpu3: cpu@3 {
|
|||
};
|
||||
|
||||
#include "k3-j742s2-main.dtsi"
|
||||
#include "k3-j742s2-mcu-wakeup.dtsi"
|
||||
|
|
|
|||
|
|
@ -27,31 +27,7 @@ memory@80000000 {
|
|||
reserved_memory: reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
c71_3_dma_memory_region: c71-dma-memory@ab000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xab000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_3_memory_region: c71-memory@ab100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xab100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
mbox_c71_3: mbox-c71-3 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&c71_3 {
|
||||
mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
|
||||
memory-region = <&c71_3_dma_memory_region>,
|
||||
<&c71_3_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
#include "k3-j784s4-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -35,137 +35,17 @@ secure_ddr: optee@9e800000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
mcu_r5fss0_core0_dma_memory_region: memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: c71-memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: c71-dma-memory@a9000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa9000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: c71-memory@a9100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa9100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_2_dma_memory_region: c71-dma-memory@aa000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xaa000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_2_memory_region: c71-memory@aa100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xaa100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
evm_12v0: regulator-evm12v0 {
|
||||
|
|
@ -301,6 +181,52 @@ codec_audio: sound {
|
|||
clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000",
|
||||
"cpb-codec-scki", "cpb-codec-scki-48000";
|
||||
};
|
||||
|
||||
vsys_io_1v8: regulator-vsys-io-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vsys_io_1v2: regulator-vsys-io-1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vsys_io_1v2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
edp1_refclk: clock-edp1-refclk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
dp1_pwr_3v3: regulator-dp1-prw {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dp1-pwr";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&exp4 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
dp1: connector-dp1 {
|
||||
compatible = "dp-connector";
|
||||
label = "DP1";
|
||||
type = "full-size";
|
||||
dp-pwr-supply = <&dp1_pwr_3v3>;
|
||||
|
||||
port {
|
||||
dp1_connector_in: endpoint {
|
||||
remote-endpoint = <&dp1_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wkup_gpio0 {
|
||||
|
|
@ -1023,221 +949,6 @@ &main_cpsw1_port1 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "okay";
|
||||
interrupts = <416>;
|
||||
|
||||
mbox_c71_2: mbox-c71-2 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
&main_r5fss2 {
|
||||
ti,cluster-mode = <0>;
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer6 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer7 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer8 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer9 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss2_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
|
||||
memory-region = <&main_r5fss2_core0_dma_memory_region>,
|
||||
<&main_r5fss2_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss2_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
|
||||
memory-region = <&main_r5fss2_core1_dma_memory_region>,
|
||||
<&main_r5fss2_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_2 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
|
||||
memory-region = <&c71_2_dma_memory_region>,
|
||||
<&c71_2_memory_region>;
|
||||
};
|
||||
|
||||
&tscadc0 {
|
||||
pinctrl-0 = <&mcu_adc0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -1340,12 +1051,26 @@ &mhdp {
|
|||
};
|
||||
|
||||
&dss_ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* DP */
|
||||
port {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&dp0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
/* DSI */
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
dpi2_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c4 {
|
||||
|
|
@ -1360,6 +1085,65 @@ exp4: gpio@20 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
bridge_dsi_edp: bridge-dsi-edp@2c {
|
||||
compatible = "ti,sn65dsi86";
|
||||
reg = <0x2c>;
|
||||
clock-names = "refclk";
|
||||
clocks = <&edp1_refclk>;
|
||||
enable-gpios = <&exp4 2 GPIO_ACTIVE_HIGH>;
|
||||
vpll-supply = <&vsys_io_1v8>;
|
||||
vccio-supply = <&vsys_io_1v8>;
|
||||
vcca-supply = <&vsys_io_1v2>;
|
||||
vcc-supply = <&vsys_io_1v2>;
|
||||
|
||||
dsi_edp_bridge_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dp1_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dp1_out: endpoint {
|
||||
remote-endpoint = <&dp1_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi0_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&dp1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpi2_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dphy_tx0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dp0_ports {
|
||||
|
|
@ -1493,3 +1277,5 @@ &mcasp0 {
|
|||
0 0 0 0
|
||||
>;
|
||||
};
|
||||
|
||||
#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi"
|
||||
|
|
|
|||
|
|
@ -819,6 +819,9 @@ ti_csi2rx0: ticsi2rx@4500000 {
|
|||
cdns_csi2rx0: csi-bridge@4504000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x04504000 0x00 0x00001000>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>,
|
||||
<&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -872,6 +875,9 @@ ti_csi2rx1: ticsi2rx@4510000 {
|
|||
cdns_csi2rx1: csi-bridge@4514000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x04514000 0x00 0x00001000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>,
|
||||
<&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -924,6 +930,9 @@ ti_csi2rx2: ticsi2rx@4520000 {
|
|||
cdns_csi2rx2: csi-bridge@4524000 {
|
||||
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
|
||||
reg = <0x00 0x04524000 0x00 0x00001000>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error_irq", "irq";
|
||||
clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>,
|
||||
<&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>;
|
||||
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
|
||||
|
|
@ -2165,6 +2174,7 @@ main_r5fss0: r5fss@5c00000 {
|
|||
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
|
||||
<0x5d00000 0x00 0x5d00000 0x20000>;
|
||||
power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss0_core0: r5f@5c00000 {
|
||||
compatible = "ti,j721s2-r5f";
|
||||
|
|
@ -2179,6 +2189,7 @@ main_r5fss0_core0: r5f@5c00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss0_core1: r5f@5d00000 {
|
||||
|
|
@ -2194,6 +2205,7 @@ main_r5fss0_core1: r5f@5d00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -2205,6 +2217,7 @@ main_r5fss1: r5fss@5e00000 {
|
|||
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
|
||||
<0x5f00000 0x00 0x5f00000 0x20000>;
|
||||
power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss1_core0: r5f@5e00000 {
|
||||
compatible = "ti,j721s2-r5f";
|
||||
|
|
@ -2219,6 +2232,7 @@ main_r5fss1_core0: r5f@5e00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss1_core1: r5f@5f00000 {
|
||||
|
|
@ -2234,6 +2248,7 @@ main_r5fss1_core1: r5f@5f00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -2245,6 +2260,7 @@ main_r5fss2: r5fss@5900000 {
|
|||
ranges = <0x5900000 0x00 0x5900000 0x20000>,
|
||||
<0x5a00000 0x00 0x5a00000 0x20000>;
|
||||
power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
main_r5fss2_core0: r5f@5900000 {
|
||||
compatible = "ti,j721s2-r5f";
|
||||
|
|
@ -2259,6 +2275,7 @@ main_r5fss2_core0: r5f@5900000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
main_r5fss2_core1: r5f@5a00000 {
|
||||
|
|
@ -2274,6 +2291,7 @@ main_r5fss2_core1: r5f@5a00000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -2522,6 +2540,45 @@ watchdog18: watchdog@2550000 {
|
|||
status = "reserved";
|
||||
};
|
||||
|
||||
dphy_tx0: phy@4480000 {
|
||||
compatible = "ti,j721e-dphy";
|
||||
reg = <0x00 0x04480000 0x00 0x00001000>;
|
||||
clocks = <&k3_clks 402 20>, <&k3_clks 402 3>;
|
||||
clock-names = "psm", "pll_ref";
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>;
|
||||
assigned-clocks = <&k3_clks 402 3>;
|
||||
assigned-clock-parents = <&k3_clks 402 4>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi0: dsi@4800000 {
|
||||
compatible = "ti,j721e-dsi";
|
||||
reg = <0x00 0x04800000 0x00 0x00100000>,
|
||||
<0x00 0x04710000 0x00 0x00000100>;
|
||||
clocks = <&k3_clks 215 2>, <&k3_clks 215 5>;
|
||||
clock-names = "dsi_p_clk", "dsi_sys_clk";
|
||||
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
|
||||
interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&dphy_tx0>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
|
||||
dsi0_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mhdp: bridge@a000000 {
|
||||
compatible = "ti,j721e-mhdp8546";
|
||||
reg = <0x0 0xa000000 0x0 0x30a00>,
|
||||
|
|
|
|||
|
|
@ -595,6 +595,7 @@ mcu_r5fss0: r5fss@41000000 {
|
|||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
|
||||
status = "disabled";
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,j721s2-r5f";
|
||||
|
|
@ -609,6 +610,7 @@ mcu_r5fss0_core0: r5f@41000000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
|
|
@ -624,6 +626,7 @@ mcu_r5fss0_core1: r5f@41400000 {
|
|||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,350 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on J784S4/J742S2 SoCs
|
||||
*
|
||||
* Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core0_dma_memory_region: memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core0_memory_region: memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core1_dma_memory_region: memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss2_core1_memory_region: memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: memory@a8000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: memory@a8100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa8100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: memory@a9000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa9000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: memory@a9100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa9100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_2_dma_memory_region: memory@aa000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xaa000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_2_memory_region: memory@aa100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xaa100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster3 {
|
||||
status = "okay";
|
||||
interrupts = <424>;
|
||||
|
||||
mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
status = "okay";
|
||||
interrupts = <416>;
|
||||
|
||||
mbox_c71_2: mbox-c71-2 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer6 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer7 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer8 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer9 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss2 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss2_core0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
|
||||
memory-region = <&main_r5fss2_core0_dma_memory_region>,
|
||||
<&main_r5fss2_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss2_core1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
|
||||
memory-region = <&main_r5fss2_core1_dma_memory_region>,
|
||||
<&main_r5fss2_core1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
|
||||
&c71_2 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
|
||||
memory-region = <&c71_2_dma_memory_region>,
|
||||
<&c71_2_memory_region>;
|
||||
};
|
||||
35
arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi
Normal file
35
arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on J784S4 SoCs
|
||||
*
|
||||
* Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
c71_3_dma_memory_region: memory@ab000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xab000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_3_memory_region: memory@ab100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xab100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster5 {
|
||||
|
||||
mbox_c71_3: mbox-c71-3 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&c71_3 {
|
||||
mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
|
||||
memory-region = <&c71_3_dma_memory_region>,
|
||||
<&c71_3_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -3,15 +3,20 @@
|
|||
* This header provides constants for pinctrl bindings for TI's K3 SoC
|
||||
* family.
|
||||
*
|
||||
* Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#ifndef DTS_ARM64_TI_K3_PINCTRL_H
|
||||
#define DTS_ARM64_TI_K3_PINCTRL_H
|
||||
|
||||
#define WKUP_LVL_EN_SHIFT (7)
|
||||
#define WKUP_LVL_POL_SHIFT (8)
|
||||
#define ST_EN_SHIFT (14)
|
||||
#define PULLUDEN_SHIFT (16)
|
||||
#define PULLTYPESEL_SHIFT (17)
|
||||
#define RXACTIVE_SHIFT (18)
|
||||
#define DRV_STR_SHIFT (19)
|
||||
#define ISO_OVERRIDE_EN_SHIFT (22)
|
||||
#define ISO_BYPASS_EN_SHIFT (23)
|
||||
#define DEBOUNCE_SHIFT (11)
|
||||
#define FORCE_DS_EN_SHIFT (15)
|
||||
#define DS_EN_SHIFT (24)
|
||||
|
|
@ -19,6 +24,7 @@
|
|||
#define DS_OUT_VAL_SHIFT (26)
|
||||
#define DS_PULLUD_EN_SHIFT (27)
|
||||
#define DS_PULLTYPE_SEL_SHIFT (28)
|
||||
#define WKUP_EN_SHIFT (29)
|
||||
|
||||
/* Schmitt trigger configuration */
|
||||
#define ST_DISABLE (0 << ST_EN_SHIFT)
|
||||
|
|
@ -33,6 +39,29 @@
|
|||
#define INPUT_EN (1 << RXACTIVE_SHIFT)
|
||||
#define INPUT_DISABLE (0 << RXACTIVE_SHIFT)
|
||||
|
||||
#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT)
|
||||
#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT)
|
||||
|
||||
#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE)
|
||||
#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE)
|
||||
|
||||
#define DS_STATE_EN (1 << DS_EN_SHIFT)
|
||||
#define DS_STATE_DISABLE (0 << DS_EN_SHIFT)
|
||||
|
||||
#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN)
|
||||
#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN)
|
||||
|
||||
#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT)
|
||||
#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT)
|
||||
|
||||
/* Configuration to enable wake-up on pin activity */
|
||||
#define WKUP_ENABLE (1 << WKUP_EN_SHIFT)
|
||||
#define WKUP_DISABLE (0 << WKUP_EN_SHIFT)
|
||||
#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT)
|
||||
#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT)
|
||||
#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT)
|
||||
#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT)
|
||||
|
||||
/* Only these macros are expected be used directly in device tree files */
|
||||
#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE)
|
||||
#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP)
|
||||
|
|
@ -53,10 +82,14 @@
|
|||
#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT)
|
||||
#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT)
|
||||
|
||||
#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT)
|
||||
#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT)
|
||||
#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT)
|
||||
|
||||
#define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT)
|
||||
#define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT)
|
||||
#define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT)
|
||||
#define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT)
|
||||
#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT)
|
||||
#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT)
|
||||
#define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT)
|
||||
#define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT)
|
||||
#define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT)
|
||||
|
|
@ -65,6 +98,18 @@
|
|||
#define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT)
|
||||
#define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT)
|
||||
#define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT)
|
||||
#define PIN_DS_ISO_BYPASS (1 << ISO_BYPASS_EN_SHIFT)
|
||||
#define PIN_DS_ISO_BYPASS_DISABLE (0 << ISO_BYPASS_EN_SHIFT)
|
||||
|
||||
#define PIN_DS_OUTPUT_LOW (DS_INPUT_DISABLE | DS_OUT_VALUE_ZERO)
|
||||
#define PIN_DS_OUTPUT_HIGH (DS_INPUT_DISABLE | DS_OUT_VALUE_ONE)
|
||||
#define PIN_DS_INPUT (DS_INPUT_EN | DS_PULL_DISABLE)
|
||||
#define PIN_DS_INPUT_PULLUP (DS_INPUT_EN | DS_PULL_UP)
|
||||
#define PIN_DS_INPUT_PULLDOWN (DS_INPUT_EN | DS_PULL_DOWN)
|
||||
|
||||
#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_LOW)
|
||||
#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH)
|
||||
#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE)
|
||||
|
||||
/* Default mux configuration for gpio-ranges to use with pinctrl */
|
||||
#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user