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STM32 DT for v6.18, round 1

Browse Source 
Highlights:
 ----------
 
 - MPU:
   - STM32MP13:
     - Add missing Ethernet1/2 PTP reference clocks.
     - Add Hardware debug port (HDP).
 
   - STMP32MP15:
     - Add resets property to m_can nodes.
     - Add Hardware debug port (HDP) and enable it on stm32mp157c-dk2
       board.
     - Reserve leds for CM4 on stm32mp15xx-ed1 and stm32mp15xx-dkx.
     - stm32mp151c-plyaqm:
         Use correct dai-format property.
 
   - STM32MP23:
     - Add Ethernet1 MAC controller on stm32mp235f-dk board:
       It is connected to a RTL8211F-CG phy through RGMII.
     - Fix GPIO bank definition & memory size (DDR).
 
   - STM32MP25:
     - Add Ethernet1 MAC controller on stm32mp257f-dk board.
       It is connected to a RTL8211F-CG phy through RGMII.
     - Add Ethernet1 MAC controller on stm32mp257f-ev1 board.
       It is connected to a RTL8211F-CG phy through RGMII.
     - Add display support by enabling the following IPs on
       stm32mp257f-ev1:
       * LTDC
       * LVDS
       * WSVGA LVDS panel (1024x600)
       * Panel LVDS backlight as GPIO backlight
       * ILI2511 i2c touchscreen
     - Add PCIe Root complex and Endpoint support on stm32mp257f-ev1.
       Root complex mode is used by default.
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Merge tag 'stm32-dt-for-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt

STM32 DT for v6.18, round 1

Highlights:
----------

- MPU:
  - STM32MP13:
    - Add missing Ethernet1/2 PTP reference clocks.
    - Add Hardware debug port (HDP).

  - STMP32MP15:
    - Add resets property to m_can nodes.
    - Add Hardware debug port (HDP) and enable it on stm32mp157c-dk2
      board.
    - Reserve leds for CM4 on stm32mp15xx-ed1 and stm32mp15xx-dkx.
    - stm32mp151c-plyaqm:
        Use correct dai-format property.

  - STM32MP23:
    - Add Ethernet1 MAC controller on stm32mp235f-dk board:
      It is connected to a RTL8211F-CG phy through RGMII.
    - Fix GPIO bank definition & memory size (DDR).

  - STM32MP25:
    - Add Ethernet1 MAC controller on stm32mp257f-dk board.
      It is connected to a RTL8211F-CG phy through RGMII.
    - Add Ethernet1 MAC controller on stm32mp257f-ev1 board.
      It is connected to a RTL8211F-CG phy through RGMII.
    - Add display support by enabling the following IPs on
      stm32mp257f-ev1:
      * LTDC
      * LVDS
      * WSVGA LVDS panel (1024x600)
      * Panel LVDS backlight as GPIO backlight
      * ILI2511 i2c touchscreen
    - Add PCIe Root complex and Endpoint support on stm32mp257f-ev1.
      Root complex mode is used by default.

* tag 'stm32-dt-for-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (30 commits)
  arm64: dts: st: fix memory region size on stm32mp235f-dk
  arm64: dts: st: remove gpioj and gpiok banks from stm32mp231
  arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk
  arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1
  arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk
  arm64: dts: st: add eth1 pins for stm32mp2x platforms
  ARM: dts: stm32: add missing PTP reference clocks on stm32mp13x SoCs
  arm64: dts: st: enable display support on stm32mp257f-ev1 board
  arm64: dts: st: add clock-cells to syscfg node on stm32mp251
  arm64: dts: st: add lvds support on stm32mp255
  arm64: dts: st: add ltdc support on stm32mp255
  arm64: dts: st: add ltdc support on stm32mp251
  ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153
  dt-binding: can: m_can: add optional resets property
  arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
  arm64: dts: st: Add PCIe Endpoint mode on stm32mp251
  arm64: dts: st: Add PCIe Root Complex mode on stm32mp251
  arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
  arm64: defconfig: Enable STMicroelectronics STM32 DMA3 support
  ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 board
  ...

Link: https://lore.kernel.org/r/13153fc2-1abe-4d53-807a-5d289981a63d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-15 22:07:20 +02:00
commit 2f5049f049
24 changed files with 496 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
View File

@ -50,6 +50,9 @@ properties:
- const: hclk
- const: cclk
resets:
maxItems: 1
bosch,mram-cfg:
description: |
Message RAM configuration data.

9
arch/arm/boot/dts/st/stm32mp131.dtsi
View File

@ -954,6 +954,13 @@ dts: thermal@50028000 {
status = "disabled";
};
hdp: pinctrl@5002a000 {
compatible = "st,stm32mp131-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
status = "disabled";
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
@ -1602,11 +1609,13 @@ ethernet1: ethernet@5800a000 {
"mac-clk-tx",
"mac-clk-rx",
"ethstp",
"ptp_ref",
"eth-ck";
clocks = <&rcc ETH1MAC>,
<&rcc ETH1TX>,
<&rcc ETH1RX>,
<&rcc ETH1STP>,
<&rcc ETH1PTP_K>,
<&rcc ETH1CK_K>;
st,syscon = <&syscfg 0x4 0xff0000>;
snps,mixed-burst;

2
arch/arm/boot/dts/st/stm32mp133.dtsi
View File

@ -81,11 +81,13 @@ ethernet2: ethernet@5800e000 {
"mac-clk-tx",
"mac-clk-rx",
"ethstp",
"ptp_ref",
"eth-ck";
clocks = <&rcc ETH2MAC>,
<&rcc ETH2TX>,
<&rcc ETH2RX>,
<&rcc ETH2STP>,
<&rcc ETH2PTP_K>,
<&rcc ETH2CK_K>;
st,syscon = <&syscfg 0x4 0xff000000>;
snps,mixed-burst;

39
arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
View File

@ -5,6 +5,14 @@
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&hdp {
/omit-if-no-ref/
hdp2_gpo: hdp2-pins {
function = "gpoval2";
pins = "HDP2";
};
};
&pinctrl {
/omit-if-no-ref/
adc1_ain_pins_a: adc1-ain-0 {
@ -731,6 +739,23 @@ pins {
};
};
/omit-if-no-ref/
hdp2_pins_a: hdp2-0 {
pins {
pinmux = <STM32_PINMUX('E', 13, AF0)>; /* HDP2 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
/omit-if-no-ref/
hdp2_sleep_pins_a: hdp2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 13, ANALOG)>; /* HDP2 */
};
};
/omit-if-no-ref/
i2c1_pins_a: i2c1-0 {
pins {
@ -1304,6 +1329,20 @@ pins {
};
};
/omit-if-no-ref/
m4_leds_orange_pins_a: m4-leds-orange-0 {
pins {
pinmux = <STM32_PINMUX('H', 7, RSVD)>;
};
};
/omit-if-no-ref/
m4_leds_orange_pins_b: m4-leds-orange-1 {
pins {
pinmux = <STM32_PINMUX('D', 8, RSVD)>;
};
};
/omit-if-no-ref/
mco1_pins_a: mco1-0 {
pins {

7
arch/arm/boot/dts/st/stm32mp151.dtsi
View File

@ -270,6 +270,13 @@ dts: thermal@50028000 {
status = "disabled";
};
hdp: pinctrl@5002a000 {
compatible = "st,stm32mp151-hdp";
reg = <0x5002a000 0x400>;
clocks = <&rcc HDP>;
status = "disabled";
};
mdma1: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;

4
arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts
View File

@ -239,7 +239,7 @@ &i2s1 {
i2s1_port: port {
i2s1_endpoint: endpoint {
format = "i2s";
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&codec_endpoint>;
};
@ -255,7 +255,7 @@ &m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
reset-names = "mcu_rst", "hold_boot";
};
&mdma1 {

2
arch/arm/boot/dts/st/stm32mp153.dtsi
View File

@ -40,6 +40,7 @@ m_can1: can@4400e000 {
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
resets = <&rcc FDCAN_R>;
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
access-controllers = <&etzpc 62>;
status = "disabled";
@ -54,6 +55,7 @@ m_can2: can@4400f000 {
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
resets = <&rcc FDCAN_R>;
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
access-controllers = <&etzpc 62>;
status = "disabled";

8
arch/arm/boot/dts/st/stm32mp157c-dk2.dts
View File

@ -45,7 +45,6 @@ panel@0 {
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
power-supply = <&v3v3>;
status = "okay";
port {
panel_in: endpoint {
@ -63,6 +62,12 @@ &dsi_out {
remote-endpoint = <&panel_in>;
};
&hdp {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hdp2_gpo &hdp2_pins_a>;
pinctrl-1 = <&hdp2_sleep_pins_a>;
};
&i2c1 {
touchscreen@38 {
compatible = "focaltech,ft6236";
@ -71,7 +76,6 @@ touchscreen@38 {
interrupt-parent = <&gpiof>;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
status = "okay";
};
};

2
arch/arm/boot/dts/st/stm32mp157c-ed1.dts
View File

@ -328,6 +328,8 @@ &m4_rproc {
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
mbox-names = "vq0", "vq1", "shutdown", "detach";
pinctrl-names = "default";
pinctrl-0 = <&m4_leds_orange_pins_b>;
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";

2
arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts
View File

@ -92,7 +92,7 @@ gpu_reserved: gpu@f8000000 {
leds: leds {
compatible = "gpio-leds";
led0{
led0 {
label = "buzzer";
gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
default-state = "off";

2
arch/arm/boot/dts/st/stm32mp157f-dk2.dts
View File

@ -51,7 +51,6 @@ panel@0 {
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
power-supply = <&scmi_v3v3>;
status = "okay";
port {
panel_in: endpoint {
@ -77,7 +76,6 @@ touchscreen@38 {
interrupt-parent = <&gpiof>;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
status = "okay";
};
};

2
arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi
View File

@ -262,7 +262,7 @@ &i2c5 {
status = "okay";
usbhub: usbhub@2c {
compatible ="microchip,usb2514b";
compatible = "microchip,usb2514b";
reg = <0x2c>;
vdd-supply = <&v3v3>;
reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;

1
arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi
View File

@ -62,7 +62,6 @@ &i2c2 {
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;

3
arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
View File

@ -20,7 +20,6 @@ display_bl: display-bl {
default-brightness-level = <8>;
enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_panel_bl>;
status = "okay";
};
gpio-keys-polled {
@ -135,7 +134,6 @@ sound {
"MIC_IN", "Microphone Jack",
"Microphone Jack", "Mic Bias";
dais = <&sai2a_port &sai2b_port>;
status = "okay";
};
};
@ -150,7 +148,6 @@ &i2c2 { /* Header X22 */
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;

2
arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi
View File

@ -269,7 +269,6 @@ pmic: stpmic@33 {
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
@ -388,7 +387,6 @@ onkey {
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
power-off-time-sec = <10>;
status = "okay";
};
watchdog {

2
arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
View File

@ -479,6 +479,8 @@ &m4_rproc {
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
mbox-names = "vq0", "vq1", "shutdown", "detach";
pinctrl-names = "default";
pinctrl-0 = <&m4_leds_orange_pins_a>;
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";

22
arch/arm64/boot/dts/st/stm32mp231.dtsi
View File

@ -1064,28 +1064,6 @@ gpioi: gpio@442c0000 {
st,bank-name = "GPIOI";
status = "disabled";
};
gpioj: gpio@442d0000 {
reg = <0x90000 0x400>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOJ>;
st,bank-name = "GPIOJ";
status = "disabled";
};
gpiok: gpio@442e0000 {
reg = <0xa0000 0x400>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&scmi_clk CK_SCMI_GPIOK>;
st,bank-name = "GPIOK";
status = "disabled";
};
};
rtc: rtc@46000000 {

25
arch/arm64/boot/dts/st/stm32mp235f-dk.dts
View File

@ -19,6 +19,7 @@ / {
compatible = "st,stm32mp235f-dk", "st,stm32mp235";
aliases {
ethernet0 = &ethernet1;
serial0 = &usart2;
};
@ -56,7 +57,7 @@ led-blue {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x0>;
reg = <0x0 0x80000000 0x0 0x80000000>;
};
reserved-memory {
@ -77,6 +78,28 @@ &arm_wdt {
status = "okay";
};
&ethernet1 {
pinctrl-0 = <&eth1_rgmii_pins_b>;
pinctrl-1 = <&eth1_rgmii_sleep_pins_b>;
pinctrl-names = "default", "sleep";
phy-handle = <&phy1_eth1>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1_eth1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <1>;
reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
};
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;

146
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
View File

@ -6,6 +6,132 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
eth1_mdio_pins_a: eth1-mdio-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */
};
};
eth1_rgmii_pins_a: eth1-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins3 {
pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
bias-disable;
};
};
eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */
};
};
eth1_rgmii_pins_b: eth1-rgmii-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, AF12)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */
<STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins3 {
pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
bias-disable;
};
};
eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 {
pins {
pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
};
};
eth2_rgmii_pins_a: eth2-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */
@ -133,6 +259,26 @@ pins {
};
};
pcie_pins_a: pcie-0 {
pins {
pinmux = <STM32_PINMUX('J', 0, AF4)>;
bias-disable;
};
};
pcie_init_pins_a: pcie-init-0 {
pins {
pinmux = <STM32_PINMUX('J', 0, GPIO)>;
output-low;
};
};
pcie_sleep_pins_a: pcie-sleep-0 {
pins {
pinmux = <STM32_PINMUX('J', 0, ANALOG)>;
};
};
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 15, AF7)>; /* TIM3_CH2 */

85
arch/arm64/boot/dts/st/stm32mp251.dtsi
View File

@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec {
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_flexgen_27_fixed: clk-54000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <54000000>;
};
};
firmware {
@ -122,6 +128,15 @@ intc: interrupt-controller@4ac00000 {
<0x0 0x4ac20000 0x0 0x20000>,
<0x0 0x4ac40000 0x0 0x20000>,
<0x0 0x4ac60000 0x0 0x20000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
v2m0: v2m@48090000 {
compatible = "arm,gic-v2m-frame";
reg = <0x0 0x48090000 0x0 0x1000>;
msi-controller;
};
};
psci {
@ -1553,6 +1568,18 @@ trigger@4 {
};
};
ltdc: display-controller@48010000 {
compatible = "st,stm32mp251-ltdc";
reg = <0x48010000 0x400>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>;
clock-names = "lcd", "bus";
resets = <&rcc LTDC_R>;
access-controllers = <&rifsc 80>;
status = "disabled";
};
csi: csi@48020000 {
compatible = "st,stm32mp25-csi";
reg = <0x48020000 0x2000>;
@ -1654,6 +1681,56 @@ stmmac_axi_config_1: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
};
};
pcie_ep: pcie-ep@48400000 {
compatible = "st,stm32mp25-pcie-ep";
reg = <0x48400000 0x100000>,
<0x48500000 0x100000>,
<0x48700000 0x80000>,
<0x10000000 0x10000000>;
reg-names = "dbi", "dbi2", "atu", "addr_space";
clocks = <&rcc CK_BUS_PCIE>;
resets = <&rcc PCIE_R>;
phys = <&combophy PHY_TYPE_PCIE>;
access-controllers = <&rifsc 68>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
};
pcie_rc: pcie@48400000 {
compatible = "st,stm32mp25-pcie-rc";
device_type = "pci";
reg = <0x48400000 0x400000>,
<0x10000000 0x10000>;
reg-names = "dbi", "config";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
<0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
<0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
clocks = <&rcc CK_BUS_PCIE>;
resets = <&rcc PCIE_R>;
msi-parent = <&v2m0>;
access-controllers = <&rifsc 68>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
pcie@0,0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
phys = <&combophy PHY_TYPE_PCIE>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
bsec: efuse@44000000 {
@ -1672,6 +1749,13 @@ package_otp@1e8 {
};
};
hdp: pinctrl@44090000 {
compatible = "st,stm32mp251-hdp";
reg = <0x44090000 0x400>;
clocks = <&rcc CK_BUS_HDP>;
status = "disabled";
};
rcc: clock-controller@44200000 {
compatible = "st,stm32mp25-rcc";
reg = <0x44200000 0x10000>;
@ -1856,6 +1940,7 @@ exti1: interrupt-controller@44220000 {
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
#clock-cells = <0>;
};
pinctrl: pinctrl@44240000 {

18
arch/arm64/boot/dts/st/stm32mp255.dtsi
View File

@ -5,7 +5,25 @@
*/
#include "stm32mp253.dtsi"
&ltdc {
compatible = "st,stm32mp255-ltdc";
clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>;
clock-names = "lcd", "bus", "ref", "lvds";
};
&rifsc {
lvds: lvds@48060000 {
compatible = "st,stm32mp255-lvds", "st,stm32mp25-lvds";
reg = <0x48060000 0x2000>;
#clock-cells = <0>;
clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
clock-names = "pclk", "ref";
resets = <&rcc LVDS_R>;
access-controllers = <&rifsc 84>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
};
vdec: vdec@480d0000 {
compatible = "st,stm32mp25-vdec";
reg = <0x480d0000 0x3c8>;

23
arch/arm64/boot/dts/st/stm32mp257f-dk.dts
View File

@ -19,6 +19,7 @@ / {
compatible = "st,stm32mp257f-dk", "st,stm32mp257";
aliases {
ethernet0 = &ethernet1;
serial0 = &usart2;
};
@ -77,6 +78,28 @@ &arm_wdt {
status = "okay";
};
&ethernet1 {
pinctrl-0 = <&eth1_rgmii_pins_b>;
pinctrl-1 = <&eth1_rgmii_sleep_pins_b>;
pinctrl-names = "default", "sleep";
phy-handle = <&phy1_eth1>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1_eth1: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <1>;
reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
};
&scmi_regu {
scmi_vddio1: regulator@0 {
regulator-min-microvolt = <1800000>;

125
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
View File

@ -19,6 +19,7 @@ / {
aliases {
ethernet0 = &ethernet2;
ethernet1 = &ethernet1;
serial0 = &usart2;
serial1 = &usart6;
};
@ -70,6 +71,42 @@ memory@80000000 {
reg = <0x0 0x80000000 0x1 0x0>;
};
panel_lvds: display {
compatible = "edt,etml0700z9ndha", "panel-lvds";
enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>;
backlight = <&panel_lvds_backlight>;
power-supply = <&scmi_v3v3>;
width-mm = <156>;
height-mm = <92>;
data-mapping = "vesa-24";
status = "okay";
panel-timing {
clock-frequency = <54000000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <150>;
hback-porch = <150>;
hsync-len = <21>;
vfront-porch = <24>;
vback-porch = <24>;
vsync-len = <21>;
};
port {
lvds_panel_in: endpoint {
remote-endpoint = <&lvds_out0>;
};
};
};
panel_lvds_backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
default-on;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -100,7 +137,7 @@ &combophy {
};
&csi {
vdd-supply = <&scmi_vddcore>;
vdd-supply = <&scmi_vddcore>;
vdda18-supply = <&scmi_v1v8>;
status = "okay";
ports {
@ -133,6 +170,29 @@ dcmipp_0: endpoint {
};
};
&ethernet1 {
pinctrl-0 = <&eth1_rgmii_pins_a &eth1_mdio_pins_a>;
pinctrl-1 = <&eth1_rgmii_sleep_pins_a &eth1_mdio_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-handle = <&phy1_eth1>;
phy-mode = "rgmii-id";
st,ext-phyclk;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy1_eth1: ethernet-phy@4 {
compatible = "ethernet-phy-id001c.c916";
reg = <4>;
reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
};
&ethernet2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth2_rgmii_pins_a>;
@ -151,7 +211,7 @@ phy0_eth2: ethernet-phy@1 {
reg = <1>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
};
};
};
@ -183,6 +243,15 @@ imx335_ep: endpoint {
};
};
};
ili2511: ili2511@41 {
compatible = "ilitek,ili251x";
reg = <0x41>;
interrupt-parent = <&gpioi>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpiog 14 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
&i2c8 {
@ -230,6 +299,58 @@ timer {
};
};
&ltdc {
status = "okay";
port {
ltdc_ep0_out: endpoint {
remote-endpoint = <&lvds_in>;
};
};
};
&lvds {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_in: endpoint {
remote-endpoint = <&ltdc_ep0_out>;
};
};
port@1 {
reg = <1>;
lvds_out0: endpoint {
remote-endpoint = <&lvds_panel_in>;
};
};
};
};
&pcie_ep {
pinctrl-names = "default", "init";
pinctrl-0 = <&pcie_pins_a>;
pinctrl-1 = <&pcie_init_pins_a>;
reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
status = "disabled";
};
&pcie_rc {
pinctrl-names = "default", "init", "sleep";
pinctrl-0 = <&pcie_pins_a>;
pinctrl-1 = <&pcie_init_pins_a>;
pinctrl-2 = <&pcie_sleep_pins_a>;
status = "okay";
pcie@0,0 {
reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
};
&rtc {
status = "okay";
};

1
arch/arm64/configs/defconfig
View File

@ -1300,6 +1300,7 @@ CONFIG_RENESAS_USB_DMAC=m
CONFIG_RZ_DMAC=y
CONFIG_TI_K3_UDMA=y
CONFIG_TI_K3_UDMA_GLUE_LAYER=y
CONFIG_STM32_DMA3=m
CONFIG_VFIO=y
CONFIG_VFIO_PCI=y
CONFIG_VIRTIO_PCI=y