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PCI: dwc: Use common D3cold eligibility helper in suspend path

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Previously, the driver skipped putting the link into L2 and device state in
D3cold whenever L1 ASPM was enabled, since some devices (e.g. NVMe) expect
low resume latency and may not tolerate deeper power states. However, such
devices typically remain in D0 and are already covered by the new helper's
requirement that all endpoints be in D3hot before the devices under host
bridge may enter D3cold.

Replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with the
shared pci_host_common_d3cold_possible() helper to decide whether the
devices under host bridge can safely transition to D3cold.

In addition, propagate PME-from-D3cold capability information from the
helper and record it in skip_pwrctrl_off. Some devices (e.g. M.2 cards
without auxiliary power) cannot send PME when the main power is removed,
even if they advertise PME-from-D3cold support. This allows controller
power-off to be skipped when required to preserve wakeup functionality.

While at it, update the 'dw_pcie::suspended' flag in dw_pcie_resume_noirq()
only after the PCIe link resumes successfully, to avoid marking the
controller as active when link resume fails.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: commit log and added TODO to query Vaux]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260429-d3cold-v5-4-89e9735b9df6@oss.qualcomm.com
This commit is contained in:
Krishna Chaitanya Chundru 2026-04-29 12:12:26 +05:30 committed by Manivannan Sadhasivam
parent 8a847d3e9e
commit 56378c03c1
2 changed files with 16 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/pci/controller/dwc/pcie-designware-host.c
View File

@ -16,9 +16,11 @@
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/platform_device.h>
#include "../pci-host-common.h"
#include "../../pci.h"
#include "pcie-designware.h"
@ -1218,18 +1220,14 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
int dw_pcie_suspend_noirq(struct dw_pcie *pci)
{
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
bool pme_capable = false;
int ret = 0;
u32 val;
if (!dw_pcie_link_up(pci))
goto stop_link;
/*
* If L1SS is supported, then do not put the link into L2 as some
* devices such as NVMe expect low resume latency.
*/
if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)
if (!pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable))
return 0;
if (pci->pp.ops->pme_turn_off) {
@ -1273,6 +1271,15 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
udelay(1);
stop_link:
/*
* TODO: "pme_capable" means some downstream device is wakeup-
* enabled and is capable of generating PME from D3cold, which
* requires auxiliary power. Instead of always skipping power off
* if PME is supported from D3cold, query the pwrctrl core and skip
* power off only if device supports PME from D3cold and Vaux is
* not supported.
*/
pci->pp.skip_pwrctrl_off = pme_capable;
dw_pcie_stop_link(pci);
if (pci->pp.ops->deinit)
pci->pp.ops->deinit(&pci->pp);
@ -1290,8 +1297,6 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci)
if (!pci->suspended)
return 0;
pci->suspended = false;
if (pci->pp.ops->init) {
ret = pci->pp.ops->init(&pci->pp);
if (ret) {
@ -1313,6 +1318,8 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci)
if (pci->pp.ops->post_init)
pci->pp.ops->post_init(&pci->pp);
pci->suspended = false;
return 0;
err_stop_link:

1
drivers/pci/controller/dwc/pcie-designware.h
View File

@ -450,6 +450,7 @@ struct dw_pcie_rp {
bool ecam_enabled;
bool native_ecam;
bool skip_l23_ready;
bool skip_pwrctrl_off;
};
struct dw_pcie_ep_ops {