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drm/i915: split out vlv_clock.[ch]

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Move the VLV clock related functions to their own file.

v2: Rebase

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> # v1
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/0bc4a930f3e364c4fc37479f56bf07ccee854fcc.1757688216.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-09-12 17:48:54 +03:00
parent 869d0e9639
commit 5615e78e81
8 changed files with 123 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/i915/Makefile
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@ -300,6 +300,7 @@ i915-y += \
display/skl_scaler.o \
display/skl_universal_plane.o \
display/skl_watermark.o \
display/vlv_clock.o \
display/vlv_sideband.o
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \

1
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@ -49,6 +49,7 @@
#include "intel_vdsc.h"
#include "skl_watermark.h"
#include "skl_watermark_regs.h"
#include "vlv_clock.h"
#include "vlv_dsi.h"
#include "vlv_sideband.h"

74
drivers/gpu/drm/i915/display/intel_display.c
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@ -129,11 +129,9 @@
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
#include "vlv_dpio_phy_regs.h"
#include "vlv_dsi.h"
#include "vlv_dsi_pll.h"
#include "vlv_dsi_regs.h"
#include "vlv_sideband.h"
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
@ -141,78 +139,6 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipe_misc(struct intel_dsb *dsb,
const struct intel_crtc_state *crtc_state);
/* returns HPLL frequency in kHz */
int vlv_clock_get_hpll_vco(struct drm_device *drm)
{
struct intel_display *display = to_intel_display(drm);
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
if (!display->vlv_clock.hpll_freq) {
vlv_cck_get(drm);
/* Obtain SKU information */
hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK;
vlv_cck_put(drm);
display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000;
drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", display->vlv_clock.hpll_freq);
}
return display->vlv_clock.hpll_freq;
}
static int vlv_get_cck_clock(struct drm_device *drm,
const char *name, u32 reg, int ref_freq)
{
u32 val;
int divider;
vlv_cck_get(drm);
val = vlv_cck_read(drm, reg);
vlv_cck_put(drm);
divider = val & CCK_FREQUENCY_VALUES;
drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=
(divider << CCK_FREQUENCY_STATUS_SHIFT),
"%s change in progress\n", name);
return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
}
int vlv_clock_get_hrawclk(struct drm_device *drm)
{
/* RAWCLK_FREQ_VLV register updated from power well code */
return vlv_get_cck_clock(drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
}
int vlv_clock_get_czclk(struct drm_device *drm)
{
struct intel_display *display = to_intel_display(drm);
if (!display->vlv_clock.czclk_freq) {
display->vlv_clock.czclk_freq = vlv_get_cck_clock(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq);
}
return display->vlv_clock.czclk_freq;
}
int vlv_clock_get_cdclk(struct drm_device *drm)
{
return vlv_get_cck_clock(drm, "cdclk", CCK_DISPLAY_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
}
int vlv_clock_get_gpll(struct drm_device *drm)
{
return vlv_get_cck_clock(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
vlv_clock_get_czclk(drm));
}
static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
{
return (crtc_state->active_planes &

5
drivers/gpu/drm/i915/display/intel_display.h
View File

@ -435,11 +435,6 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
void i830_enable_pipe(struct intel_display *display, enum pipe pipe);
void i830_disable_pipe(struct intel_display *display, enum pipe pipe);
int vlv_clock_get_hpll_vco(struct drm_device *drm);
int vlv_clock_get_hrawclk(struct drm_device *drm);
int vlv_clock_get_czclk(struct drm_device *drm);
int vlv_clock_get_cdclk(struct drm_device *drm);
int vlv_clock_get_gpll(struct drm_device *drm);
bool intel_has_pending_fb_unpin(struct intel_display *display);
void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *

81
drivers/gpu/drm/i915/display/vlv_clock.c Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: MIT
/* Copyright © 2025 Intel Corporation */
#include <drm/drm_print.h>
#include "intel_display_core.h"
#include "intel_display_types.h"
#include "vlv_clock.h"
#include "vlv_sideband.h"
/* returns HPLL frequency in kHz */
int vlv_clock_get_hpll_vco(struct drm_device *drm)
{
struct intel_display *display = to_intel_display(drm);
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
if (!display->vlv_clock.hpll_freq) {
vlv_cck_get(drm);
/* Obtain SKU information */
hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK;
vlv_cck_put(drm);
display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000;
drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", display->vlv_clock.hpll_freq);
}
return display->vlv_clock.hpll_freq;
}
static int vlv_get_cck_clock(struct drm_device *drm,
const char *name, u32 reg, int ref_freq)
{
u32 val;
int divider;
vlv_cck_get(drm);
val = vlv_cck_read(drm, reg);
vlv_cck_put(drm);
divider = val & CCK_FREQUENCY_VALUES;
drm_WARN(drm, (val & CCK_FREQUENCY_STATUS) !=
(divider << CCK_FREQUENCY_STATUS_SHIFT),
"%s change in progress\n", name);
return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
}
int vlv_clock_get_hrawclk(struct drm_device *drm)
{
/* RAWCLK_FREQ_VLV register updated from power well code */
return vlv_get_cck_clock(drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
}
int vlv_clock_get_czclk(struct drm_device *drm)
{
struct intel_display *display = to_intel_display(drm);
if (!display->vlv_clock.czclk_freq) {
display->vlv_clock.czclk_freq = vlv_get_cck_clock(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq);
}
return display->vlv_clock.czclk_freq;
}
int vlv_clock_get_cdclk(struct drm_device *drm)
{
return vlv_get_cck_clock(drm, "cdclk", CCK_DISPLAY_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
}
int vlv_clock_get_gpll(struct drm_device *drm)
{
return vlv_get_cck_clock(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
vlv_clock_get_czclk(drm));
}

38
drivers/gpu/drm/i915/display/vlv_clock.h Normal file
View File

@ -0,0 +1,38 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2025 Intel Corporation */
#ifndef __VLV_CLOCK_H__
#define __VLV_CLOCK_H__
struct drm_device;
#ifdef I915
int vlv_clock_get_hpll_vco(struct drm_device *drm);
int vlv_clock_get_hrawclk(struct drm_device *drm);
int vlv_clock_get_czclk(struct drm_device *drm);
int vlv_clock_get_cdclk(struct drm_device *drm);
int vlv_clock_get_gpll(struct drm_device *drm);
#else
static inline int vlv_clock_get_hpll_vco(struct drm_device *drm)
{
return 0;
}
static inline int vlv_clock_get_hrawclk(struct drm_device *drm)
{
return 0;
}
static inline int vlv_clock_get_czclk(struct drm_device *drm)
{
return 0;
}
static inline int vlv_clock_get_cdclk(struct drm_device *drm)
{
return 0;
}
static inline int vlv_clock_get_gpll(struct drm_device *drm)
{
return 0;
}
#endif
#endif /* __VLV_CLOCK_H__ */

2
drivers/gpu/drm/i915/gt/intel_rc6.c
View File

@ -6,7 +6,7 @@
#include <linux/pm_runtime.h>
#include <linux/string_helpers.h>
#include "display/intel_display.h"
#include "display/vlv_clock.h"
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_reg.h"

2
drivers/gpu/drm/i915/gt/intel_rps.c
View File

@ -7,8 +7,8 @@
#include <drm/intel/i915_drm.h>
#include "display/intel_display.h"
#include "display/intel_display_rps.h"
#include "display/vlv_clock.h"
#include "soc/intel_dram.h"
#include "i915_drv.h"