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drm/i915: move hpll and czclk caching under display

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Perhaps not the ideal place, but better than having to have the fields
in both struct drm_i915_private and struct xe_device.

v2: Rebase

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> # v1
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/cbca9b13f2235a624a21bf7617ffe763e25c848c.1757688216.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-09-12 17:48:53 +03:00
parent b478f2035c
commit 869d0e9639
4 changed files with 16 additions and 20 deletions
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22
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -144,22 +144,22 @@ static void bdw_set_pipe_misc(struct intel_dsb *dsb,
/* returns HPLL frequency in kHz */
int vlv_clock_get_hpll_vco(struct drm_device *drm)
{
struct drm_i915_private *i915 = to_i915(drm);
struct intel_display *display = to_intel_display(drm);
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
if (!i915->hpll_freq) {
if (!display->vlv_clock.hpll_freq) {
vlv_cck_get(drm);
/* Obtain SKU information */
hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK;
vlv_cck_put(drm);
i915->hpll_freq = vco_freq[hpll_freq] * 1000;
display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000;
drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", i915->hpll_freq);
drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", display->vlv_clock.hpll_freq);
}
return i915->hpll_freq;
return display->vlv_clock.hpll_freq;
}
static int vlv_get_cck_clock(struct drm_device *drm,
@ -190,15 +190,15 @@ int vlv_clock_get_hrawclk(struct drm_device *drm)
int vlv_clock_get_czclk(struct drm_device *drm)
{
struct drm_i915_private *i915 = to_i915(drm);
struct intel_display *display = to_intel_display(drm);
if (!i915->czclk_freq) {
i915->czclk_freq = vlv_get_cck_clock(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", i915->czclk_freq);
if (!display->vlv_clock.czclk_freq) {
display->vlv_clock.czclk_freq = vlv_get_cck_clock(drm, "czclk", CCK_CZ_CLOCK_CONTROL,
vlv_clock_get_hpll_vco(drm));
drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq);
}
return i915->czclk_freq;
return display->vlv_clock.czclk_freq;
}
int vlv_clock_get_cdclk(struct drm_device *drm)

5
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@ -567,6 +567,11 @@ struct intel_display {
u32 bxt_phy_grc;
} state;
struct {
unsigned int hpll_freq;
unsigned int czclk_freq;
} vlv_clock;
struct {
/* ordered wq for modesets */
struct workqueue_struct *modeset;

3
drivers/gpu/drm/i915/i915_drv.h
View File

@ -239,9 +239,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
unsigned int hpll_freq;
unsigned int czclk_freq;
/**
* wq - Driver workqueue for GEM.
*

6
drivers/gpu/drm/xe/xe_device_types.h
View File

@ -617,12 +617,6 @@ struct xe_device {
struct intel_uncore {
spinlock_t lock;
} uncore;
/* only to allow build, not used functionally */
struct {
unsigned int hpll_freq;
unsigned int czclk_freq;
};
#endif
};