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i.MX arm64 device tree changes for 7.1:

Browse Source 
- New Board Support
   S32N79-RDB, Variscite DART-MX95, DART-MX91 with Sonata carrier boards,
   Verdin iMX95 with multiple carrier boards (Yavia, Mallow, Ivy, Dahlia)
   TQMa93xx/MBa93xxLA-MINI, SolidRun i.MX8MP HummingBoard IIoT,
   SolidRun i.MX8MM SOM and EVB, SolidRun SolidSense-N8 board
   Ka-Ro Electronics tx8m-1610 COM, GOcontroll Moduline IV and Moduline Mini,
   NXP FRDM-IMX91S board, i.MX93 Wireless EVK board with Wireless SiP,
   NXP i.MX8MP audio board v2.
 
 - USB & Type-C Support
   Type-C and USB nodes for imx943, correct power-fole for
   imx8qxp-mek/imx8qm-mek.
 
 - Audio Enhancements
   PDM microphone, bt-sco, and WM8962 sound card support for i.MX952. AONMIX
   MQS for i.MX95. Use audio-graph-card2 for imx8dxl-evk. WM8904 audio codec
   for imx8mm-var-som.
 
 - Thermal & Cooling
   PF09/53 thermal zone, fan node, active cooling on A55, SCMI
   sensor/lmm/cpu for imx943/imx94.
 
 - Display Support
   Multiple LVDS and parallel display overlays for TQ boards (imx91/imx93).
   Parallel display for i.MX93. ontat,kd50g21-40nt-a1 panel for
   imx93-9x9-qsb. pixpaper display overlay for i.MX93 FRDM.
 
 - Networking
   Multiple queue configuration on eqos for TQMa8MPxL.
   MaxLinear PHY support, MCP251xFD CAN controller for imx8mm-var-som.
   SDIO WiFi support (imx91-evk, imx8mp-evk, imx943-evk)
 
 - Bluetooth Support
   imx943-evk, imx93-14x14-evk, imx95-19x19-evk, imx8mp-evk, imx8mn-evk,
   imx8mm-evk.
 
 - Miscellaneous
   xspi and MT35XU01G SPI NOR flash for i.MX952.
   V2X/ELE mailbox nodes, SCMI misc ctrl-ids for imx94.
   eDMA channel reservation for V2X, Cortex M7 support for imx95.
   Ethos-U65 NPU and SRAM nodes for imx93.
   Wire up DMA IRQ for PCIe for imx8qm-ss-hsio.
 
 - Bug Fixes & Improvements
   Complete pinmux for rcwsr12 to fix I2C bus recovery affect other module
   pinmux for layscape platform.
   Multiple bug fixes for GPIO polarity, IRQ types, pinmux configurations.
   GICv3 PPI interrupt CPU mask cleanup across multiple SoCs.
   Fixed Ethernet PHY IRQ types on TQ boards.
   Fixed UART RTS/CTS muxing issues.
   Fixed SD card issues on Kontron boards.
   Fixed touch reset configuration.
   Removed fallback ethernet-phy-ieee802.3-c22 where appropriate.
   Move funnel outside from soc.
   TMU sensor ID cleanup.
   Change usdhc tuning step for eMMC and SD.
   Hexadecimal format, readability improvements, duplicate removal.
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Merge tag 'imx-dt64-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt

Krzysztof notes:
1. This might impact users of i.MX8MM SPDIF as compatible is being
   replaced.

Frank Li writes:

i.MX arm64 device tree changes for 7.1:

- New Board Support
  S32N79-RDB, Variscite DART-MX95, DART-MX91 with Sonata carrier boards,
  Verdin iMX95 with multiple carrier boards (Yavia, Mallow, Ivy, Dahlia)
  TQMa93xx/MBa93xxLA-MINI, SolidRun i.MX8MP HummingBoard IIoT,
  SolidRun i.MX8MM SOM and EVB, SolidRun SolidSense-N8 board
  Ka-Ro Electronics tx8m-1610 COM, GOcontroll Moduline IV and Moduline Mini,
  NXP FRDM-IMX91S board, i.MX93 Wireless EVK board with Wireless SiP,
  NXP i.MX8MP audio board v2.

- USB & Type-C Support
  Type-C and USB nodes for imx943, correct power-fole for
  imx8qxp-mek/imx8qm-mek.

- Audio Enhancements
  PDM microphone, bt-sco, and WM8962 sound card support for i.MX952. AONMIX
  MQS for i.MX95. Use audio-graph-card2 for imx8dxl-evk. WM8904 audio codec
  for imx8mm-var-som.

- Thermal & Cooling
  PF09/53 thermal zone, fan node, active cooling on A55, SCMI
  sensor/lmm/cpu for imx943/imx94.

- Display Support
  Multiple LVDS and parallel display overlays for TQ boards (imx91/imx93).
  Parallel display for i.MX93. ontat,kd50g21-40nt-a1 panel for
  imx93-9x9-qsb. pixpaper display overlay for i.MX93 FRDM.

- Networking
  Multiple queue configuration on eqos for TQMa8MPxL.
  MaxLinear PHY support, MCP251xFD CAN controller for imx8mm-var-som.
  SDIO WiFi support (imx91-evk, imx8mp-evk, imx943-evk)

- Bluetooth Support
  imx943-evk, imx93-14x14-evk, imx95-19x19-evk, imx8mp-evk, imx8mn-evk,
  imx8mm-evk.

- Miscellaneous
  xspi and MT35XU01G SPI NOR flash for i.MX952.
  V2X/ELE mailbox nodes, SCMI misc ctrl-ids for imx94.
  eDMA channel reservation for V2X, Cortex M7 support for imx95.
  Ethos-U65 NPU and SRAM nodes for imx93.
  Wire up DMA IRQ for PCIe for imx8qm-ss-hsio.

- Bug Fixes & Improvements
  Complete pinmux for rcwsr12 to fix I2C bus recovery affect other module
  pinmux for layscape platform.
  Multiple bug fixes for GPIO polarity, IRQ types, pinmux configurations.
  GICv3 PPI interrupt CPU mask cleanup across multiple SoCs.
  Fixed Ethernet PHY IRQ types on TQ boards.
  Fixed UART RTS/CTS muxing issues.
  Fixed SD card issues on Kontron boards.
  Fixed touch reset configuration.
  Removed fallback ethernet-phy-ieee802.3-c22 where appropriate.
  Move funnel outside from soc.
  TMU sensor ID cleanup.
  Change usdhc tuning step for eMMC and SD.
  Hexadecimal format, readability improvements, duplicate removal.

* tag 'imx-dt64-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (139 commits)
  arm64: dts: imx8qxp-mek: switch Type-C connector power-role to dual
  arm64: dts: imx8qm-mek: switch Type-C connector power-role to dual
  arm64: dts: lx2162a-clearfog: set sfp connector leds function and source
  arm64: dts: lx2162a-sr-som: add crypto & rtc aliases, model
  arm64: dts: lx2160a-cex7: add rtc alias
  arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word
  arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes
  arm64: dts: lx2160a: add sda gpio references for i2c bus recovery
  arm64: dts: lx2160a: rename pinmux nodes for readability
  arm64: dts: lx2160a: remove duplicate pinmux nodes
  arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit
  arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
  arm64: dts: freescale: imx8mp-moduline-display-106: add typec-power-opmode property
  arm64: dts: imx8mp-tqma8mpql: Add DT overlays to explicit list
  arm64: dts: imx8mp-evk: Specify ADV7535 register addresses
  arm64: dts: imx8dxl-evk: Use audio-graph-card2 for wm8960-2 and wm8960-3
  arm64: dts: imx943-evk: Add pf09/53 thermal zone
  arm64: dts: imx943-evk: Add fan node and enable active cooling on A55
  arm64: dts: imx943-evk: Add nxp,ctrl-ids for scmi_misc
  arm64: dts: imx943: Add thermal support
  ...

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-04-04 16:30:40 +02:00
commit 55fbbbbed6
124 changed files with 16775 additions and 1342 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
arch/arm64/boot/dts/freescale/Makefile
View File

@ -126,6 +126,8 @@ imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo
imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-hummingboard-ripple.dtb
DTC_FLAGS_imx8mm-hummingboard-ripple += -@
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb
@ -158,7 +160,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
@ -178,7 +183,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb
imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo
imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
@ -189,6 +196,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-rve-gateway.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb
DTC_FLAGS_imx8mn-solidsense-n8-compact += -@
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
@ -212,17 +221,21 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \
imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtb \
imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo
imx8mn-tqma8mqnl-mba8mx-lvds-g133han01-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo
imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo
imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-g133han01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-usbotg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-ab2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-adpismarc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios.dtb
imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-aristainetos3-helios-lvds.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
DTC_FLAGS_imx8mp-cubox-m := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
@ -234,9 +247,27 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb
DTC_FLAGS_imx8mp-hummingboard-iiot := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtbo
imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-a.dtbo
imx8mp-hummingboard-iiot-rs485-a-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-rs485-a.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-b.dtbo
imx8mp-hummingboard-iiot-rs485-b-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-rs485-b.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-b.dtb
DTC_FLAGS_imx8mp-hummingboard-mate := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
DTC_FLAGS_imx8mp-hummingboard-pro := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
DTC_FLAGS_imx8mp-hummingboard-pulse := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb
DTC_FLAGS_imx8mp-hummingboard-ripple := -@
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb
@ -339,8 +370,11 @@ imx8mp-tqma8mpql-mba8mp-ras314-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb
imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo
imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb
@ -406,17 +440,31 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo
imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-rgb-cdtech-dc44.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo
imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
imx93-9x9-qsb-ontat-kd50g21-40nt-a1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb
imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm-pixpaper.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb
@ -425,12 +473,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
imx93-phyboard-nash-jtag-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-jtag.dtbo
imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo
imx93-phyboard-nash-pwm-fan-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-pwm-fan.dtbo
imx93-phyboard-segin-peb-av-02-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-av-02.dtbo
imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo
imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo
imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-jtag.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-pwm-fan.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-02.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb
@ -438,7 +488,19 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini.dtb
imx93-tqma9352-mba91xxca-lvds-tm070jvhg33-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo
imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb
imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb
@ -446,6 +508,17 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
@ -501,4 +574,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
dtb-$(CONFIG_ARCH_S32) += s32n79-rdb.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb

15
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -114,14 +114,10 @@ optee: optee {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
@ -138,8 +134,7 @@ gic: interrupt-controller@6000000 {
<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;

10
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
View File

@ -14,6 +14,7 @@ / {
aliases {
crypto = &crypto;
rtc0 = &com_rtc;
};
sb_3v3: regulator-sb3v3 {
@ -154,7 +155,7 @@ &i2c2 {
&i2c4 {
status = "okay";
rtc@51 {
com_rtc: rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>;
@ -162,6 +163,8 @@ rtc@51 {
};
&fspi {
pinctrl-names = "default";
pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@ -177,6 +180,11 @@ flash@0 {
};
};
&pinmux_i2crv {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_14_12_pins>;
};
&usb0 {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
View File

@ -89,6 +89,8 @@ &emdio2 {
};
&esdhc0 {
pinctrl-names = "default";
pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;

185
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -750,9 +750,10 @@ i2c0: i2c@2000000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c0_scl>;
pinctrl-1 = <&i2c0_scl_gpio>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-1 = <&gpio0_3_2_pins>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -766,9 +767,10 @@ i2c1: i2c@2010000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c1_scl>;
pinctrl-1 = <&i2c1_scl_gpio>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&gpio0_31_30_pins>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -782,9 +784,10 @@ i2c2: i2c@2020000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c2_scl>;
pinctrl-1 = <&i2c2_scl_gpio>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&gpio0_29_28_pins>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -798,9 +801,10 @@ i2c3: i2c@2030000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c3_scl>;
pinctrl-1 = <&i2c3_scl_gpio>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-1 = <&gpio0_27_26_pins>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -814,9 +818,10 @@ i2c4: i2c@2040000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c4_scl>;
pinctrl-1 = <&i2c4_scl_gpio>;
pinctrl-0 = <&i2c4_pins>;
pinctrl-1 = <&gpio0_25_24_pins>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -830,9 +835,10 @@ i2c5: i2c@2050000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c5_scl>;
pinctrl-1 = <&i2c5_scl_gpio>;
pinctrl-0 = <&i2c5_pins>;
pinctrl-1 = <&gpio0_23_22_pins>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -846,9 +852,10 @@ i2c6: i2c@2060000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c6_scl>;
pinctrl-1 = <&i2c6_scl_gpio>;
pinctrl-0 = <&i2c6_i2c7_pins>;
pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -862,9 +869,10 @@ i2c7: i2c@2070000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c7_scl>;
pinctrl-1 = <&i2c7_scl_gpio>;
pinctrl-0 = <&i2c6_i2c7_pins>;
pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@ -1713,68 +1721,159 @@ pinmux_i2crv: pinmux@70010012c {
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
i2c1_scl: i2c1-scl-pins {
pinctrl-single,bits = <0x0 0 0x7>;
/* RCWSR12 */
i2c1_pins: iic2-i2c-pins {
pinctrl-single,bits = <0x0 0x0 0x7>;
};
i2c1_scl_gpio: i2c1-scl-gpio-pins {
gpio0_31_30_pins: iic2-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
i2c2_scl: i2c2-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
ftm0_ch10_pins: iic2-ftm-pins {
pinctrl-single,bits = <0x0 0x2 0x7>;
};
i2c2_scl_gpio: i2c2-scl-gpio-pins {
esdhc0_cd_wp_pins: iic2-sdhc-pins {
pinctrl-single,bits = <0x0 0x6 0x7>;
};
i2c2_pins: iic3-i2c-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>;
};
gpio0_29_28_pins: iic3-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
i2c3_scl: i2c3-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
can0_pins: iic3-can-pins {
pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>;
};
i2c3_scl_gpio: i2c3-scl-gpio-pins {
event65_pins: iic3-event-pins {
pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>;
};
i2c3_pins: iic4-i2c-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>;
};
gpio0_27_26_pins: iic4-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
i2c4_scl: i2c4-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
can1_pins: iic4-can-pins {
pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>;
};
i2c4_scl_gpio: i2c4-scl-gpio-pins {
event87_pins: iic4-event-pins {
pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>;
};
i2c4_pins: iic5-i2c-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>;
};
gpio0_25_24_pins: iic5-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
i2c5_scl: i2c5-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
esdhc0_clksync_pins: iic5-sdhc-clk-pins {
pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>;
};
i2c5_scl_gpio: i2c5-scl-gpio-pins {
dspi2_miso_mosi_pins: iic5-spi3-pins {
pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>;
};
i2c5_pins: iic6-i2c-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>;
};
gpio0_23_22_pins: iic6-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
i2c6_scl: i2c6-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
esdhc1_clksync_pins: iic6-sdhc-clk-pins {
pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>;
};
i2c6_scl_gpio: i2c6-scl-gpio-pins {
fspi_data74_pins: xspi1-data74-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
};
gpio1_31_28_pins: xspi1-data74-gpio-pins {
pinctrl-single,bits = <0x0 0x1 (0x7 << 15)>;
};
fspi_data30_pins: xspi1-data30-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
};
gpio1_27_24_pins: xspi1-data30-gpio-pins {
pinctrl-single,bits = <0x0 0x1 (0x7 << 18)>;
};
fspi_dqs_sck_cs10_pins: xspi1-base-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
};
gpio1_23_20_pins: xspi1-base-gpio-pins {
pinctrl-single,bits = <0x0 0x1 (0x7 << 21)>;
};
esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
};
gpio0_21_15_pins: sdhc1-base-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>;
};
dspi0_pins: sdhc1-base-spi1-pins {
pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>;
};
esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>;
};
esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>;
};
esdhc0_dir_pins: sdhc1-dir-pins {
pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>;
};
gpio0_14_12_pins: sdhc1-dir-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
};
dspi2_cs31_pins: sdhc1-dir-spi3-pins {
pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>;
};
esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>;
};
/* RCWSR13 */
gpio1_18_15_pins: iic8-iic7-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
i2c7_scl: i2c7-scl-pins {
i2c6_i2c7_pins: iic8-iic7-i2c-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
i2c7_scl_gpio: i2c7-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
/* RCWSR14 */
i2c0_pins: iic1-i2c-pins {
pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
i2c0_scl: i2c0-scl-pins {
pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
};
i2c0_scl_gpio: i2c0-scl-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
gpio0_3_2_pins: iic1-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
};
};

10
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
View File

@ -41,21 +41,29 @@ leds {
led_sfp_at: led-sfp-at {
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
default-state = "off";
linux,default-trigger = "netdev";
trigger-sources = <&dpmac3>;
};
led_sfp_ab: led-sfp-ab {
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
default-state = "off";
linux,default-trigger = "netdev";
trigger-sources = <&dpmac4>;
};
led_sfp_bt: led-sfp-bt {
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
default-state = "off";
linux,default-trigger = "netdev";
trigger-sources = <&dpmac5>;
};
led_sfp_bb: led-sfp-bb {
gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
default-state = "off";
linux,default-trigger = "netdev";
trigger-sources = <&dpmac6>;
};
};
@ -223,6 +231,8 @@ ethernet_phy8: ethernet-phy@15 {
};
&esdhc0 {
pinctrl-names = "default";
pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;

19
arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
View File

@ -5,6 +5,16 @@
// Copyright 2021 Rabeeh Khoury <rabeeh@solid-run.com>
// Copyright 2023 Josua Mayer <josua@solid-run.com>
/ {
model = "SolidRun LX2162A System on Module";
compatible = "solidrun,lx2162a-som", "fsl,lx2160a";
aliases {
crypto = &crypto;
rtc0 = &som_rtc;
};
};
&crypto {
status = "okay";
};
@ -30,6 +40,8 @@ &esdhc1 {
};
&fspi {
pinctrl-names = "default";
pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@ -75,8 +87,13 @@ variable_eeprom: eeprom@54 {
&i2c5 {
status = "okay";
rtc@6f {
som_rtc: rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};
&pinmux_i2crv {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_14_12_pins>;
};

4
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
View File

@ -22,10 +22,6 @@ &adc1 {
status = "okay";
};
&amix {
status = "okay";
};
&asrc0 {
status = "okay";
};

10
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
View File

@ -21,6 +21,7 @@ led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>;
};
@ -29,6 +30,7 @@ led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>;
};
@ -37,6 +39,7 @@ led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
};
@ -45,6 +48,7 @@ led-4 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
};
};
@ -62,10 +66,6 @@ &adc1 {
status = "okay";
};
&amix {
status = "okay";
};
&asrc0 {
status = "okay";
};
@ -89,8 +89,6 @@ &flexcan2 {
status = "okay";
};
/* TODO: GPU */
/* Apalis I2C1 */
&i2c2 {
status = "okay";

10
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
View File

@ -21,6 +21,7 @@ led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>;
};
@ -29,6 +30,7 @@ led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>;
};
@ -37,6 +39,7 @@ led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>;
};
@ -45,6 +48,7 @@ led-4 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
};
};
@ -94,10 +98,6 @@ &adc1 {
status = "okay";
};
&amix {
status = "okay";
};
&asrc0 {
status = "okay";
};
@ -123,8 +123,6 @@ &flexcan2 {
status = "okay";
};
/* TODO: GPU */
/* Apalis I2C1 */
&i2c2 {
status = "okay";

114
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -259,33 +259,37 @@ sound-wm8960-1 {
};
sound-wm8960-2 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio-2";
audio-cpu = <&sai2>;
audio-codec = <&wm8960_2>;
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
compatible = "audio-graph-card2";
label = "wm8960-audio-2";
links = <&sai2_port2>;
routing = "Headphones", "HP_L",
"Headphones", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
widgets = "Headphone", "Headphones",
"Speaker", "Ext Spk",
"Microphone", "Mic Jack";
};
sound-wm8960-3 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio-3";
audio-cpu = <&sai3>;
audio-codec = <&wm8960_3>;
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
compatible = "audio-graph-card2";
label = "wm8960-audio-3";
links = <&sai3_port2>;
routing = "Headphones", "HP_L",
"Headphones", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
widgets = "Headphone", "Headphones",
"Speaker", "Ext Spk",
"Microphone", "Mic Jack";
};
};
@ -481,6 +485,16 @@ wm8960_2: audio-codec@1a {
DCVDD-supply = <&reg_audio_1v8>;
SPKVDD1-supply = <&reg_audio_5v>;
SPKVDD2-supply = <&reg_audio_5v>;
port {
capture-only;
wm8960_2_ep: endpoint {
bitclock-master;
frame-master;
remote-endpoint = <&sai2_endpoint2>;
};
};
};
};
@ -510,6 +524,16 @@ wm8960_3: audio-codec@1a {
DCVDD-supply = <&reg_audio_1v8>;
SPKVDD1-supply = <&reg_audio_5v>;
SPKVDD2-supply = <&reg_audio_5v>;
port {
capture-only;
wm8960_3_ep: endpoint {
bitclock-master;
frame-master;
remote-endpoint = <&sai3_endpoint2>;
};
};
};
};
@ -700,6 +724,27 @@ &sai2 {
pinctrl-0 = <&pinctrl_sai2>;
fsl,sai-asynchronous;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
sai2_port1: port@1 {
reg = <1>;
endpoint { /* not used */ };
};
sai2_port2: port@2 {
reg = <2>;
capture-only;
sai2_endpoint2: endpoint {
dai-format = "i2s";
remote-endpoint = <&wm8960_2_ep>;
system-clock-direction-out;
};
};
};
};
&sai3 {
@ -712,6 +757,27 @@ &sai3 {
pinctrl-0 = <&pinctrl_sai3>;
fsl,sai-asynchronous;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
sai3_port1: port@1 {
reg = <1>;
endpoint { /* not used */ };
};
sai3_port2: port@2 {
reg = <2>;
capture-only;
sai3_endpoint2: endpoint {
dai-format = "i2s";
remote-endpoint = <&wm8960_3_ep>;
system-clock-direction-out;
};
};
};
};
&thermal_zones {

78
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -608,12 +608,34 @@ &spdif1 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
&usbphynop1 {
wakeup-source;
};
@ -691,7 +713,7 @@ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
pinctrl_ir: irgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
>;
};
@ -724,26 +746,26 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
>;
};
@ -761,19 +783,19 @@ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
@ -790,6 +812,15 @@ MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
@ -797,6 +828,15 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4

335
arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts Normal file
View File

@ -0,0 +1,335 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mm-sr-som.dtsi"
/ {
compatible = "solidrun,imx8mm-hummingboard-ripple",
"solidrun,imx8mm-sr-som", "fsl,imx8mm";
model = "SolidRun i.MX8MM HummingBoard Ripple";
aliases {
rtc0 = &carrier_rtc;
rtc1 = &snvs_rtc;
};
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "c";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7535_out>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
label = "D30";
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
label = "D31";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
label = "D32";
};
led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
label = "D33";
};
led-4 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
label = "D34";
};
};
v_1_2: regulator-1-2 {
compatible = "regulator-fixed";
regulator-name = "1v2";
regulator-max-microvolt = <1200000>;
regulator-min-microvolt = <1200000>;
};
vmmc: regulator-mmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
pinctrl-0 = <&vmmc_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
startup-delay-us = <250>;
gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
};
vbus1: regulator-vbus-1 {
compatible = "regulator-fixed";
regulator-name = "vbus1";
pinctrl-0 = <&vbus1_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vbus2: regulator-vbus-2 {
compatible = "regulator-fixed";
regulator-name = "vbus2";
pinctrl-0 = <&vbus2_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
rfkill-mpcie-wifi {
compatible = "rfkill-gpio";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
label = "mpcie WiFi";
pinctrl-0 = <&pcie_rfkill_pins>;
pinctrl-names = "default";
radio-type = "wlan";
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
reg-names = "main", "edid", "cec", "packet";
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
a2vdd-supply = <&v_1_8>;
avdd-supply = <&v_1_8>;
dvdd-supply = <&v_1_8>;
pd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_pins>;
pinctrl-names = "default";
pvdd-supply = <&v_1_8>;
v3p3-supply = <&v_3_3>;
adi,dsi-lanes = <4>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7535_from_dsim: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
carrier_eeprom: eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
carrier_rtc: rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
};
};
&iomuxc {
hdmi_pins: pinctrl-hdmi-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x0
>;
};
i2c3_pins: pinctrl-i2c3-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
led_pins: pinctrl-led-grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x0
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x0
MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x0
MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x0
>;
};
pcie_rfkill_pins: pinctrl-pcie-rfkill-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0
>;
};
usb_hub_pins: pinctrl-usb-hub-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x0
>;
};
usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
>;
};
usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
>;
};
usdhc2_pins: pinctrl-usdhc2-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
>;
};
vbus1_pins: pinctrl-vbus-1-grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x20
>;
};
vbus2_pins: pinctrl-vbus-2-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x20
>;
};
vmmc_pins: pinctrl-vmmc-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
};
&mipi_dsi_out {
remote-endpoint = <&adv7535_from_dsim>;
};
&usbotg1 {
dr_mode = "host";
vbus-supply = <&vbus2>;
status = "okay";
};
&usbotg2 {
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
pinctrl-0 = <&usb_hub_pins>;
pinctrl-names = "default";
vbus-supply = <&vbus1>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb4b4,6502", "usb4b4,6506";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
vdd2-supply = <&v_3_3>;
vdd-supply = <&v_1_2>;
};
/* this device is not visible because host supports 2.0 only */
hub_3_0: hub@2 {
compatible = "usb4b4,6500", "usb4b4,6504";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
vdd2-supply = <&v_3_3>;
vdd-supply = <&v_1_2>;
};
};
&usdhc2 {
bus-width = <4>;
pinctrl-0 = <&usdhc2_pins>;
pinctrl-1 = <&usdhc2_100mhz_pins>;
pinctrl-2 = <&usdhc2_200mhz_pins>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&vmmc>;
status = "okay";
};

33
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
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@ -6,6 +6,39 @@
#ifndef __DTS_IMX8MM_PINFUNC_H
#define __DTS_IMX8MM_PINFUNC_H
/* Drive Strength */
#define MX8MM_DSE_X1 0x0
#define MX8MM_DSE_X2 0x4
#define MX8MM_DSE_X4 0x2
#define MX8MM_DSE_X6 0x6
/* Slew Rate */
#define MX8MM_FSEL_FAST 0x10
#define MX8MM_FSEL_SLOW 0x0
/* Open Drain */
#define MX8MM_ODE_ENABLE 0x20
#define MX8MM_ODE_DISABLE 0x0
#define MX8MM_PULL_DOWN 0x0
#define MX8MM_PULL_UP 0x40
/* Hysteresis */
#define MX8MM_HYS_CMOS 0x0
#define MX8MM_HYS_SCHMITT 0x80
#define MX8MM_PULL_ENABLE 0x100
#define MX8MM_PULL_DISABLE 0x0
/* SION force input mode */
#define MX8MM_SION 0x40000000
/* long defaults */
#define MX8MM_USDHC_DATA_DEFAULT (MX8MM_FSEL_FAST | MX8MM_PULL_UP | \
MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
#define MX8MM_I2C_DEFAULT (MX8MM_DSE_X6 | MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | \
MX8MM_PULL_ENABLE | MX8MM_SION)
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>

393
arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi Normal file
View File

@ -0,0 +1,393 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
/ {
compatible = "solidrun,imx8mm-sr-som", "fsl,imx8mm";
model = "SolidRun i.MX8MM SoM";
chosen {
bootargs = "earlycon=ec_imx6q,0x30890000,115200";
stdout-path = &uart2;
};
v_1_8: regulator-1-8 {
compatible = "regulator-fixed";
regulator-name = "1v8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
v_3_3: regulator-3-3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
};
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
memory@40000000 {
reg = <0x0 0x40000000 0 0x80000000>;
device_type = "memory";
};
};
&fec1 {
phy = <&phy0>;
phy-mode = "rgmii-id";
pinctrl-0 = <&fec1_pins>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x4>;
phy-reset-duration = <10>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
vddio-supply = <&vddio>;
qca,smarteee-tw-us-1g = <24>;
vddio: vddio-regulator {
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
clocks = <&osc_32k>;
#clock-cells = <0>;
clock-output-names = "clk-32k-out";
pinctrl-0 = <&pmic_pins>;
pinctrl-names = "default";
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1300000>;
regulator-min-microvolt = <700000>;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1300000>;
regulator-min-microvolt = <700000>;
regulator-ramp-delay = <1250>;
rohm,dvs-idle-voltage = <900000>;
rohm,dvs-run-voltage = <1000000>;
};
buck3_reg: BUCK3 {
// BUCK5 in datasheet
regulator-name = "buck3";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1350000>;
regulator-min-microvolt = <700000>;
};
buck4_reg: BUCK4 {
// BUCK6 in datasheet
regulator-name = "buck4";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
};
buck5_reg: BUCK5 {
// BUCK7 in datasheet
regulator-name = "buck5";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1995000>;
regulator-min-microvolt = <1605000>;
};
buck6_reg: BUCK6 {
// BUCK8 in datasheet
regulator-name = "buck6";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1400000>;
regulator-min-microvolt = <800000>;
};
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
};
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <800000>;
};
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <900000>;
};
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <900000>;
};
};
};
som_eeprom: eeprom@50 {
compatible = "st,24c01", "atmel,24c01";
reg = <0x50>;
pagesize = <16>;
};
};
&iomuxc {
fec1_pins: pinctrl-fec1-grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
i2c1_pins: pinctrl-i2c1-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pcie_pins: pinctrl-pcie-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0
>;
};
pmic_pins: pinctrl-pmic-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
>;
};
uart1_pins: pinctrl-uart1-grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
/* BT_REG_ON */
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
/* BT_WAKE_DEV */
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0
/* BT_WAKE_HOST */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100
>;
};
uart2_pins: pinctrl-uart2-grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
usdhc1_pins: pinctrl-usdhc1-grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
/* wifi refclk */
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0
/* WL_REG_ON */
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0
/* WL_WAKE_HOST */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100
>;
};
usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
usdhc3_pins: pinctrl-usdhc3-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
wdog1_pins: pinctrl-wdog1-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
>;
};
};
/* assembly-option for AI accelerator on SoM, otherwise routed to carrier */
&pcie0 {
pinctrl-0 = <&pcie_pins>;
pinctrl-names = "default";
reset-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
status = "okay";
};
&pcie_phy {
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
status = "okay";
};
&uart1 {
/* select 80MHz parent clock to support maximum baudrate 4Mbps */
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
};
};
&uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
&usdhc1 {
bus-width = <4>;
mmc-pwrseq = <&usdhc1_pwrseq>;
pinctrl-0 = <&usdhc1_pins>;
pinctrl-names = "default";
vmmc-supply = <&v_3_3>;
vqmmc-supply = <&v_1_8>;
status = "okay";
};
&usdhc3 {
bus-width = <8>;
non-removable;
pinctrl-0 = <&usdhc3_pins>;
pinctrl-1 = <&usdhc3_100mhz_pins>;
pinctrl-2 = <&usdhc3_200mhz_pins>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&v_3_3>;
vqmmc-supply = <&v_1_8>;
status = "okay";
};
&wdog1 {
pinctrl-0 = <&wdog1_pins>;
pinctrl-names = "default";
status = "okay";
};

86
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso Normal file
View File

@ -0,0 +1,86 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/gpio/gpio.h>
&backlight_lvds {
status = "okay";
};
&dsi_lvds_bridge {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
reg = <2>;
lvds_bridge_out0: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
port@3 {
reg = <3>;
lvds_bridge_out1: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&expander0 {
dsi-mux-oe-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_LOW>;
output-high;
line-name = "DSI_MUX_OE#";
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
};
&panel {
compatible = "auo,g133han01";
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds_bridge_out0>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
panel_in_lvds1: endpoint {
remote-endpoint = <&lvds_bridge_out1>;
};
};
};
};

9
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* Copyright (c) 2022-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
@ -10,10 +10,6 @@
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
};
&backlight_lvds {
status = "okay";
};
@ -36,7 +32,8 @@ &lcdif {
};
&mipi_dsi {
status = "okay";
samsung,burst-clock-frequency = <600000000>;
status = "okay";
};
&panel {

1
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
View File

@ -76,7 +76,6 @@ expander2: gpio@27 {
};
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
};

799
arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts Normal file
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@ -0,0 +1,799 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Maud Spierings <maudspierings@gocontroll.com>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mm-tx8m-1610.dtsi"
/ {
chassis-type = "embedded";
compatible = "gocontroll,moduline-iv-306-d", "karo,tx8m-1610", "fsl,imx8mm";
hardware = "Moduline IV V3.06-D";
model = "GOcontroll Moduline IV";
aliases {
spi0 = &ecspi2; /* spidev number compatibility */
spi1 = &ecspi3; /* spidev number compatibility */
spi2 = &ecspi1; /* spidev number compatibility */
};
chosen {
stdout-path = "serial2:115200n8";
};
mcp_clock: mcp-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
reg_3v3_m2: regulator-3v3-m2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_reg_m2>;
pinctrl-names = "default";
power-supply = <&reg_6v4>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3v3-m.2";
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
power-supply = <&reg_6v4>;
regulator-always-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "5v0";
};
reg_6v4: regulator-6v4 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <6400000>;
regulator-min-microvolt = <6400000>;
regulator-name = "6v4";
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_can1_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can1-stby";
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
gpio = <&gpio3 17 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_can2_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can2-stby";
};
reg_can3_stby: regulator-can3-stby {
compatible = "regulator-fixed";
gpio = <&gpio1 11 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_can3_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can3-stby";
};
reg_can4_stby: regulator-can4-stby {
compatible = "regulator-fixed";
gpio = <&gpio3 8 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_can4_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can4-stby";
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-0 = <&pinctrl_wl_reg>;
pinctrl-names = "default";
post-power-on-delay-ms = <100>;
power-off-delay-us = <500000>;
reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
};
};
/* SPI 2 */
&ecspi1 {
cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>,
<&gpio1 0 GPIO_ACTIVE_LOW>,
<&gpio5 2 GPIO_ACTIVE_LOW>,
<&gpio4 27 GPIO_ACTIVE_LOW>,
<&gpio3 1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-names = "default";
status = "okay";
connector@0 {
compatible = "gocontroll,moduline-module-slot";
reg = <0>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
slot-number = <3>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
connector@1 {
compatible = "gocontroll,moduline-module-slot";
reg = <1>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio5>;
interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
slot-number = <4>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
connector@2 {
compatible = "gocontroll,moduline-module-slot";
reg = <2>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio5>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
slot-number = <5>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
connector@3 {
compatible = "gocontroll,moduline-module-slot";
reg = <3>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
slot-number = <6>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
adc@4 {
compatible = "microchip,mcp3004";
reg = <4>;
spi-max-frequency = <2300000>;
vref-supply = <&reg_vdd_3v3>;
};
};
&ecspi2 {
cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>,
<&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio3 2 GPIO_ACTIVE_LOW>,
<&gpio5 25 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi2>;
pinctrl-names = "default";
status = "okay";
connector@0 {
compatible = "gocontroll,moduline-module-slot";
reg = <0>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
slot-number = <7>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
connector@1 {
compatible = "gocontroll,moduline-module-slot";
reg = <1>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio3>;
interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
slot-number = <8>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
can@2 {
compatible = "microchip,mcp25625";
reg = <2>;
clocks = <&mcp_clock>;
interrupt-parent = <&gpio3>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_can1>;
pinctrl-names = "default";
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_can1_stby>;
};
can@3 {
compatible = "microchip,mcp25625";
reg = <3>;
clocks = <&mcp_clock>;
interrupt-parent = <&gpio3>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_can2>;
pinctrl-names = "default";
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_can2_stby>;
};
};
&ecspi3 {
cs-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>,
<&gpio5 5 GPIO_ACTIVE_LOW>,
<&gpio5 4 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi3>;
pinctrl-names = "default";
status = "okay";
connector@0 {
compatible = "gocontroll,moduline-module-slot";
reg = <0>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio1>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
slot-number = <1>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
connector@1 {
compatible = "gocontroll,moduline-module-slot";
reg = <1>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio5>;
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
slot-number = <2>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
can@2 {
compatible = "microchip,mcp25625";
reg = <2>;
clocks = <&mcp_clock>;
interrupt-parent = <&gpio3>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_can3>;
pinctrl-names = "default";
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_can3_stby>;
};
can@3 {
compatible = "microchip,mcp25625";
reg = <3>;
clocks = <&mcp_clock>;
interrupt-parent = <&gpio3>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_can4>;
pinctrl-names = "default";
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_can4_stby>;
};
};
&gpu_2d {
status = "disabled";
};
&gpu_3d {
status = "disabled";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
lp5012@14 {
compatible = "ti,lp5012";
reg = <0x14>;
vled-supply = <&reg_6v4>;
#address-cells = <1>;
#size-cells = <0>;
multi-led@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
color = <LED_COLOR_ID_RGB>;
label = "case-led1";
led@0 {
color = <LED_COLOR_ID_RED>;
reg = <0>;
};
led@1 {
color = <LED_COLOR_ID_GREEN>;
reg = <1>;
};
led@2 {
color = <LED_COLOR_ID_BLUE>;
reg = <2>;
};
};
multi-led@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
color = <LED_COLOR_ID_RGB>;
label = "case-led2";
led@0 {
color = <LED_COLOR_ID_RED>;
reg = <0>;
};
led@1 {
color = <LED_COLOR_ID_GREEN>;
reg = <1>;
};
led@2 {
color = <LED_COLOR_ID_BLUE>;
reg = <2>;
};
};
multi-led@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
color = <LED_COLOR_ID_RGB>;
label = "case-led3";
led@0 {
color = <LED_COLOR_ID_RED>;
reg = <0>;
};
led@1 {
color = <LED_COLOR_ID_GREEN>;
reg = <1>;
};
led@2 {
color = <LED_COLOR_ID_BLUE>;
reg = <2>;
};
};
multi-led@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
color = <LED_COLOR_ID_RGB>;
label = "case-led4";
led@0 {
color = <LED_COLOR_ID_RED>;
reg = <0>;
};
led@1 {
color = <LED_COLOR_ID_GREEN>;
reg = <1>;
};
led@2 {
color = <LED_COLOR_ID_BLUE>;
reg = <2>;
};
};
};
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1
MX8MM_DSE_X1
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13
MX8MM_DSE_X1
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_can1_reg: can1reggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_can2_reg: can2reggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_can3: can3grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_can3_reg: can3reggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_can4: can4grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_can4_reg: can4reggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
MX8MM_DSE_X4
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
(MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
MX8MM_DSE_X4
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9
MX8MM_DSE_X1
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0
MX8MM_DSE_X1
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2
MX8MM_DSE_X1
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27
MX8MM_DSE_X1
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1
MX8MM_DSE_X1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
MX8MM_DSE_X4
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
(MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
MX8MM_DSE_X4
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23
MX8MM_DSE_X1
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9
MX8MM_DSE_X1
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2
MX8MM_DSE_X1
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25
MX8MM_DSE_X1
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI
MX8MM_DSE_X4
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO
(MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK
MX8MM_DSE_X4
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4
MX8MM_DSE_X1
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10
MX8MM_DSE_X1
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
MX8MM_DSE_X1
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4
MX8MM_DSE_X1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA
MX8MM_I2C_DEFAULT
>;
};
pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17
MX8MM_I2C_DEFAULT
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA
MX8MM_I2C_DEFAULT
>;
};
pinctrl_i2c3_gpio: i2c3-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19
MX8MM_I2C_DEFAULT
>;
};
pinctrl_reg_m2: reg-m2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8
MX8MM_DSE_X1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_usdhc2: pinctrlusdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
>;
};
pinctrl_wl_int: wlintgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20
(MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
>;
};
pinctrl_wl_reg: wlreggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3
MX8MM_DSE_X1
>;
};
};
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wakeup";
interrupt-parent = <&gpio3>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
max-speed = <921600>;
pinctrl-0 = <&pinctrl_bt>;
pinctrl-names = "default";
shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
vbat-supply = <&reg_3v3_m2>;
vddio-supply = <&reg_3v3_m2>;
};
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-0 = <&pinctrl_uart3>;
pinctrl-names = "default";
status = "okay";
};
&uart4 {
pinctrl-0 = <&pinctrl_uart4>;
pinctrl-names = "default";
status = "okay";
};
&usbotg1 {
disable-over-current;
dr_mode = "peripheral";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
vbus-supply = <&reg_5v0>;
status = "okay";
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
cap-power-off-card;
keep-power-in-suspend;
max-frequency = <50000000>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-names = "default";
sd-uhs-sdr25;
vmmc-supply = <&reg_3v3_m2>;
status = "okay";
wifi@1 {
compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
reg = <1>;
pinctrl-0 = <&pinctrl_wl_int>;
pinctrl-names = "default";
interrupt-names = "host-wake";
interrupt-parent = <&gpio3>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
brcm,board-type = "GOcontroll,moduline";
};
};
&vpu_blk_ctrl {
status = "disabled";
};
&vpu_g1 {
status = "disabled";
};
&vpu_g2 {
status = "disabled";
};
&wdog1 {
status = "okay";
};

687
arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts Normal file
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@ -0,0 +1,687 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Maud Spierings <maudspierings@gocontroll.com>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mm-tx8m-1610.dtsi"
/ {
chassis-type = "embedded";
compatible = "gocontroll,moduline-mini-111", "karo,tx8m-1610", "fsl,imx8mm";
hardware = "Moduline Mini V1.11";
model = "GOcontroll Moduline Mini";
aliases {
spi0 = &ecspi2; /* spidev number compatibility */
spi1 = &ecspi3; /* spidev number compatibility */
spi2 = &ecspi1; /* spidev number compatibility */
};
chosen {
stdout-path = "serial2:115200n8";
};
mcp_clock: mcp-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
reg_3v3_comm: regulator-3v3-communication {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_reg_comm>;
pinctrl-names = "default";
power-supply = <&reg_6v4>;
/* also powers the cellular modem which can't vote on the regulator */
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3v3_comm";
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
power-supply = <&reg_6v4>;
regulator-always-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "5v0";
};
reg_6v4: regulator-6v4 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <6400000>;
regulator-min-microvolt = <6400000>;
regulator-name = "6v4";
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
gpio = <&gpio2 12 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_can1_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can1-stby";
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_can2_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can2-stby";
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-0 = <&pinctrl_wl_reg>;
pinctrl-names = "default";
post-power-on-delay-ms = <100>;
power-off-delay-us = <500000>;
reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
};
};
&ecspi1 {
cs-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>,
<&gpio3 23 GPIO_ACTIVE_LOW>,
<&gpio3 1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi1>;
pinctrl-names = "default";
status = "okay";
connector@0 {
compatible = "gocontroll,moduline-module-slot";
reg = <0>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
slot-number = <3>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
connector@1 {
compatible = "gocontroll,moduline-module-slot";
reg = <1>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
slot-number = <4>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
adc@2 {
compatible = "microchip,mcp3004";
reg = <2>;
spi-max-frequency = <2300000>;
vref-supply = <&reg_vdd_3v3>;
};
};
&ecspi2 {
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
<&gpio3 9 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi2>;
pinctrl-names = "default";
status = "okay";
can@0 {
compatible = "microchip,mcp25625";
reg = <0>;
clocks = <&mcp_clock>;
interrupt-parent = <&gpio3>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_can1>;
pinctrl-names = "default";
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_can1_stby>;
};
can@1 {
compatible = "microchip,mcp25625";
reg = <1>;
clocks = <&mcp_clock>;
interrupt-parent = <&gpio3>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_can2>;
pinctrl-names = "default";
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_can2_stby>;
};
};
&ecspi3 {
cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>,
<&gpio1 2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_ecspi3>;
pinctrl-names = "default";
status = "okay";
connector@0 {
compatible = "gocontroll,moduline-module-slot";
reg = <0>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
slot-number = <1>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
connector@1 {
compatible = "gocontroll,moduline-module-slot";
reg = <1>;
i2c-bus = <&i2c2>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
slot-number = <2>;
spi-max-frequency = <54000000>;
sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
vddhpp-supply = <&reg_6v4>;
vddp-supply = <&reg_5v0>;
vdd-supply = <&reg_vdd_3v3>;
};
};
&gpu_2d {
status = "disabled";
};
&gpu_3d {
status = "disabled";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
lp5012@14 {
compatible = "ti,lp5012";
reg = <0x14>;
vled-supply = <&reg_6v4>;
#address-cells = <1>;
#size-cells = <0>;
multi-led@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
color = <LED_COLOR_ID_RGB>;
label = "case-led1";
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
multi-led@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
color = <LED_COLOR_ID_RGB>;
label = "case-led2";
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
multi-led@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
color = <LED_COLOR_ID_RGB>;
label = "case-led3";
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
multi-led@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
color = <LED_COLOR_ID_RGB>;
label = "case-led4";
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
};
accelerometer@18 {
compatible = "st,lis2dw12";
reg = <0x18>;
interrupt-parent = <&gpio5>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>, <5 IRQ_TYPE_EDGE_RISING>;
pinctrl-0 = <&pinctrl_lis_int>;
pinctrl-names = "default";
vddio-supply = <&reg_vdd_3v3>;
vdd-supply = <&reg_vdd_3v3>;
};
humidity-sensor@5f {
compatible = "st,hts221";
reg = <0x5f>;
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_EDGE_RISING>;
pinctrl-0 = <&pinctrl_hts_int>;
pinctrl-names = "default";
vdd-supply = <&reg_vdd_3v3>;
};
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1
MX8MM_DSE_X1
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13
MX8MM_DSE_X1
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_can1_reg: can1reggrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_can2_reg: can2reggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
MX8MM_DSE_X4
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
(MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
MX8MM_DSE_X4
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27
MX8MM_DSE_X1
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23
MX8MM_DSE_X1
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1
MX8MM_DSE_X1
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
MX8MM_DSE_X4
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
(MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
MX8MM_DSE_X4
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24
MX8MM_DSE_X1
MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9
MX8MM_DSE_X1
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI
MX8MM_DSE_X4
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO
(MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK
MX8MM_DSE_X4
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9
MX8MM_DSE_X1
MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2
MX8MM_DSE_X1
>;
};
pinctrl_hts_int: htsintgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10
(MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA
MX8MM_I2C_DEFAULT
>;
};
pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17
MX8MM_I2C_DEFAULT
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA
MX8MM_I2C_DEFAULT
>;
};
pinctrl_i2c3_gpio: i2c3-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19
MX8MM_I2C_DEFAULT
>;
};
pinctrl_lis_int: lisintgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3
(MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
(MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_reg_comm: reg_commgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11
MX8MM_DSE_X1
>;
};
pinctrl_sysfs_gpios: sysfsgpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7
MX8MM_DSE_X1
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21
MX8MM_DSE_X1
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28
MX8MM_DSE_X1
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21
MX8MM_DSE_X1
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20
MX8MM_DSE_X1
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0
MX8MM_DSE_X1
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4
MX8MM_DSE_X1
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6
MX8MM_DSE_X1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_usdhc2: pinctrlusdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
>;
};
pinctrl_wl_int: wlintgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20
(MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
>;
};
pinctrl_wl_reg: wlreggrp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28
MX8MM_DSE_X1
>;
};
};
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wakeup";
interrupt-parent = <&gpio3>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
max-speed = <921600>;
pinctrl-0 = <&pinctrl_bt>;
pinctrl-names = "default";
shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
vbat-supply = <&reg_3v3_comm>;
vddio-supply = <&reg_3v3_comm>;
};
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-0 = <&pinctrl_uart3>;
pinctrl-names = "default";
status = "okay";
};
&usbotg1 {
disable-over-current;
dr_mode = "peripheral";
status = "okay";
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
vbus-supply = <&reg_5v0>;
status = "okay";
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
cap-power-off-card;
keep-power-in-suspend;
max-frequency = <50000000>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-names = "default";
sd-uhs-sdr25;
vmmc-supply = <&reg_3v3_comm>;
status = "okay";
wifi@1 {
compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
reg = <1>;
pinctrl-0 = <&pinctrl_wl_int>;
pinctrl-names = "default";
interrupt-names = "host-wake";
interrupt-parent = <&gpio3>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
brcm,board-type = "GOcontroll,moduline";
};
};
&vpu_blk_ctrl {
status = "disabled";
};
&vpu_g1 {
status = "disabled";
};
&vpu_g2 {
status = "disabled";
};
&wdog1 {
status = "okay";
};

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arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi Normal file
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@ -0,0 +1,444 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 Lothar Waßmann <LW@KARO-electronics.de>
* 2025 Maud Spierings <maudspierings@gocontroll.com>
*/
#include "imx8mm.dtsi"
/ {
model = "Ka-Ro Electronics TX8M-1610";
compatible = "karo,tx8m-1610", "fsl,imx8mm";
reg_3v3_etn: regulator-3v3-etn {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_reg_3v3_etn>;
pinctrl-names = "default";
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "3v3-etn";
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
};
};
};
&fec1 {
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>,
<&clk IMX8MM_CLK_ENET_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_SYS_PLL2_100M>,
<&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>;
clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
phy-reset-duration = <25>;
phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <1>;
phy-supply = <&reg_3v3_etn>;
pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_ethphy_rst>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
clocks = <&clk IMX8MM_CLK_ENET_REF>;
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&pinctrl_ethphy_int>;
pinctrl-names = "default";
smsc,disable-energy-detect;
};
};
};
&gpio1 {
gpio-line-names = "SODIMM_152", "SODIMM_42", "SODIMM_153", "PMIC_IRQ_B",
"SODIMM_154", "SODIMM_155", "SODIMM_156", "SODIMM_157",
"SODIMM_158", "SODIMM_159", "SODIMM_161", "SODIMM_162",
"SODIMM_34", "SODIMM_36", "SODIMM_27", "SODIMM_28",
"", "", "", "",
"", "", "", "ENET_POWER",
"", "", "", "",
"ENET_nINT", "ENET_nRST", "", "";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"SODIMM_51", "SODIMM_57", "SODIMM_56", "SODIMM_52",
"SODIMM_53", "SODIMM_54", "SODIMM_55", "SODIMM_15",
"SODIMM_45", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio3 {
gpio-line-names = "SODIMM_103", "SODIMM_104", "SODIMM_105", "SODIMM_106",
"SODIMM_107", "SODIMM_112", "SODIMM_108", "SODIMM_109",
"SODIMM_95", "SODIMM_110", "SODIMM_96", "SODIMM_97",
"SODIMM_98", "SODIMM_99", "SODIMM_113", "SODIMM_114",
"SODIMM_115", "SODIMM_101", "SODIMM_100", "SODIMM_77",
"SODIMM_72", "SODIMM_73", "SODIMM_74", "SODIMM_75",
"SODIMM_76", "SODIMM_43", "", "",
"", "", "", "";
};
&gpio4 {
gpio-line-names = "SODIMM_178", "SODIMM_180", "SODIMM_184", "SODIMM_185",
"SODIMM_186", "SODIMM_187", "SODIMM_188", "SODIMM_189",
"SODIMM_190", "SODIMM_191", "SODIMM_179", "SODIMM_181",
"SODIMM_192", "SODIMM_193", "SODIMM_194", "SODIMM_195",
"SODIMM_196", "SODIMM_197", "SODIMM_198", "SODIMM_199",
"SODIMM_182", "SODIMM_79", "SODIMM_78", "SODIMM_84",
"SODIMM_87", "SODIMM_86", "SODIMM_85", "SODIMM_83",
"SODIMM_81", "SODIMM_80", "SODIMM_90", "SODIMM_93";
};
&gpio5 {
gpio-line-names = "SODIMM_92", "SODIMM_91", "SODIMM_89", "SODIMM_144",
"SODIMM_143", "SODIMM_146", "SODIMM_68", "SODIMM_67",
"SODIMM_70", "SODIMM_69", "SODIMM_48", "SODIMM_46",
"SODIMM_47", "SODIMM_44", "PMIC_SCL", "PMIC_SDA",
"SODIMM_41", "SODIMM_40", "SODIMM_148", "SODIMM_149",
"SODIMM_150", "SODIMM_151", "SODIMM_60", "SODIMM_59",
"SODIMM_64", "SODIMM_63", "SODIMM_62", "SODIMM_61",
"SODIMM_66", "SODIMM_65", "", "";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
pinctrl-names = "default", "gpio";
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-names = "default";
rohm,reset-snvs-powered;
regulators {
BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <780000>;
regulator-name = "buck1";
regulator-ramp-delay = <1250>;
};
reg_vdd_arm: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <805000>;
regulator-name = "buck2";
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <950000>;
rohm,dvs-idle-voltage = <810000>;
};
BUCK3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <805000>;
regulator-name = "buck3";
};
reg_vdd_3v3: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "buck4";
};
reg_vdd_1v8: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1700000>;
regulator-name = "buck5";
};
BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <(1350000 + 100000)>;
regulator-min-microvolt = <(1350000 - 67000)>;
regulator-name = "buck6";
rohm,fb-pull-up-microvolt = <0>;
rohm,feedback-pull-up-r1-ohms = <2200>;
rohm,feedback-pull-up-r2-ohms = <499>;
};
LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1980000>;
regulator-min-microvolt = <1620000>;
regulator-name = "ldo1";
};
LDO2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <760000>;
regulator-name = "ldo2";
};
LDO3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1890000>;
regulator-min-microvolt = <1710000>;
regulator-name = "ldo3";
};
LDO4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <855000>;
regulator-name = "ldo4";
};
LDO5 {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "ldo5";
};
LDO6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1260000>;
regulator-min-microvolt = <1140000>;
regulator-name = "ldo6";
};
};
};
};
&iomuxc {
pinctrl_ethphy_int: etnphy-intgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28
(MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT)
>;
};
pinctrl_ethphy_rst: etnphy-rstgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29
(MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC
(MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO
(MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK
(MX8MM_FSEL_FAST | MX8MM_SION)
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST)
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST)
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
(MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
(MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT)
MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER
MX8MM_FSEL_FAST
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
MX8MM_FSEL_FAST
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST)
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA
MX8MM_I2C_DEFAULT
>;
};
pinctrl_i2c1_gpio: i2c1-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14
MX8MM_I2C_DEFAULT
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15
MX8MM_I2C_DEFAULT
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3
(MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
>;
};
pinctrl_reg_3v3_etn: reg-3v3-etngrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23
(MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
(MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
MX8MM_USDHC_DATA_DEFAULT
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
(MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
(MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
(MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
(MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT)
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE)
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
(MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE)
>;
};
};
&usdhc1 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
status = "okay";
};

19
arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 Variscite Ltd.
*/
#include "imx8mm-var-som-symphony.dts"
#include "imx8mm-var-som-wifi-brcm-legacy.dtsi"
&bluetooth_iw61x {
status = "disabled";
};
&iw61x_pwrseq {
status = "disabled";
};
&usdhc1 {
/delete-property/ mmc-pwrseq;
};

214
arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
View File

@ -5,12 +5,25 @@
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-var-som.dtsi"
#include "imx8mm-var-som-wifi-bt-iw61x.dtsi"
/ {
model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";
compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";
chosen {
stdout-path = &uart4;
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -18,7 +31,8 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
@ -26,6 +40,7 @@ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
pinctrl-1 = <&pinctrl_reg_usb_otg2_vbus_sleep>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -67,7 +82,24 @@ led {
};
&ethphy {
reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
&i2c2 {
@ -110,17 +142,38 @@ enet-sel-hog {
};
};
extcon_usbotg1: typec@3d {
/* USB Type-C Controller */
ptn5150: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
&i2c3 {
pca6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
label = "tpm";
reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>;
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5406";
@ -142,6 +195,39 @@ rtc@68 {
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&pcie_phy {
clocks = <&pcie0_refclk>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
fsl,clkreq-unsupported;
status = "okay";
};
&pcie0 {
reset-gpio = <&pca6408 1 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
<&clk IMX8MM_CLK_PCIE1_AUX>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
/* Header */
&uart1 {
pinctrl-names = "default";
@ -156,28 +242,49 @@ &uart3 {
status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
disable-over-current;
extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg2_vbus>;
srp-disable;
hnp-disable;
adp-disable;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
disable-over-current;
/delete-property/ usb-role-switch;
/*
* FIXME: having USB2 enabled hangs the boot just after:
* [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller
* [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
* [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
* [ 1.977203] hub 1-0:1.0: USB hub found
* [ 1.980987] hub 1-0:1.0: 1 port detected
*/
status = "disabled";
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&pinctrl_fec1 {
@ -214,6 +321,20 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
@ -232,9 +353,15 @@ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16
>;
};
pinctrl_reg_usb_otg2_vbus_sleep: regusbotg2vbus-sleepgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x120
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
>;
};
@ -251,4 +378,53 @@ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1
>;
};
};

12
arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 Variscite Ltd.
*/
/* WIFI */
&usdhc1 {
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};

45
arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 Variscite Ltd.
*/
/ {
iw61x_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_bt>;
bluetooth_iw61x: bluetooth {
compatible = "nxp,88w8987-bt";
};
};
/* WIFI */
&usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
mmc-pwrseq = <&iw61x_pwrseq>;
};
&iomuxc {
pinctrl_bt: bluetoothgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1
>;
};
pinctrl_wifi: wifigrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1
>;
};
};

372
arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
View File

@ -9,15 +9,26 @@
/ {
model = "Variscite VAR-SOM-MX8MM module";
chosen {
stdout-path = &uart4;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
clk40m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
clock-output-names = "can_osc";
};
reg_audio_supply: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "wm8904-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -28,6 +39,41 @@ reg_eth_phy: regulator-eth-phy {
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_phy_vddio: regulator-phy-vddio {
compatible = "regulator-fixed";
regulator-name = "vddio-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai5>;
};
};
};
&A53_0 {
@ -100,15 +146,33 @@ touchscreen@0 {
ti,keep-vref-on;
wakeup-source;
};
/* CAN controller */
can0: can@1 {
compatible = "microchip,mcp251xfd";
reg = <1>;
clocks = <&clk40m>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
interrupt-parent = <&gpio1>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <20000000>;
microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-supply = <&reg_eth_phy>;
fsl,magic-packet;
status = "okay";
mdio {
@ -120,7 +184,8 @@ ethphy: ethernet-phy@4 {
reg = <4>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
reset-deassert-us = <100000>;
vddio-supply = <&reg_phy_vddio>;
};
};
};
@ -248,18 +313,57 @@ ldo6_reg: LDO6 {
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* TODO: configure audio, as of now just put a placeholder */
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
status = "disabled";
#sound-dai-cells = <0>;
clocks = <&clk IMX8MM_CLK_SAI5_ROOT>;
clock-names = "mclk";
AVDD-supply = <&ldo5_reg>;
CPVDD-supply = <&ldo5_reg>;
DBVDD-supply = <&reg_audio_supply>;
DCVDD-supply = <&ldo5_reg>;
MICVDD-supply = <&ldo5_reg>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <1536000>;
#sound-dai-cells = <0>;
dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>;
dma-names = "rx", "tx";
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -274,26 +378,6 @@ &uart2 {
status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usbotg2 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
/* WIFI */
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
@ -305,11 +389,6 @@ &usdhc1 {
non-removable;
keep-power-in-suspend;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD */
@ -347,6 +426,13 @@ &wdog1 {
};
&iomuxc {
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x16
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
@ -377,180 +463,212 @@ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_fec1_sleep: fec1sleepgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
>;
};
pinctrl_reg_eth_phy: regethphygrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
};

19
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -220,16 +220,15 @@ psci {
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};
@ -400,7 +399,7 @@ micfil: audio-controller@30080000 {
};
spdif1: spdif@30090000 {
compatible = "fsl,imx35-spdif";
compatible = "fsl,imx8mm-spdif";
reg = <0x30090000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
@ -1149,8 +1148,10 @@ mipi_dsi: dsi@32e10000 {
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_CLK_24M>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
status = "disabled";

4
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@ -415,6 +415,10 @@ &uart1 { /* BT */
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&uart2 { /* console */

851
arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts Normal file
View File

@ -0,0 +1,851 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for SolidSense N8 Compact
*
* Copyright 2024 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mn.dtsi"
/ {
compatible = "solidrun,solidsense-n8-compact", "fsl,imx8mn";
model = "SolidRun SolidSense N8 Compact";
/* LED labels based on enclosure, schematic names differ. */
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
/* D20 */
led1 {
default-state = "off";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
label = "led1";
};
/* D18 */
led2 {
default-state = "off";
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
label = "led2";
};
/* D19 */
led3 {
default-state = "off";
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
label = "led3";
};
};
aliases {
gpio5 = &expander;
rtc0 = &rtc;
rtc1 = &snvs_rtc;
usb0 = &usbotg1;
watchdog0 = &wdog1;
watchdog1 = &rtc;
};
chosen {
stdout-path = &uart2;
};
reg_modem_vbat: regulator-modem-vbat {
compatible = "regulator-fixed";
regulator-name = "modem-vbat";
pinctrl-0 = <&regulator_modem_vbat_pins>;
pinctrl-names = "default";
regulator-always-on;
regulator-max-microvolt = <3800000>;
regulator-min-microvolt = <3800000>;
gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* power to lte modems behind hub ports 2/3 */
reg_modem_vbus: regulator-modem-vbus {
compatible = "regulator-fixed";
regulator-name = "modem-vbus";
pinctrl-0 = <&regulator_modem_vbus_pins>;
pinctrl-names = "default";
regulator-always-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* power to usb hub, and type-a behind hub port 1 */
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
pinctrl-0 = <&regulator_usb1_vbus_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "usdhc2-vmmc";
off-on-delay-us = <250>;
pinctrl-0 = <&regulator_usdhc2_vmmc_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
vin-supply = <&reg_vdd_3v3>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vdd_1v8: regulator-vdd-1v8 {
compatible = "regulator-fixed";
regulator-name = "vdd-1v8";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
reg_vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd-3v3";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
};
rfkill {
compatible = "rfkill-gpio";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
label = "rfkill-wwan";
pinctrl-0 = <&modem_pins>;
pinctrl-names = "default";
radio-type = "wwan";
};
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
memory@40000000 {
reg = <0x0 0x40000000 0 0x80000000>;
device_type = "memory";
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-266500000 {
opp-hz = /bits/ 64 <266500000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
};
};
};
&ecspi2 {
/* native chip-select causes reading 0xffffffff */
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
num-cs = <1>;
pinctrl-0 = <&ecspi2_pins>;
pinctrl-names = "default";
status = "okay";
can@0 {
compatible = "microchip,mcp2518fd";
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk IMX8MN_CLK_CLKOUT1>;
/* generate 8MHz clock from soc-internal 24mhz reference */
assigned-clock-parents = <&clk IMX8MN_CLK_24M>, <0>;
assigned-clock-rates = <0>, <8000000>;
assigned-clocks = <&clk IMX8MN_CLK_CLKOUT1_SEL>,
<&clk IMX8MN_CLK_CLKOUT1_DIV>;
pinctrl-0 = <&can_pins>;
pinctrl-names = "default";
spi-max-frequency = <20000000>;
};
};
&fec1 {
phy-handle = <&phy4>;
phy-mode = "rgmii-id";
pinctrl-0 = <&fec1_pins>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/*
* Depending on board revision two different phys are used:
* - v1.1: atheros phy at address 4
* - v1.2+: analog devices phy at address 0
* Configure first version by default.
* On v1.2 and later, U-Boot will enable the correct phy
* based on runtime detection and patch dtb accordingly.
*/
/* ADIN1300 */
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
reset-assert-us = <10>;
reset-deassert-us = <5000>;
reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
adi,led-polarity = <GPIO_ACTIVE_LOW>;
adi,link-st-polarity = <GPIO_ACTIVE_LOW>;
status = "disabled";
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
active-low;
color = <LED_COLOR_ID_YELLOW>;
default-state = "keep";
function = LED_FUNCTION_LAN;
};
};
};
/* AR8035 */
phy4: ethernet-phy@4 {
reg = <4>;
reset-assert-us = <10000>;
reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
};
&gpio5 {
usb-hub-reset-hog {
line-name = "usb-hub-reset";
gpios = <3 GPIO_ACTIVE_LOW>;
gpio-hog;
/* deasserted */
output-low;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
clocks = <&osc_32k>;
#clock-cells = <0>;
clock-output-names = "clk-32k-out";
pinctrl-0 = <&pmic_pins>;
pinctrl-names = "default";
rohm,reset-snvs-powered;
regulators {
BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1300000>;
regulator-min-microvolt = <700000>;
regulator-ramp-delay = <1250>;
// supplies soc vdd, soc mipi vdd @ 0.9V
regulator-name = "buck1";
rohm,dvs-run-voltage = <850000>;
rohm,dvs-suspend-voltage = <750000>;
};
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1300000>;
regulator-min-microvolt = <700000>;
regulator-ramp-delay = <1250>;
rohm,dvs-idle-voltage = <900000>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-suspend-voltage = <0>;
};
BUCK3 {
// BUCK5 in datasheet
// output floating
regulator-name = "buck3";
regulator-max-microvolt = <1350000>;
regulator-min-microvolt = <700000>;
};
BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3000000>;
// BUCK6 in datasheet
// supplies ldo3, ldo5, muxsw
regulator-name = "buck4";
};
BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1995000>;
regulator-min-microvolt = <1605000>;
// BUCK7 in datasheet
// supplies ldo4, ldo6, muxsw
// enables dram vpp @ 2.5V
regulator-name = "buck5";
};
BUCK6 {
// BUCK8 in datasheet
// supplies dram @ 1.2V
regulator-name = "buck6";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1400000>;
regulator-min-microvolt = <800000>;
};
LDO1 {
// supplies soc snvs @ 1.8V
regulator-name = "ldo1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
};
LDO2 {
// supplies soc snvs @ 0.8V
regulator-name = "ldo2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <800000>;
};
LDO3 {
// supplies soc vdd @ 1.8V
regulator-name = "ldo3";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
LDO4 {
// output floating
regulator-name = "ldo4";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <900000>;
};
LDO5 {
// output floating
regulator-name = "ldo5";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
LDO6 {
// supplies soc vdd mipi @ 1.2V
regulator-name = "ldo6";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <900000>;
};
};
};
};
&i2c2 {
/*
* routed to various connectors:
* - basler camera (CON2)
* - touchscreen (J3)
* - expansion connector (J14)
*/
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
expander: gpio@20 {
compatible = "ti,tca6408";
reg = <0x20>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "SYSGD", "PFO#", "CAPGD", "CAPFLT#",
"CHGEN#", "BSTEN#", "", "";
pinctrl-0 = <&gpio_expander_pins>;
pinctrl-names = "default";
reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>;
};
light-sensor@44 {
compatible = "isil,isl29023";
reg = <0x44>;
};
accelerometer@53 {
compatible = "adi,adxl345";
reg = <0x53>;
};
/* battery-charger@68 */
rtc: rtc@69 {
compatible = "abracon,abx80x";
reg = <0x69>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&rtc_pins>;
pinctrl-names = "default";
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
};
};
&i2c4 {
/* routed to expansion connector (J14) */
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&tamper_pins>, <&usb_hub_pins>;
pinctrl-names = "default";
can_pins: pinctrl-can-grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x140
>;
};
ecspi2_pins: pinctrl-ecspi2-grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x96
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x1d6
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1d6
MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1d6
>;
};
fec1_pins: pinctrl-fec1-grp {
/*
* Some pins are sampled at phy reset to apply configuration:
* - AR803x PHY (revision 1.1)
* - RXD[1:0]: phy address bits [1:0]
* - RXD[3:2],RX_CTL: mac interface select bits 3,1,0
* - ADIN1300 PHY (revision 1.2 or later)
* - RXD[3:0]: phy address bits [3:0]
* - RX_CTL,RXC: mac interface select bits 1,0
* SoC enables pull-down at reset, PHYs have internal
* pull-down, so pinmux may unset pull-enable.
*/
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x2
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1e
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1e
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1e
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1e
/* RD[3:0] sampled at phy reset for address bits [3:0] */
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x10
/* phy reset */
MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0
/* phy interrupt */
MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
>;
};
gpio_expander_pins: pinctrl-gpio-expander-grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x140
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140
>;
};
i2c1_pins: pinctrl-i2c1-grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c2
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c2
>;
};
i2c2_pins: pinctrl-i2c2-grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
>;
};
i2c3_pins: pinctrl-i2c3-grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
>;
};
i2c4_pins: pinctrl-i2c4-grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
>;
};
ieee802151_radio_pins: pinctrl-ieee802151-radio-grp {
fsl,pins = <
/* RESETN */
MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x0
/* VDD_EN */
MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0
/* SWDCLK */
MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0
/* SDIO */
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0
>;
};
led_pins: pinctrl-led-grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x100
MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x100
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x100
>;
};
modem_pins: pinctrl-modem-grp {
fsl,pins = <
/* RESET_N: modem-internal pull-down */
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0
/* PWRKEY: pull-down ensures always-on */
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x100
>;
};
pmic_pins: pinctrl-pmic-grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
>;
};
regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0
>;
};
regulator_modem_vbus_pins: pinctrl-regulator-modem-vbus-grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0
>;
};
regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x0
>;
};
regulator_usdhc2_vmmc_pins: pinctrl-regulator-usdhc2-vmmc-grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0
>;
};
rtc_pins: pinctrl-rtc-grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x100
>;
};
tamper_pins: pinctrl-tamper-grp {
/*
* Routed to physical tamper input (J12),
* accelerometer and light-sensor interrupts.
*/
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x140
>;
};
uart1_pins: pinctrl-uart1-grp {
fsl,pins = <
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
/* BT_REG_ON */
MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
/* BT_WAKE_DEV */
MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0
/* BT_WAKE_HOST */
MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100
>;
};
uart2_pins: pinctrl-uart2-grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
uart3_pins: pinctrl-uart3-grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x140
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x140
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x140
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x140
>;
};
uart4_pins: pinctrl-uart4-grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
usb_hub_pins: pinctrl-usb-hub-grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x0
>;
};
usdhc1_pins: pinctrl-usdhc1-grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
/* wifi refclk */
MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0
/* WL_WAKE_HOST */
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100
/* WL_REG_ON */
MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0
>;
};
usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
/* usdhc2 signalling voltage pmic control */
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
>;
};
usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
/* usdhc2 signalling voltage pmic control */
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
>;
};
usdhc2_pins: pinctrl-usdhc2-grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
/* usdhc2 signalling voltage pmic control */
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140
>;
};
usdhc3_pins: pinctrl-usdhc3-grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
wdog1_pins: pinctrl-wdog1-grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
>;
};
};
/* Bluetooth */
&uart1 {
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
/* select 80MHz parent clock to support maximum baudrate 4Mbps */
assigned-clocks = <&clk IMX8MN_CLK_UART1>;
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
};
};
/* console */
&uart2 {
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
status = "okay";
};
/* RS485 */
&uart3 {
pinctrl-0 = <&uart3_pins>;
pinctrl-names = "default";
uart-has-rtscts;
fsl,dte-mode;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
/* 802.15.1 radio */
&uart4 {
pinctrl-0 = <&uart4_pins &ieee802151_radio_pins>;
pinctrl-names = "default";
status = "okay";
};
&usbotg1 {
disable-over-current;
dr_mode = "host";
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
/* WiFi */
&usdhc1 {
bus-width = <4>;
mmc-pwrseq = <&usdhc1_pwrseq>;
pinctrl-0 = <&usdhc1_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
status = "okay";
};
/* microSD */
&usdhc2 {
broken-cd;
bus-width = <4>;
pinctrl-0 = <&usdhc2_pins>;
pinctrl-1 = <&usdhc2_100mhz_pins>;
pinctrl-2 = <&usdhc2_200mhz_pins>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* eMMC */
&usdhc3 {
bus-width = <8>;
non-removable;
pinctrl-0 = <&usdhc3_pins>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
/*
* Use lowest drive strength for all high-speed modes to minimise
* electro-magnetic emissions.
* In this particular design HS-400 still works okay, no extra
* pinctrl for 100mhz and 200mhz are required.
*/
pinctrl-names = "default";
status = "okay";
};
&wdog1 {
pinctrl-0 = <&wdog1_pins>;
pinctrl-names = "default";
status = "okay";
};

7
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* Copyright (c) 2022-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
@ -10,10 +10,6 @@
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
};
&backlight_lvds {
status = "okay";
};
@ -36,6 +32,7 @@ &lcdif {
};
&mipi_dsi {
samsung,burst-clock-frequency = <600000000>;
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts
View File

@ -65,7 +65,6 @@ expander2: gpio@27 {
};
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
};

11
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -215,8 +215,7 @@ clk_ext4: clock-ext4 {
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@ -258,10 +257,10 @@ map0 {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};

912
arch/arm64/boot/dts/freescale/imx8mp-ab2.dts Normal file
View File

@ -0,0 +1,912 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020-2026 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
compatible = "fsl,imx8mp-ab2", "fsl,imx8mp";
model = "NXP i.MX8MP SOM on AB2";
chosen {
stdout-path = &uart2;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&pinctrl_gpio_led>;
pinctrl-names = "default";
status {
default-state = "on";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
label = "yellow:status";
};
};
native-hdmi-connector {
compatible = "hdmi-connector";
label = "HDMI OUT";
type = "a";
port {
hdmi_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
compatible = "regulator-fixed";
regulator-name = "ab2_ana_pwr";
pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
pinctrl-names = "default";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
compatible = "regulator-fixed";
regulator-name = "ab2_vdd_pwr_5v0";
pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
pinctrl-names = "default";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
dsp_vdev0vring0: vdev0vring0@942f0000 {
reg = <0 0x942f0000 0 0x8000>;
no-map;
};
dsp_vdev0vring1: vdev0vring1@942f8000 {
reg = <0 0x942f8000 0 0x8000>;
no-map;
};
dsp_vdev0buffer: vdev0buffer@94300000 {
compatible = "shared-dma-pool";
reg = <0 0x94300000 0 0x100000>;
no-map;
};
};
sound-ak4458 {
compatible = "fsl,imx-audio-card";
model = "ak4458-audio";
pri-dai-link {
format = "i2s";
link-name = "akcodec";
fsl,mclk-equal-bclk;
codec {
sound-dai = <&ak4458_1>, <&ak4458_2>;
};
cpu {
sound-dai = <&sai1>;
};
};
};
sound-ak5552 {
compatible = "fsl,imx-audio-card";
model = "ak5552-audio";
pri-dai-link {
format = "i2s";
link-name = "akcodec";
fsl,mclk-equal-bclk;
codec {
sound-dai = <&ak5552>;
};
cpu {
sound-dai = <&sai3>;
};
};
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
model = "audio-hdmi";
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
format = "i2s";
link-name = "micfil hifi";
cpu {
sound-dai = <&micfil>;
};
};
};
sound-xcvr {
compatible = "fsl,imx-audio-card";
model = "imx-audio-xcvr";
pri-dai-link {
link-name = "XCVR PCM";
cpu {
sound-dai = <&xcvr>;
};
};
};
memory@40000000 {
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
device_type = "memory";
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&aud2htx {
status = "okay";
};
&dsp {
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
status = "okay";
};
&dsp_reserved {
status = "okay";
};
&easrc {
#sound-dai-cells = <0>;
fsl,asrc-rate = <48000>;
status = "okay";
};
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-names = "default";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&flexspi {
pinctrl-0 = <&pinctrl_flexspi0>;
pinctrl-names = "default";
status = "okay";
mt25qu256aba: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&hdmi_pai {
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-0 = <&pinctrl_hdmi>;
pinctrl-names = "default";
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-names = "default";
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_pmic>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <800000>;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-names = "default";
status = "okay";
pca6408: gpio@20 {
compatible = "ti,tca6408";
reg = <0x20>;
#gpio-cells = <2>;
gpio-controller;
};
pca6416_2: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-names = "default";
status = "okay";
ak4458_1: audio-codec@10 {
compatible = "asahi-kasei,ak4458";
reg = <0x10>;
#sound-dai-cells = <0>;
AVDD-supply = <&reg_ab2_ana_pwr>;
DVDD-supply = <&reg_ab2_ana_pwr>;
reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
sound-name-prefix = "0";
};
ak4458_2: audio-codec@11 {
compatible = "asahi-kasei,ak4458";
reg = <0x11>;
#sound-dai-cells = <0>;
AVDD-supply = <&reg_ab2_ana_pwr>;
DVDD-supply = <&reg_ab2_ana_pwr>;
reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
sound-name-prefix = "1";
};
ak4458_3: audio-codec@12 {
compatible = "asahi-kasei,ak4458";
reg = <0x12>;
#sound-dai-cells = <0>;
AVDD-supply = <&reg_ab2_ana_pwr>;
DVDD-supply = <&reg_ab2_ana_pwr>;
reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
};
ak5552: audio-codec@13 {
compatible = "asahi-kasei,ak5552";
reg = <0x13>;
#sound-dai-cells = <0>;
AVDD-supply = <&reg_ab2_ana_pwr>;
DVDD-supply = <&reg_ab2_ana_pwr>;
reset-gpios = <&pca6416 2 GPIO_ACTIVE_LOW>;
};
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
#gpio-cells = <2>;
gpio-controller;
};
};
&iomuxc {
pinctrl-0 = <&pinctrl_hog>;
pinctrl-names = "default";
pinctrl_ab2_ana_pwr: ab2anapwrgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6
>;
};
pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x10
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6
MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6
MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6
MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6
MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6
MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6
MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6
MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6
MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6
MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
pinctrl_xcvr: xcvrgrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0xd6
MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6
MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6
>;
};
};
&lcdif3 {
status = "okay";
};
&micfil {
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
#sound-dai-cells = <0>;
pinctrl-0 = <&pinctrl_pdm>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pinctrl_pwm1>;
pinctrl-names = "default";
status = "okay";
};
&pwm2 {
pinctrl-0 = <&pinctrl_pwm2>;
pinctrl-names = "default";
status = "okay";
};
&pwm4 {
pinctrl-0 = <&pinctrl_pwm4>;
pinctrl-names = "default";
status = "okay";
};
&sai1 {
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>;
#sound-dai-cells = <0>;
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-names = "default";
fsl,dataline = <2 0xff 0xff>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai3 {
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>,
<&clk IMX8MP_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
#sound-dai-cells = <0>;
pinctrl-0 = <&pinctrl_sai3>;
pinctrl-names = "default";
fsl,sai-asynchronous;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sdma2 {
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
status = "okay";
};
&uart3 {
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-0 = <&pinctrl_uart3>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
bus-width = <4>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
};
&wdog1 {
pinctrl-0 = <&pinctrl_wdog>;
pinctrl-names = "default";
fsl,ext-reset-output;
status = "okay";
};
&xcvr {
#sound-dai-cells = <0>;
pinctrl-0 = <&pinctrl_xcvr>;
pinctrl-names = "default";
status = "okay";
};

3
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
View File

@ -266,8 +266,7 @@ mdio {
#size-cells = <0>;
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <3>;
reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;

3
arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
View File

@ -60,8 +60,7 @@ mdio {
#size-cells = <0>;
ethphy0: ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id0022.1640";
reg = <3>;
reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;

2
arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts
View File

@ -68,7 +68,7 @@ vmmc: regulator-mmc {
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
startup-delay-us = <250>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
View File

@ -345,7 +345,7 @@ &pinctrl_dhcom_l
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 MX8MP_SION
>;
};
};

98
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -134,7 +134,7 @@ reg_audio_pwr: regulator-audio-pwr {
enable-active-high;
};
reg_pcie0: regulator-pcie {
reg_m2_wlan: reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0_reg>;
@ -250,6 +250,13 @@ cpu {
};
};
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_pwrseq>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -595,7 +602,8 @@ ov5640_mipi_0_ep: endpoint {
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>;
reg = <0x3d>, <0x3f>, <0x3b>, <0x38>;
reg-names = "main", "edid", "cec", "packet";
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
@ -825,6 +833,10 @@ &uart1 { /* BT */
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&uart2 {
@ -858,6 +870,19 @@ &uart3 {
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
keep-power-in-suspend;
non-removable;
wakeup-source;
mmc-pwrseq = <&usdhc1_pwrseq>;
vmmc-supply = <&reg_m2_wlan>;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
@ -965,33 +990,33 @@ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_flexcan_phy: flexcanphygrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
>;
};
@ -1044,8 +1069,8 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
pinctrl_i2c5: i2c5grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>;
};
@ -1064,7 +1089,7 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140
>;
};
@ -1164,6 +1189,45 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc1_pwrseq: usdhc1pwrseqgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190

538
arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
View File

@ -42,6 +42,67 @@ memory@40000000 {
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0x40000000>;
};
native-hdmi-connector {
compatible = "hdmi-connector";
label = "HDMI OUT";
type = "a";
port {
hdmi_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
reg_usdhc2_vmmc: regulator-sd {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc1_vmmc: regulator-wifi-vmmc {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>;
/*
* IW612 wifi chip needs more delay than other wifi chips to complete
* the host interface initialization after power up, otherwise the
* internal state of IW612 may be unstable, resulting in the failure of
* the SDIO3.0 switch voltage.
*/
enable-active-high;
startup-delay-us = <20000>;
};
reg_usdhc1_vqmmc: regulator-wifi-vqmmc {
compatible = "regulator-fixed";
regulator-name = "regulator-wifi-vqmmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
};
sdio_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
};
&A53_0 {
@ -60,6 +121,146 @@ &A53_3 {
cpu-supply = <&reg_arm>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
snps,force_thresh_dma_mode;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_phy>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
snps,map-to-dma-channel = <4>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
eee-broken-1000t;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,aldps-enable;
realtek,clkout-disable;
};
};
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -218,6 +419,10 @@ &i2c3 {
status = "okay";
};
&lcdif3 {
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
@ -237,6 +442,58 @@ &uart3 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&reg_usdhc1_vmmc>;
vqmmc-supply = <&reg_usdhc1_vqmmc>;
bus-width = <4>;
non-removable;
no-sd;
no-mmc;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
@ -250,106 +507,291 @@ &usdhc3 {
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
>;
};
pinctrl_eqos_phy: eqosphygrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
>;
};
pinctrl_fec_phy: fecphygrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* Pin might be required by multiple drivers
* (e. g. HDMI Audio and HDMI TX)
*/
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
pinctrl_pcal6416_0_int: pcal6416-0-int-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16
(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_pcal6416_1_int: pcal6416-1-int-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11
(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
(MX8MP_FSEL_FAST | MX8MP_PULL_UP |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 MX8MP_USDHC_DATA_DEFAULT
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST |
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
>;
};
};

67
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*
* Overlay for enabling HummingBoard IIoT MIPI-DSI connector
* with Winstar WJ70N3TYJHMNG0 panel.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
&{/} {
dsi_backlight: dsi-backlight {
compatible = "gpio-backlight";
gpios = <&tca6408_u48 3 GPIO_ACTIVE_LOW>;
};
};
&i2c_dsi {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili2130";
reg = <0x41>;
interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tca6408_u48 6 GPIO_ACTIVE_LOW>;
};
};
&lcdif1 {
status = "okay";
};
&mipi_dsi {
#address-cells = <1>;
#size-cells = <0>;
samsung,esc-clock-frequency = <10000000>;
status = "okay";
panel@0 {
/* This is a Winstar panel, but the ronbo panel uses same controls. */
compatible = "ronbo,rb070d30";
reg = <0>;
/* reset is active-low but driver inverts it internally */
reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>;
backlight = <&dsi_backlight>;
power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>;
shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>;
updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>;
vcc-lcd-supply = <&reg_dsi_panel>;
port {
panel_from_dsim: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
};
&mipi_dsi_out {
data-lanes = <1 2 3 4>;
remote-endpoint = <&panel_from_dsim>;
};

97
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*
* Overlay for enabling HummingBoard IIoT LVDS connector
* with Winstar WF70A8SYJHLNGA panel.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
&{/} {
lvds_backlight: lvds-backlight {
compatible = "gpio-backlight";
gpios = <&tca6408_u37 3 GPIO_ACTIVE_LOW>;
};
panel-lvds {
compatible = "winstar,wf70a8syjhlnga", "panel-lvds";
backlight = <&lvds_backlight>;
data-mapping = "vesa-24";
enable-gpios = <&tca6408_u37 2 GPIO_ACTIVE_HIGH>;
height-mm = <86>;
power-supply = <&reg_dsi_panel>;
reset-gpios = <&tca6408_u37 1 GPIO_ACTIVE_HIGH>;
width-mm = <154>;
panel-timing {
/*
* Note: NXP BSP hard-codes 74MHz clock in ldb driver:
* drivers/gpu/drm/imx/imx8mp-ldb.c
* SolidRun BSP carries patch.
*/
clock-frequency = <49500000>;
de-active = <1>;
hactive = <1024>;
hback-porch = <144>;
hfront-porch = <40>;
hsync-active = <0>;
hsync-len = <104>;
vactive = <600>;
vback-porch = <11>;
vfront-porch = <3>;
vsync-active = <1>;
vsync-len = <10>;
};
port {
panel_from_lvds: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
};
&i2c_lvds {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@41 {
compatible = "ilitek,ili2130";
reg = <0x41>;
interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tca6408_u37 6 GPIO_ACTIVE_LOW>;
};
};
&lcdif2 {
status = "okay";
};
&ldb_lvds_ch0 {
remote-endpoint = <&panel_from_lvds>;
};
&lvds_bridge {
status = "okay";
};
&tca6408_u37 {
lvds-lr-hog {
gpios = <4 GPIO_ACTIVE_HIGH>;
gpio-hog;
line-name = "lvds-l/r";
output-high;
};
lvds-ud-hog {
gpios = <5 GPIO_ACTIVE_HIGH>;
gpio-hog;
line-name = "lvds-u/d";
output-high;
};
};

18
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*
* Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
*/
/dts-v1/;
/plugin/;
&uart3 {
linux,rs485-enabled-at-boot-time;
};
&uart3_rs_232_485_mux {
/* select rs485 */
idle-state = <1>;
};

18
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*
* Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004.
*/
/dts-v1/;
/plugin/;
&uart4 {
linux,rs485-enabled-at-boot-time;
};
&uart4_rs_232_485_mux {
/* select rs485 */
idle-state = <1>;
};

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arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 Yazan Shhady <yazan.shhady@solid-run.com>
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-sr-som.dtsi"
/ {
compatible = "solidrun,imx8mp-hummingboard-iiot",
"solidrun,imx8mp-sr-som", "fsl,imx8mp";
model = "SolidRun i.MX8MP HummingBoard IIoT";
/* power for M.2 B-Key connector (J6) */
regulator-m2-b {
compatible = "regulator-fixed";
regulator-name = "m2-b";
gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
enable-active-high;
};
/* power for M.2 M-Key connector (J4) */
regulator-m2-m {
compatible = "regulator-fixed";
regulator-name = "m2-m";
gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
enable-active-high;
};
/* power for USB-A J27 behind USB Hub Port 3 */
regulator-vbus-2 {
compatible = "regulator-fixed";
regulator-name = "vbus2";
regulator-always-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* power for USB-A J27 behind USB Hub Port 4 */
regulator-vbus-3 {
compatible = "regulator-fixed";
regulator-name = "vbus3";
regulator-always-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
aliases {
/* J10 */
ethernet0 = &eqos;
/* J11 */
ethernet1 = &fec;
gpio5 = &tca6408_u48;
gpio6 = &tca6408_u37;
gpio7 = &tca6416_u20;
gpio8 = &tca6416_u21;
i2c6 = &i2c_exp;
i2c7 = &i2c_csi;
i2c8 = &i2c_dsi;
i2c9 = &i2c_lvds;
rtc0 = &carrier_rtc;
rtc1 = &snvs_rtc;
};
gpio-keys {
compatible = "gpio-keys";
wakeup-event {
interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>;
label = "m2-m-wakeup";
wakeup-source;
linux,code = <KEY_WAKEUP>;
};
};
can_mux: mux-controller-0 {
compatible = "gpio-mux";
/*
* Mux routes CAN bus signals between SoM connector pins,
* expansion connector (J22) and on-board transceivers using
* two GPIO:
* - IO3: 0 = on-board transceivers, 1 = expansion connector
* - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56
*/
mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>,
<&tca6416_u20 4 GPIO_ACTIVE_HIGH>;
/* default J7-12/16 & J9-54/56 to on-board transceivers */
idle-state = <2>;
#mux-control-cells = <0>;
};
spi_mux: mux-controller-1 {
compatible = "gpio-mux";
/* default on-board */
idle-state = <0>;
/*
* Mux switches spi bus between on-board tpm
* and expansion connector (J22).
*/
mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>;
#mux-control-cells = <0>;
};
uart3_uart4_b2b_mux: mux-controller-2 {
compatible = "gpio-mux";
/* default on-board */
idle-state = <0>;
/*
* Mux switches both uart3 and uart4 tx/rx between expansion
* connector (J22) and on-board rs232/rs485 transceivers
* using one GPIO: 0 = on-board, 1 = connector.
*/
mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>;
#mux-control-cells = <0>;
};
uart3_rs_232_485_mux: mux-controller-3 {
compatible = "gpio-mux";
/* default rs232 */
idle-state = <0>;
/*
* Mux switches uart3 tx/rx between rs232 and rs485
* transceivers. using one GPIO: 0 = rs232, 1 = rs485.
*/
mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>;
#mux-control-cells = <0>;
};
uart4_rs_232_485_mux: mux-controller-4 {
compatible = "gpio-mux";
/* default rs232 */
idle-state = <0>;
/*
* Mux switches uart4 tx/rx between rs232 and rs485
* transceivers. using one GPIO: 0 = rs232, 1 = rs485.
*/
mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>;
#mux-control-cells = <0>;
};
v_1_2: regulator-1-2 {
compatible = "regulator-fixed";
regulator-name = "1v2";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
};
reg_dsi_panel: regulator-dsi-panel {
compatible = "regulator-fixed";
regulator-name = "dsi-panel";
gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>;
regulator-max-microvolt = <11200000>;
regulator-min-microvolt = <11200000>;
enable-active-high;
};
vmmc: regulator-mmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
pinctrl-0 = <&vmmc_pins>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
startup-delay-us = <250>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* power for USB-A J5003 */
vbus1: regulator-vbus-1 {
compatible = "regulator-fixed";
regulator-name = "vbus1";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
gpio = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
rfkill-m2-b-gnss {
compatible = "rfkill-gpio";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>;
label = "m2-b gnss";
radio-type = "gps";
};
rfkill-m2-b-wwan {
compatible = "rfkill-gpio";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>;
label = "m2-b radio";
radio-type = "wwan";
};
};
&ecspi2 {
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
num-cs = <1>;
pinctrl-0 = <&ecspi2_pins>;
pinctrl-names = "default";
status = "okay";
ecspi2_muxed: spi@0 {
compatible = "spi-mux";
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mux-controls = <&spi_mux>;
/* mux bandwidth is 2GHz, soc max. spi clock is 166MHz */
spi-max-frequency = <166000000>;
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
spi-max-frequency = <43000000>;
};
};
};
&flexcan1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
can-transceiver {
max-bitrate = <8000000>;
};
};
&flexcan2 {
pinctrl-0 = <&can2_pins>;
pinctrl-names = "default";
status = "okay";
can-transceiver {
max-bitrate = <8000000>;
};
};
&i2c2 {
i2c-mux@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
/*
* This reset is open drain,
* but reset core does not support GPIO_OPEN_DRAIN flag.
*/
reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
/* channel 0 routed to expansion connector (J22) */
i2c_exp: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
/* channel 1 routed to mipi-csi connector (J23) */
i2c_csi: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
/* channel 2 routed to mipi-dsi connector (J25) */
i2c_dsi: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
tca6408_u48: gpio@21 {
compatible = "ti,tca6408";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "CAM_RST#", "DSI_RESET",
"DSI_STBYB", "DSI_PWM_BL",
"DSI_L/R", "DSI_U/D",
"DSI_CTP_/RST", "CAM_TRIG";
/*
* reset shared between U37 and U48, to be
* supported once gpio-pca953x switches to
* reset framework.
*
* reset-gpios = <&tca6416_u21 4
* (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
*/
};
};
/* channel 2 routed to lvds connector (J24) */
i2c_lvds: i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
tca6408_u37: gpio@20 {
compatible = "ti,tca6408";
reg = <0x20>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "SELB", "LVDS_RESET",
"LVDS_STBYB", "LVDS_PWM_BL",
"LVDS_L/R", "LVDS_U/D",
"LVDS_CTP_/RST", "";
/*
* reset shared between U37 and U48, to be
* supported once gpio-pca953x switches to
* reset framework.
*
* reset-gpios = <&tca6416_u21 4
* (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
*/
};
};
};
};
&i2c3 {
/* highest i2c clock supported by all peripherals is 400kHz */
clock-frequency = <400000>;
tca6416_u20: gpio@20 {
reg = <0x20>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485",
"TCA_UARTB_232/485", "TCA_INT/EXT_CAN",
"TCA_NXP/REN", "TCA_M.2B_3V3_EN",
"TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#",
"TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#",
"TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#",
"TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN",
"TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN";
/*
* This is a TI TCAL6416 using same programming model as
* NXP PCAL6416, not to be confused with TI TCA6416.
*/
compatible = "nxp,pcal6416";
m2-b-reset-hog {
gpios = <8 GPIO_ACTIVE_LOW>;
gpio-hog;
line-name = "m2-b-reset";
output-low;
};
};
tca6416_u21: gpio@21 {
reg = <0x21>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
"TCA_I2C_RST", "TCA_RS232_SHTD#",
"TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
"TCA_bDIG_IN1", "TCA_SENS_INT",
"TCA_ALERT#", "TCA_TPM_PIRQ#",
"TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
"TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
"", "TCA_POE_AT";
interrupts-extended = <&gpio1 15 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&tca6416_u21_int_pins>;
pinctrl-names = "default";
/*
* This is a TI TCAL6416 using same programming model as
* NXP PCAL6416, not to be confused with TI TCA6416.
*/
compatible = "nxp,pcal6416";
lcd-i2c-reset-hog {
gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
line-name = "lcd-i2c-reset";
output-low;
/*
* reset shared between U37 and U48, to be
* supported once gpio-pca953x switches to
* reset framework.
*/
gpio-hog;
};
m2-m-clkreq-hog {
gpios = <12 GPIO_ACTIVE_LOW>;
gpio-hog;
input;
line-name = "m2-m-clkreq";
};
rs232_shutdown: rs232-shutdown-hog {
gpios = <3 GPIO_ACTIVE_LOW>;
gpio-hog;
line-name = "rs232-shutdown";
output-low;
};
};
led-controller@30 {
compatible = "ti,lp5562";
reg = <0x30>;
#address-cells = <1>;
#size-cells = <0>;
/* use internal clock, could use external generated by rtc */
clock-mode = /bits/ 8 <1>;
multi-led@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
color = <LED_COLOR_ID_RGB>;
label = "D7";
led@0 {
reg = <0x0>;
color = <LED_COLOR_ID_RED>;
led-cur = /bits/ 8 <0x32>;
max-cur = /bits/ 8 <0x64>;
};
led@1 {
reg = <0x1>;
color = <LED_COLOR_ID_GREEN>;
led-cur = /bits/ 8 <0x19>;
max-cur = /bits/ 8 <0x32>;
};
led@2 {
reg = <0x2>;
color = <LED_COLOR_ID_BLUE>;
led-cur = /bits/ 8 <0x19>;
max-cur = /bits/ 8 <0x32>;
};
};
led@3 {
reg = <0x3>;
chan-name = "D8";
color = <LED_COLOR_ID_GREEN>;
label = "D8";
led-cur = /bits/ 8 <0x19>;
max-cur = /bits/ 8 <0x64>;
};
};
light-sensor@44 {
compatible = "isil,isl29023";
reg = <0x44>;
/* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>;
};
accelerometer@53 {
compatible = "adi,adxl345";
reg = <0x53>;
/* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "INT1";
};
carrier_eeprom: eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
pagesize = <8>;
};
carrier_rtc: rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
/*
* AM1805 RTC used on this board has only nTIRQ pins wired,
* which is for countdown timer irqs only.
* Driver does not support this, disable for now.
*
* interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_EDGE_FALLING>;
*/
};
};
&iomuxc {
can1_pins: pinctrl-can1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
can2_pins: pinctrl-can2-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
ecspi2_pins: pinctrl-ecspi2-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
>;
};
tca6416_u21_int_pins: pinctrl-tca6416-u21-int-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x0
>;
};
/* UARTA */
uart3_pins: pinctrl-uart3-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
>;
};
/* UARTB */
uart4_pins: pinctrl-uart4-grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140
>;
};
usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
usdhc2_pins: pinctrl-usdhc2-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
vmmc_pins: pinctrl-vmmc-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0
>;
};
};
&pcie {
reset-gpio = <&tca6416_u20 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* M.2 M-Key (J4) */
&pcie_phy {
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
status = "okay";
};
&phy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
/* ADIN1300 LED_0 pin */
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
default-state = "keep";
function = LED_FUNCTION_LAN;
};
};
};
&phy1 {
leds {
#address-cells = <1>;
#size-cells = <0>;
/* ADIN1300 LED_0 pin */
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
default-state = "keep";
function = LED_FUNCTION_LAN;
};
};
};
&uart3 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
/* select 80MHz parent clock to support maximum baudrate 4Mbps */
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
pinctrl-0 = <&uart3_pins>;
pinctrl-names = "default";
rts-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart4 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
/* select 80MHz parent clock to support maximum baudrate 4Mbps */
assigned-clocks = <&clk IMX8MP_CLK_UART4>;
pinctrl-0 = <&uart4_pins>;
pinctrl-names = "default";
rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&vbus1>;
fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
};
&usb_dwc3_1 {
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
hub_2_0: hub@1 {
compatible = "usb4b4,6502", "usb4b4,6506";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
vdd2-supply = <&v_3_3>;
vdd-supply = <&v_1_2>;
};
hub_3_0: hub@2 {
compatible = "usb4b4,6500", "usb4b4,6504";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
vdd2-supply = <&v_3_3>;
vdd-supply = <&v_1_2>;
};
};
&usdhc2 {
bus-width = <4>;
cap-power-off-card;
full-pwr-cycle;
pinctrl-0 = <&usdhc2_pins>;
pinctrl-1 = <&usdhc2_100mhz_pins>;
pinctrl-2 = <&usdhc2_200mhz_pins>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&vmmc>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi
View File

@ -73,7 +73,7 @@ vmmc: regulator-mmc {
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
startup-delay-us = <250>;
};

13
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi
View File

@ -41,7 +41,7 @@ port@0 {
reg = <0>;
adv7535_from_dsim: endpoint {
remote-endpoint = <&dsim_to_adv7535>;
remote-endpoint = <&mipi_dsi_out>;
};
};
@ -71,11 +71,8 @@ &lcdif1 {
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
port@1 {
dsim_to_adv7535: endpoint {
remote-endpoint = <&adv7535_from_dsim>;
attach-bridge;
};
};
};
&mipi_dsi_out {
remote-endpoint = <&adv7535_from_dsim>;
};

26
arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso
View File

@ -7,6 +7,7 @@
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mp-pinfunc.h"
&{/} {
@ -77,12 +78,14 @@ &i2c1 {
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupt-parent = <&gpio1>;
interrupts = <6 8>;
irq-gpios = <&gpio1 6 0>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
irq-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
AVDD28-supply = <&reg_vcc_panel>;
VDDIO-supply = <&reg_vcc_panel>;
reset-gpios = <&gpio1 7 0>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
};
@ -98,6 +101,16 @@ &lvds_bridge {
status = "okay";
};
/* redefine to remove touch controller GPIOs */
&pinctrl_gpio1 {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x19 /* GPIO_A_0 */
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x19 /* GPIO_A_1 */
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 /* GPIO_A_2 */
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19 /* GPIO_A_5 */
>;
};
&pwm1 {
status = "okay";
};
@ -108,4 +121,11 @@ pinctrl_panel_stby: panelstbygrp {
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x19
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
>;
};
};

6
arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi
View File

@ -330,6 +330,12 @@ rv3028: rtc@52 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio3 24 IRQ_TYPE_LEVEL_LOW>;
/*
* While specifying the vdd-supply is normally not strictly necessary,
* here it also makes sure that the PMIC driver enables the level-
* shifter for the RTC before the RTC is probed.
*/
vdd-supply = <&reg_vdd_3v3>;
};
};

1
arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts
View File

@ -249,6 +249,5 @@ &usb3_phy1 {
};
&usdhc2 {
vmmc-supply = <&reg_vdd_3v3>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h
View File

@ -36,7 +36,7 @@
/* long defaults */
#define MX8MP_USDHC_DATA_DEFAULT (MX8MP_FSEL_FAST | MX8MP_PULL_UP | \
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
#define MX8MP_I2C_DEFAULT (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | \
#define MX8MP_I2C_DEFAULT (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | \
MX8MP_PULL_ENABLE | MX8MP_SION)
/*

72
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
View File

@ -184,6 +184,9 @@ &eqos {
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy3>;
snps,force_thresh_dma_mode;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
status = "okay";
mdio {
@ -209,6 +212,70 @@ ethphy3: ethernet-phy@3 {
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
snps,map-to-dma-channel = <4>;
};
};
};
&fec {
@ -520,6 +587,7 @@ &uart2 {
bluetooth {
compatible = "nxp,88w8987-bt";
vcc-supply = <&reg_vcc_3v3>;
};
};
@ -848,8 +916,8 @@ pinctrl_tlv320aic3x04: tlv320aic3x04grp {
pinctrl_uart1: uart1grp {
fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>,
<MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>,
<MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>,
<MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>;
<MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x14>,
<MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x14>;
};
pinctrl_uart1_gpio: uart1gpiogrp {

6
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* Copyright (c) 2023-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
@ -10,10 +10,6 @@
#include <dt-bindings/clock/imx8mp-clock.h>
&{/} {
compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
};
&backlight_lvds {
status = "okay";
};

6
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>,
* Copyright (c) 2022-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
@ -8,10 +8,6 @@
/dts-v1/;
/plugin/;
&{/} {
compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
};
&backlight_lvds {
status = "okay";
};

67
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@ -336,6 +336,9 @@ &eqos {
pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy3>;
snps,force_thresh_dma_mode;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
status = "okay";
mdio {
@ -359,6 +362,70 @@ ethphy3: ethernet-phy@3 {
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
snps,map-to-dma-channel = <4>;
};
};
};
&fec {

1
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso
View File

@ -77,6 +77,7 @@ connector {
compatible = "usb-c-connector";
data-role = "host";
pd-disable;
typec-power-opmode = "default";
vbus-supply = <&reg_vbus>;
port {

16
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts
View File

@ -302,36 +302,36 @@ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c4_gpio: i2c4-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
>;
};

8
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
View File

@ -425,18 +425,18 @@ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
>;
};
pinctrl_i2c1_gpio: i2c1-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15
MX8MP_I2C_DEFAULT
(MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT)
>;
};

11
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -310,8 +310,7 @@ dsp_reserved: dsp@92400000 {
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@ -397,10 +396,10 @@ map0 {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};

6
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2019-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
* Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
@ -10,10 +10,6 @@
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
};
&backlight_lvds {
status = "okay";
};

10
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -611,9 +611,17 @@ ptn5110: tcpc@51 {
usb_con1: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "source";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
/*
* Set operational current to 0mA as we don't want EN_SNK
* enable 12V VBUS switch when it work as a sink.
*/
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <0>;
self-powered;
ports {
#address-cells = <1>;

5
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
View File

@ -20,8 +20,9 @@ pcie0: pciea: pcie@5f000000 {
ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>,
<0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi", "dma";
#address-cells = <3>;
#size-cells = <2>;
clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,

10
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -566,9 +566,17 @@ ptn5110: tcpc@50 {
usb_con1: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "source";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
/*
* Set operational current to 0mA as we don't want EN_SNK
* enable 12V VBUS switch when it work as a sink.
*/
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <0>;
self-powered;
ports {
#address-cells = <1>;

3
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@ -86,8 +86,7 @@ gic: interrupt-controller@2d400000 {
pmu {
compatible = "arm,cortex-a35-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A35_0>, <&A35_1>;
};

98
arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
View File

@ -23,6 +23,7 @@ aliases {
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
@ -57,6 +58,15 @@ reg_audio_pwr: regulator-audio-pwr {
enable-active-high;
};
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-name = "M.2-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
@ -69,6 +79,23 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
enable-active-high;
};
reg_usdhc3_vmmc: regulator-usdhc3 {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_m2_pwr>;
gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
/*
* IW612 wifi chip needs more delay than other wifi chips to complete
* the host interface initialization after power up, otherwise the
* internal state of IW612 may be unstable, resulting in the failure of
* the SDIO3.0 switch voltage.
*/
startup-delay-us = <20000>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
@ -144,6 +171,11 @@ cpu {
};
};
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
};
};
&adc1 {
@ -246,6 +278,12 @@ pcal6524: gpio@22 {
interrupt-parent = <&gpio3>;
pinctrl-0 = <&pinctrl_pcal6524>;
pinctrl-names = "default";
m2-pcm-level-shifter-hog {
gpio-hog;
gpios = <19 GPIO_ACTIVE_HIGH>;
output-high;
};
};
pmic@25 {
@ -514,6 +552,7 @@ &usdhc1 {
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
fsl,tuning-step = <1>;
status = "okay";
};
@ -528,6 +567,22 @@ &usdhc2 {
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <&reg_usdhc2_vmmc>;
fsl,tuning-step = <1>;
status = "okay";
};
&usdhc3 {
bus-width = <4>;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc3_pwrseq>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <&reg_usdhc3_vmmc>;
wakeup-source;
status = "okay";
};
@ -850,4 +905,47 @@ MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
};

769
arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts Normal file
View File

@ -0,0 +1,769 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx91.dtsi"
/ {
compatible = "fsl,imx91-11x11-frdm-s", "fsl,imx91";
model = "NXP FRDM-IMX91S board";
aliases {
ethernet0 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &pcf2131;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
serial4 = &lpuart5;
};
chosen {
stdout-path = &lpuart1;
};
flexcan1_phy: can-phy {
compatible = "nxp,tja1051";
#phy-cells = <0>;
max-bitrate = <5000000>;
silent-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_gpio_key>;
pinctrl-names = "default";
button {
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
gpios = <&gpio3 26 GPIO_PULL_UP>;
label = "User Button";
linux,code = <BTN_1>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-0 {
default-state = "on";
gpios = <&pcal6524 7 GPIO_ACTIVE_LOW>;
label = "green:status";
};
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "vref_1v8";
};
reg_usdhc1_vmmc: regulator-usdhc1 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "WLAN_EN";
startup-delay-us = <20000>;
gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
bootph-pre-ram;
bootph-some-ram;
};
reg_usb_vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "USB_VBUS";
gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x20000000>;
reusable;
size = <0 0x2000000>;
linux,cma-default;
};
};
soc@0 {
bootph-all;
bootph-pre-ram;
};
sound-mqs {
compatible = "fsl,imx-audio-mqs";
model = "mqs-audio";
audio-codec = <&mqs1>;
audio-cpu = <&sai1>;
};
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 18 GPIO_ACTIVE_LOW>;
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&clk {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};
&eqos {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
};
};
};
&flexcan1 {
phys = <&flexcan1_phy>;
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-1 = <&pinctrl_flexcan1_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&flexspi1 {
pinctrl-0 = <&pinctrl_flexspi1>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <104000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x000000 0x800000>;
label = "bootloader";
};
partition@1 {
reg = <0x800000 0x800000>;
label = "env";
};
partition@2 {
reg = <0x1000000 0x2800000>;
label = "kernel";
};
partition@3 {
reg = <0x3800000 0x20000>;
label = "dtb";
};
partition@4 {
reg = <0x3820000 0xc7e0000>;
label = "rootfs";
linux,rootfs;
};
};
};
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__CAN1_TX 0x139e
MX91_PAD_GPIO_IO29__CAN1_RX 0x139e
MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_flexcan1_sleep: flexcan1sleepgrp {
fsl,pins = <
MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e
MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e
MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <
MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe
MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe
MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x3fe
MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x3fe
MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x3fe
MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x3fe
>;
};
pinctrl_gpio_key: gpiokeysgrp {
fsl,pins = <
MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_mqs1: mqs1grp {
fsl,pins = <
MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e
MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
MX91_PAD_SD1_DATA5__GPIO3_IO15 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
bootph-pre-ram;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e
MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e
MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e
MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
bootph-pre-ram;
bootph-some-ram;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-names = "default";
bootph-pre-ram;
bootph-some-ram;
status = "okay";
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupt-parent = <&pcal6524>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-names = "default";
bootph-pre-ram;
bootph-some-ram;
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
pinctrl-0 = <&pinctrl_pcal6524>;
pinctrl-names = "default";
reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
};
pmic@32 {
compatible = "nxp,pf9453";
reg = <0x32>;
interrupt-parent = <&pcal6524>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
bootph-pre-ram;
bootph-some-ram;
regulators {
bootph-pre-ram;
bootph-some-ram;
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3775000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK1";
};
buck2: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <12500>;
};
buck3: BUCK3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3775000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK3";
};
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3775000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK4";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
regulator-name = "LDO1";
};
ldo2: LDO2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <500000>;
regulator-name = "LDO2";
};
ldo_snvs: LDO-SNVS {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <1200000>;
regulator-name = "LDO-SNVS";
};
};
};
ptn5110: tcpc@52 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x52>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec1_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
};
&lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&lpuart5 {
pinctrl-0 = <&pinctrl_uart5>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&media_blk_ctrl {
status = "okay";
};
&mqs1 {
clocks = <&clk IMX93_CLK_MQS1_GATE>;
clock-names = "mclk";
pinctrl-0 = <&pinctrl_mqs1>;
pinctrl-names = "default";
status = "okay";
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&sai1 {
clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k";
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <24576000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
vbus-supply = <&reg_usb_vbus>;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
};
&usdhc1 {
bus-width = <8>;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc1_pwrseq>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&reg_usdhc1_vmmc>;
wakeup-source;
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <&reg_usdhc2_vmmc>;
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&wdog3 {
pinctrl-0 = <&pinctrl_wdog>;
pinctrl-names = "default";
fsl,ext-reset-output;
status = "okay";
};

471
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Variscite Sonata carrier board for DART-MX91
*
* Link: https://variscite.com/carrier-boards/sonata-board/
*
* Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include "imx91-var-dart.dtsi"
/ {
model = "Variscite DART-MX91 on Sonata-Board";
compatible = "variscite,var-dart-mx91-sonata",
"variscite,var-dart-mx91",
"fsl,imx91";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
};
chosen {
stdout-path = &lpuart1;
};
gpio-keys {
compatible = "gpio-keys";
button-home {
label = "Home";
linux,code = <KEY_HOME>;
gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
button-back {
label = "Back";
linux,code = <KEY_BACK>;
gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
led-emmc {
label = "eMMC";
gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VDD_SD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <20000>;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x40000000>;
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
/* Use external instead of internal RTC */
&bbnsm_rtc {
status = "disabled";
};
&eqos {
mdio {
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca6408_1: gpio@20 {
compatible = "nxp,pcal6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
pca6408_2: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
pca9534: gpio@22 {
compatible = "nxp,pca9534";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
/* USB Type-C Controller */
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_extcon>;
interrupt-parent = <&gpio4>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
/* Console (J10) */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Header (J12.4, J12.6) */
&lpuart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;
no-mmc;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
/* GPIO Expanders shared IRQ */
MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_captouch: captouchgrp {
fsl,pins = <
MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_extcon: extcongrp {
fsl,pins = <
MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x37e
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX91_PAD_PDM_CLK__CAN1_TX 0x139e
MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp {
fsl,pins = <
MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e
MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX91_PAD_GPIO_IO05__LPUART6_RX 0x31e
MX91_PAD_GPIO_IO04__LPUART6_TX 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite DART-MX91
*
* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx91.dtsi"
/ {
model = "Variscite DART-MX91 Module";
compatible = "variscite,var-dart-mx91", "fsl,imx91";
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
snps,clk-csr = <5>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX93_CLK_SAI1_GATE>;
clock-names = "mclk";
AVDD-supply = <&buck5>;
CPVDD-supply = <&buck5>;
DBVDD-supply = <&buck4>;
DCVDD-supply = <&buck5>;
MICVDD-supply = <&buck5>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
/* DMIC is connected to IN1L */
wlf,in1l-as-dmicdat1;
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <2237500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
/* BT module */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&sai1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
mmc-pwrseq = <&wifi_pwrseq>;
keep-power-in-suspend;
bus-width = <4>;
non-removable;
wakeup-source;
status = "okay";
};
&wdog3 {
status = "okay";
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e
>;
};
pinctrl_eqos_sleep: eqos-sleepgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
fsl,pins = <
MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e
MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e
MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e
MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e
>;
};
pinctrl_sai1_sleep: sai1-sleepgrp {
fsl,pins = <
MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e
MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e
MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e
MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e
MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e
MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e
MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
pinctrl_usdhc3_wlan: usdhc3wlangrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e
>;
};
};

2
arch/arm64/boot/dts/freescale/imx91.dtsi
View File

@ -11,7 +11,7 @@ thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 0>;
thermal-sensors = <&tmu>;
trips {
cpu_alert: cpu-alert {

64
arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
View File

@ -69,7 +69,7 @@ clk_ext1: clock-ext1 {
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@ -79,10 +79,10 @@ psci {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
@ -1122,8 +1122,62 @@ media_blk_ctrl: system-controller@4ac10000 {
<&clk IMX93_CLK_MIPI_DSI_GATE>;
clock-names = "apb", "axi", "nic", "disp", "cam",
"pxp", "lcdif", "isi", "csi", "dsi";
assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>,
<&clk IMX93_CLK_MEDIA_DISP_PIX>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_VIDEO_PLL>;
assigned-clock-rates = <400000000>, <133333333>;
#power-domain-cells = <1>;
status = "disabled";
dpi_bridge: dpi-bridge {
compatible = "nxp,imx93-pdfc";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpi_from_lcdif: endpoint {
remote-endpoint = <&lcdif_to_dpi>;
};
};
port@1 {
reg = <1>;
dpi_to_panel: endpoint {
};
};
};
};
};
lcdif: display-controller@4ae30000 {
compatible = "fsl,imx93-lcdif";
reg = <0x4ae30000 0x23c>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>,
<&clk IMX93_CLK_LCDIF_GATE>,
<&clk IMX93_CLK_MEDIA_AXI>;
clock-names = "pix", "axi", "disp_axi";
power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>;
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
lcdif_to_dpi: endpoint@0 {
reg = <0>;
remote-endpoint = <&dpi_from_lcdif>;
};
};
};
usbotg1: usb@4c100000 {

861
arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi Normal file
View File

@ -0,0 +1,861 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022,2026 NXP
*/
#include <dt-bindings/usb/pd.h>
/ {
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
};
chosen {
stdout-path = &lpuart1;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
vdev0vring0: vdev0vring0@a4000000 {
reg = <0 0xa4000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@a4008000 {
reg = <0 0xa4008000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@a4010000 {
reg = <0 0xa4010000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@a4018000 {
reg = <0 0xa4018000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@2021e000 {
reg = <0 0x2021e000 0 0x1000>;
no-map;
};
vdevbuffer: vdevbuffer@a4020000 {
compatible = "shared-dma-pool";
reg = <0 0xa4020000 0 0x100000>;
no-map;
};
};
flexcan_phy: can-phy {
compatible = "nxp,tja1057";
#phy-cells = <0>;
max-bitrate = <5000000>;
silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>;
};
reg_vdd_12v: regulator-vdd-12v {
compatible = "regulator-fixed";
regulator-name = "VDD_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <12000>;
enable-active-high;
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&adp5585 0 100000 0>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
default-brightness-level = <100>;
power-supply = <&reg_vdd_12v>;
enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
sound-wm8962 {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC",
"IN1R", "AMIC";
};
sound-xcvr {
compatible = "fsl,imx-audio-card";
model = "imx-audio-xcvr";
pri-dai-link {
link-name = "XCVR PCM";
cpu {
sound-dai = <&xcvr>;
};
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&cm33 {
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu1 0 1>,
<&mu1 1 1>,
<&mu1 3 1>;
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
status = "okay";
};
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
reg = <2>;
reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
phys = <&flexcan_phy>;
status = "okay";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
wm8962: codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX93_CLK_SAI3_GATE>;
DCVDD-supply = <&reg_audio_pwr>;
DBVDD-supply = <&reg_audio_pwr>;
AVDD-supply = <&reg_audio_pwr>;
CPVDD-supply = <&reg_audio_pwr>;
MICVDD-supply = <&reg_audio_pwr>;
PLLVDD-supply = <&reg_audio_pwr>;
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
inertial-meter@6a {
compatible = "st,lsm6dso";
reg = <0x6a>;
};
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6524>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
interrupt-parent = <&pcal6524>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <670000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1140000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <840000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
adp5585: io-expander@34 {
compatible = "adi,adp5585-00", "adi,adp5585";
reg = <0x34>;
vdd-supply = <&buck4>;
gpio-controller;
#gpio-cells = <2>;
gpio-reserved-ranges = <5 1>;
#pwm-cells = <3>;
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
adp5585_isp: io-expander@34 {
compatible = "adi,adp5585-01", "adi,adp5585";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <3>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
ptn5110_2: tcpc@51 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x51>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec2_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec2_dr_sw: endpoint {
remote-endpoint = <&usb2_drd_sw>;
};
};
};
};
};
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupt-parent = <&pcal6524>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};
&lpuart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&mu1 {
status = "okay";
};
&mu2 {
status = "okay";
};
&sai3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai3>;
pinctrl-1 = <&pinctrl_sai3_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI3>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb2_drd_sw: endpoint {
remote-endpoint = <&typec2_dr_sw>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
fsl,tuning-step = <1>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
fsl,tuning-step = <1>;
status = "okay";
no-mmc;
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&xcvr {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_spdif>;
pinctrl-1 = <&pinctrl_spdif_sleep>;
assigned-clocks = <&clk IMX93_CLK_SPDIF>,
<&clk IMX93_CLK_AUDIO_XCVR>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <12288000>, <200000000>;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e
MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
>;
};
pinctrl_sai3_sleep: sai3sleepgrp {
fsl,pins = <
MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e
MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e
MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e
MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e
MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e
MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e
>;
};
pinctrl_spdif_sleep: spdifsleepgrp {
fsl,pins = <
MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};

855
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@ -1,116 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 NXP
* Copyright 2022,2026 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx93.dtsi"
#include "imx93-11x11-evk-common.dtsi"
/ {
model = "NXP i.MX93 11X11 EVK board";
compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
};
chosen {
stdout-path = &lpuart1;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
vdev0vring0: vdev0vring0@a4000000 {
reg = <0 0xa4000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@a4008000 {
reg = <0 0xa4008000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@a4010000 {
reg = <0 0xa4010000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@a4018000 {
reg = <0 0xa4018000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@2021e000 {
reg = <0 0x2021e000 0 0x1000>;
no-map;
};
vdevbuffer: vdevbuffer@a4020000 {
compatible = "shared-dma-pool";
reg = <0 0xa4020000 0 0x100000>;
no-map;
};
};
flexcan_phy: can-phy {
compatible = "nxp,tja1057";
#phy-cells = <0>;
max-bitrate = <5000000>;
silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>;
};
reg_vdd_12v: regulator-vdd-12v {
compatible = "regulator-fixed";
regulator-name = "VDD_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
mmc2 = &usdhc3;
};
reg_m2_pwr: regulator-m2-pwr {
@ -122,18 +25,6 @@ reg_m2_pwr: regulator-m2-pwr {
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <12000>;
enable-active-high;
};
reg_usdhc3_vmmc: regulator-usdhc3 {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
@ -156,17 +47,6 @@ usdhc3_pwrseq: usdhc3_pwrseq {
reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&adp5585 0 100000 0>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
default-brightness-level = <100>;
power-supply = <&reg_vdd_12v>;
enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
bt_sco_codec: bt-sco-codec {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
@ -204,348 +84,6 @@ cpu {
};
};
};
sound-wm8962 {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC",
"IN1R", "AMIC";
};
sound-xcvr {
compatible = "fsl,imx-audio-card";
model = "imx-audio-xcvr";
pri-dai-link {
link-name = "XCVR PCM";
cpu {
sound-dai = <&xcvr>;
};
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&cm33 {
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu1 0 1>,
<&mu1 1 1>,
<&mu1 3 1>;
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
status = "okay";
};
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
};
&fec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
reg = <2>;
reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
realtek,clkout-disable;
};
};
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
phys = <&flexcan_phy>;
status = "okay";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
wm8962: codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX93_CLK_SAI3_GATE>;
DCVDD-supply = <&reg_audio_pwr>;
DBVDD-supply = <&reg_audio_pwr>;
AVDD-supply = <&reg_audio_pwr>;
CPVDD-supply = <&reg_audio_pwr>;
MICVDD-supply = <&reg_audio_pwr>;
PLLVDD-supply = <&reg_audio_pwr>;
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
inertial-meter@6a {
compatible = "st,lsm6dso";
reg = <0x6a>;
};
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6524>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
interrupt-parent = <&pcal6524>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <670000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1140000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <840000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
adp5585: io-expander@34 {
compatible = "adi,adp5585-00", "adi,adp5585";
reg = <0x34>;
vdd-supply = <&buck4>;
gpio-controller;
#gpio-cells = <2>;
gpio-reserved-ranges = <5 1>;
#pwm-cells = <3>;
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
adp5585_isp: io-expander@34 {
compatible = "adi,adp5585-01", "adi,adp5585";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <3>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
ptn5110_2: tcpc@51 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x51>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec2_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec2_dr_sw: endpoint {
remote-endpoint = <&usb2_drd_sw>;
};
};
};
};
};
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupt-parent = <&pcal6524>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};
&lpuart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&micfil {
@ -558,12 +96,12 @@ &micfil {
status = "okay";
};
&mu1 {
status = "okay";
};
&mu2 {
status = "okay";
&pcal6524 {
m2-pcm-level-shifter-hog {
gpio-hog;
gpios = <19 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&sai1 {
@ -577,76 +115,6 @@ &sai1 {
status = "okay";
};
&sai3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai3>;
pinctrl-1 = <&pinctrl_sai3_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI3>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb2_drd_sw: endpoint {
remote-endpoint = <&typec2_dr_sw>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
no-mmc;
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
@ -662,152 +130,7 @@ &usdhc3 {
status = "okay";
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&xcvr {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_spdif>;
pinctrl-1 = <&pinctrl_spdif_sleep>;
assigned-clocks = <&clk IMX93_CLK_SPDIF>,
<&clk IMX93_CLK_AUDIO_XCVR>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <12288000>, <200000000>;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX93_PAD_PDM_CLK__PDM_CLK 0x31e
@ -842,160 +165,6 @@ MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e
MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
>;
};
pinctrl_sai3_sleep: sai3sleepgrp {
fsl,pins = <
MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e
MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e
MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e
MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e
MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e
MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e
>;
};
pinctrl_spdif_sleep: spdifsleepgrp {
fsl,pins = <
MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
@ -1048,10 +217,4 @@ pinctrl_usdhc3_wlan: usdhc3wlangrp {
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};

50
arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso Normal file
View File

@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Overlay for Mayqueen (Open-EP Community) pixpaper display
* support on NXP FRDM i.MX 93 Development Board
*
* Copyright (C) 2026 Wig Cheng <onlywig@gmail.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx93-pinfunc.h"
/dts-v1/;
/plugin/;
&iomuxc {
pinctrl_epd_ctrl: epdctrlgrp {
fsl,pins = <
MX93_PAD_GPIO_IO05__GPIO2_IO05 0x31e /* DC pin */
MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e /* RESET pin */
MX93_PAD_GPIO_IO26__GPIO2_IO26 0x31e /* BUSY pin */
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe /* SPI3 CE0 */
MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe /* SPI3 MISO */
MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe /* SPI3 MOSI */
MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe /* SPI3 CLK */
>;
};
};
&lpspi3 {
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_lpspi3>, <&pinctrl_epd_ctrl>;
pinctrl-names = "default";
status = "okay";
display@0 {
compatible = "mayqueen,pixpaper";
reg = <0>;
busy-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
dc-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <1000000>;
};
};

12
arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts
View File

@ -25,6 +25,7 @@ aliases {
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
serial4 = &lpuart5;
};
bt_sco_codec: bt-sco-codec {
@ -400,6 +401,17 @@ &lpuart1 { /* console */
status = "okay";
};
&lpuart5 {
/* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&mu1 {
status = "okay";
};

110
arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso Normal file
View File

@ -0,0 +1,110 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx93-pinfunc.h"
&{/} {
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
};
panel {
compatible = "ontat,kd50g21-40nt-a1";
backlight = <&backlight>;
power-supply = <&reg_rpi_3v3>;
port {
panel_in: endpoint {
remote-endpoint = <&dpi_to_panel>;
};
};
};
};
&dpi_bridge {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dpi_to_panel: endpoint {
remote-endpoint = <&panel_in>;
bus-width = <18>;
};
};
};
};
&iomuxc {
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e
MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e
MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e
MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e
MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e
MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e
MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e
MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e
MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e
MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e
MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
>;
};
};
&lcdif {
status = "okay";
};
&media_blk_ctrl {
status = "okay";
};
&pcal6524 {
/*
* exp-sel-hog has property 'output-low' while DT overlay doesn't
* support /delete-property/. Both 'output-low' and 'output-high'
* will exist under hog nodes if DT overlay file sets 'output-high'.
* Workaround is to disable this hog and create new hog with
* 'output-high'.
*/
exp-sel-hog {
status = "disabled";
};
exp-high-sel-hog {
gpio-hog;
gpios = <22 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&sai3 {
/* disable due to GPIO12 and GPIO17~20 pin conflicts with LCDIF */
status = "disabled";
};

6
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@ -349,6 +349,12 @@ mic-can-sel-hog {
gpios = <17 GPIO_ACTIVE_HIGH>;
output-low;
};
m2-pcm-level-shifter-hog {
gpio-hog;
gpios = <19 GPIO_ACTIVE_HIGH>;
output-high;
};
};
pmic@25 {

12
arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
View File

@ -144,8 +144,11 @@ &flexcan1 {
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* RTC */
@ -277,6 +280,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
fsl,pins = <
MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e
MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e
>;
};
pinctrl_lpspi6: lpspi6grp {
fsl,pins = <
MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386

146
arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso Normal file
View File

@ -0,0 +1,146 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Copyright (C) 2025 Pengutronix
*
* Author: Andrej Picej <andrej.picej@norik.com>
* Author: Marco Felsch <kernel@pengutronix.de>
*/
#include <dt-bindings/clock/imx93-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx93-pinfunc.h"
/dts-v1/;
/plugin/;
&{/} {
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <5>;
power-supply = <&reg_vcc_3v3_con>;
pwms = <&pwm7 0 5000000 0>;
};
panel {
compatible = "edt,etm0700g0edh6";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel>;
backlight = <&backlight>;
enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_vcc_3v3_con>;
port {
panel_in: endpoint {
remote-endpoint = <&dpi_to_panel>;
};
};
};
/* TODO: Convert to FlexIO PWM once supported */
pwm7: pwm-7 {
compatible = "pwm-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
#pwm-cells = <3>;
};
reg_vcc_3v3_con: regulator-vcc-3v3-con {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_CON";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
};
};
&dpi_bridge {
status = "okay";
};
&dpi_to_panel {
remote-endpoint = <&panel_in>;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>;
assigned-clock-rates = <332600000>;
status = "okay";
};
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
interrupt-parent = <&gpio4>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
vcc-supply = <&reg_vcc_3v3_con>;
iovcc-supply = <&reg_vcc_3v3_con>;
touchscreen-size-x = <1792>;
touchscreen-size-y = <1024>;
wakeup-source;
};
};
&media_blk_ctrl {
status = "okay";
};
&iomuxc {
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x50e
MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x50e
MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x50e
MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x50e
MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x50e
MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x50e
MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x50e
MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x50e
MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x50e
MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x51e
MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x50e
MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x50e
MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x50e
MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x50e
MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x50e
MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x50e
MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x506
MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x506
MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x506
MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x506
MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x506
MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x506
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e
>;
};
pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x11e
MX93_PAD_ENET1_RD2__GPIO4_IO12 0x1133e
>;
};
};

12
arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
View File

@ -148,8 +148,11 @@ &flexcan1 {
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
/* Codec */
@ -262,6 +265,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
fsl,pins = <
MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e
MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e

12
arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
View File

@ -93,8 +93,11 @@ ethphy1: ethernet-phy@1 {
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@25 {
@ -234,6 +237,13 @@ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO28__GPIO2_IO28 0x31e
MX93_PAD_GPIO_IO29__GPIO2_IO29 0x31e
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e

56
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso Normal file
View File

@ -0,0 +1,56 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2023-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include <dt-bindings/clock/imx93-clock.h>
/dts-v1/;
/plugin/;
&backlight {
status = "okay";
};
&display {
compatible = "tianma,tm070jvhg33";
status = "okay";
};
&dpi_bridge {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgbdisp>;
status = "okay";
};
&dpi_to_panel {
remote-endpoint = <&lvds_encoder_input>;
};
&lcdif {
assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>;
assigned-clock-rates = <477400000>;
status = "okay";
};
&lvds_encoder {
status = "okay";
};
&lvds_encoder_input {
remote-endpoint = <&dpi_to_panel>;
};
&lvds_encoder_output {
remote-endpoint = <&panel_in>;
};
&media_blk_ctrl {
status = "okay";
};
&panel_in {
remote-endpoint = <&lvds_encoder_output>;
};

66
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso Normal file
View File

@ -0,0 +1,66 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2023-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Alexander Stein
*/
#include <dt-bindings/clock/imx93-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/;
/plugin/;
&backlight {
status = "okay";
};
&display {
compatible = "cdtech,s070swv29hg-dc44";
status = "okay";
};
&dpi_bridge {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgbdisp>;
status = "okay";
};
&dpi_to_panel {
remote-endpoint = <&panel_in>;
};
&lcdif {
assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>;
assigned-clock-rates = <333333333>;
status = "okay";
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
polytouch: touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupt-parent = <&gpio1>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&expander2 0 GPIO_ACTIVE_LOW>;
iovcc-supply = <&reg_3v3>;
vcc-supply = <&reg_3v3>;
gain = <20>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
};
&media_blk_ctrl {
status = "okay";
};
&panel_in {
remote-endpoint = <&dpi_to_panel>;
};

4
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts
View File

@ -232,7 +232,7 @@ ethphy_eqos: ethernet-phy@0 {
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@ -265,7 +265,7 @@ ethphy_fec: ethernet-phy@0 {
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;

4
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
View File

@ -242,7 +242,7 @@ ethphy_eqos: ethernet-phy@0 {
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@ -275,7 +275,7 @@ ethphy_fec: ethernet-phy@0 {
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;

35
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2025-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Martin Schmiedel
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/;
/plugin/;
&lpuart7 {
status = "okay";
bluetooth {
compatible = "brcm,bcm4329-bt";
vbat-supply = <&reg_3v3>;
vddio-supply = <&reg_3v3>;
shutdown-gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
};
};
&usdhc3 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf_sdio: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
};

598
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts Normal file
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@ -0,0 +1,598 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2025-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Martin Schmiedel
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "imx93-tqma9352.dtsi"
/{
model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA-MINI SBC";
compatible = "tq,imx93-tqma9352-mba93xxla-mini",
"tq,imx93-tqma9352", "fsl,imx93";
chassis-type = "embedded";
chosen {
stdout-path = &lpuart1;
};
aliases {
eeprom0 = &eeprom0;
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
rtc0 = &pcf85063;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
serial7 = &lpuart8;
spi0 = &lpspi1;
spi1 = &lpspi2;
spi2 = &lpspi3;
spi3 = &lpspi4;
spi4 = &lpspi5;
spi5 = &lpspi6;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v0_usb: regulator-5v0-usb {
compatible = "regulator-fixed";
regulator-name = "V_5V0_HUB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "V_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander0 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy_eqos: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_phy>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&expander0 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_fec>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy_fec: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
/* deactivated because pins are used for SDIO */
&flexspi1 {
status = "disabled";
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_m2_key_b>, <&pinctrl_m2_key_e>;
gpio-line-names =
/* 00 */ "", "", "M2_KEYE_ALERT#", "",
/* 04 */ "", "", "M2_KEYE_UART_WAKE#", "BM1_M2_KEYE_SDIO_WAKE#",
/* 08 */ "", "", "", "BM2_M2_KEYE_SDIO_RST#",
/* 12 */ "M2_KEYB_WOWWAN#", "BM3_M2_KEYB_PEWAKE#", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>;
gpio-line-names =
/* 00 */ "", "", "", "",
/* 04 */ "LVDS_RESET#", "LVDS_BLT_EN", "", "LVDS_PWR_EN",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "X1_9", "X1_19", "X1_15", "X1_11",
/* 20 */ "X1_13", "X1_7", "", "CAM_TRIGGER",
/* 24 */ "CAM_SYNC", "", "X1_5", "",
/* 28 */ "", "", "", "";
};
&gpio4 {
gpio-line-names =
/* 00 */ "", "", "", "",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "DSI_GPIO", "", "";
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
expander0: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
"M2_KEYE_PERST#", "M2_KEYB_PERST#",
"M2_KEYE_W_DISABLE1#", "M2_KEYE_W_DISABLE2#",
"M2_KEYA_W_DISABLE1#", "12V_EN";
};
expander1: gpio@71 {
compatible = "nxp,pca9538";
reg = <0x71>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "USB_HUB_PWR", "DSI_RST#",
"CAM_PWR#", "CAMRST#",
"M2_KEYB_FULL_CARD_PWR_OFF#", "M2_KEYB_W_DISABLE2#",
"M2_KEYB_RST#", "M2_KEYB_DPR";
/*
* Controls the LTE card FULL_CARD_PWR_OFF pin which is low active
* as power down signal. The output-low states, the signal
* is inactive, e.g. not power down
*/
full-card-power-off-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
output-low;
line-name = "M2_KEYB_FULL_CARD_PWR_OFF#";
};
/*
* Controls the LTE card reset pin which is low active
* as reset signal. The output-low states, the signal
* is inactive, e.g. not in reset
*/
wlan-perst-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "M2_KEYB_RST#";
};
};
};
&lpspi6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>;
cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* disabled per default, console for M33 */
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
/* disabled per default, used for bluetooth on M.2 slot */
&lpuart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
uart-has-rtscts;
status = "disabled";
};
&lpuart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
status = "okay";
};
&pcf85063 {
/* RTC_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcf85063>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
};
&tpm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm5>;
};
&usbotg1 {
disable-over-current;
dr_mode = "peripheral";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhub>;
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
dr_mode = "host";
vbus-supply = <&reg_5v0_usb>;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
hub_2_0: usb-hub@1 {
compatible = "usb424,2517";
reg = <1>;
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_3v3>;
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
disable-wp;
no-sdio;
no-mmc;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
non-removable;
vmmc-supply = <&reg_3v3>;
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = /* PD | FSEL_2 | DSE X4 */
<MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e>,
/* SION | HYS | FSEL_2 | DSE X4 */
<MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e>,
/* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000>,
<MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000>,
<MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000>,
<MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000>,
<MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000>,
/* HYS | PD | FSEL_0 | DSE no drive */
<MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x1400>,
/* PD | FSEL_2 | DSE X5 */
<MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e>,
<MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e>,
<MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e>,
<MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e>,
<MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e>,
/* PD | FSEL_3 | DSE X4 */
<MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x59e>;
};
pinctrl_eqos_phy: eqosphygrp {
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1000>;
};
pinctrl_fec: fecgrp {
fsl,pins = /* PD | FSEL_2 | DSE X4 */
<MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e>,
/* SION | HYS | FSEL_2 | DSE X4 */
<MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e>,
/* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000>,
<MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000>,
<MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x1000>,
<MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x1000>,
<MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x1000>,
/* HYS | PD | FSEL_0 | DSE no drive */
<MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x1400>,
/* PD | FSEL_2 | DSE X5 */
<MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x53e>,
<MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x53e>,
<MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x53e>,
<MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x53e>,
<MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x53e>,
/* PD | FSEL_3 | DSE X4 */
<MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x59e>;
};
pinctrl_fec_phy: fecphygrp {
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
<MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1000>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */
<MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200>,
/* PU | FSEL_3 | DSE X4 */
<MX93_PAD_PDM_CLK__CAN1_TX 0x039e>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */
<MX93_PAD_GPIO_IO27__CAN2_RX 0x1200>,
/* PU | FSEL_3 | DSE X4 */
<MX93_PAD_GPIO_IO25__CAN2_TX 0x039e>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO16__GPIO2_IO16 0x151e>,
<MX93_PAD_GPIO_IO17__GPIO2_IO17 0x151e>,
<MX93_PAD_GPIO_IO18__GPIO2_IO18 0x151e>,
<MX93_PAD_GPIO_IO19__GPIO2_IO19 0x151e>,
<MX93_PAD_GPIO_IO20__GPIO2_IO20 0x151e>,
<MX93_PAD_GPIO_IO21__GPIO2_IO21 0x151e>,
<MX93_PAD_GPIO_IO26__GPIO2_IO26 0x151e>;
};
pinctrl_jtag: jtaggrp {
fsl,pins = <MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e>,
<MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200>,
<MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e>,
<MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */
<MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e>,
<MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e>;
};
pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {
fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */
<MX93_PAD_GPIO_IO28__GPIO2_IO28 0x4000199e>,
<MX93_PAD_GPIO_IO29__GPIO2_IO29 0x4000199e>;
};
pinctrl_lpspi6: lpspi6grp {
fsl,pins = /* HYS | PD | FSEL_0 | DSE no drive */
<MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x1400>,
/* PD | FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e>,
<MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x051e>;
};
pinctrl_lpspi6_cs: lpspi6csgrp {
fsl,pins = /* FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO00__GPIO2_IO00 0x011e>;
};
pinctrl_m2_key_b: m2keybgrp {
fsl,pins = <MX93_PAD_SAI1_TXC__GPIO1_IO12 0x00001000>,
<MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x00001000>;
};
pinctrl_m2_key_e: m2keyegrp {
fsl,pins = <MX93_PAD_I2C2_SCL__GPIO1_IO02 0x00001000>,
<MX93_PAD_UART2_RXD__GPIO1_IO06 0x00001000>,
<MX93_PAD_UART2_TXD__GPIO1_IO07 0x00001000>,
<MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x00001000>;
};
/*CAM_MCLK, DSI_GPIO, CAM_TRIGGER, CAM_SYNC*/
pinctrl_mipi_csi_dsi: mipi_csi_dsigrp {
fsl,pins = <MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0000011e>,
<MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0000011e>,
<MX93_PAD_GPIO_IO23__GPIO2_IO23 0x0000011e>,
<MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0000111e>;
};
pinctrl_pcf85063: pcf85063grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000>;
};
pinctrl_tpm5: tpm5grp {
fsl,pins = <MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e>;
};
pinctrl_uart1: uart1grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_UART1_RXD__LPUART1_RX 0x1000>,
/* FSEL_2 | DSE X4 */
<MX93_PAD_UART1_TXD__LPUART1_TX 0x011e>;
};
pinctrl_uart3: uart3grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_GPIO_IO15__LPUART3_RX 0x1000>,
/* FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO14__LPUART3_TX 0x011e>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <MX93_PAD_GPIO_IO08__LPUART7_TX 0x031e>,
<MX93_PAD_GPIO_IO09__LPUART7_RX 0x031e>,
<MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x031e>,
<MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x031e>;
};
pinctrl_uart8: uart8grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_GPIO_IO13__LPUART8_RX 0x1000>,
/* FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO12__LPUART8_TX 0x011e>;
};
pinctrl_usbhub: usbhubgrp {
fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */
<MX93_PAD_GPIO_IO22__GPIO2_IO22 0x151e>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX93_PAD_SD2_CD_B__GPIO3_IO00 0x1000>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_hs: usdhc2hsgrp {
fsl,pins = /* PD | FSEL_3 | DSE X5 */
<MX93_PAD_SD2_CLK__USDHC2_CLK 0x05be>,
/* HYS | PU | FSEL_3 | DSE X4 */
<MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
/* HYS | PU | FSEL_3 | DSE X3 */
<MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e>,
<MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e>,
<MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e>,
<MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e>,
/* FSEL_2 | DSE X3 */
<MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_uhs: usdhc2uhsgrp {
fsl,pins = /* PD | FSEL_3 | DSE X6 */
<MX93_PAD_SD2_CLK__USDHC2_CLK 0x05fe>,
/* HYS | PU | FSEL_3 | DSE X4 */
<MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
<MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e>,
<MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e>,
<MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e>,
<MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e>,
/* FSEL_2 | DSE X3 */
<MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc3: usdhc3grp {
fsl,pins = /* PD | FSEL_3 | DSE X6 */
<MX93_PAD_SD3_CLK__USDHC3_CLK 0x05fe>,
/* HYS | PU | FSEL_3 | DSE X4 */
<MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000139e>,
<MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000139e>,
<MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000139e>,
<MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000139e>,
<MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000139e>;
};
};

4
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -172,7 +172,7 @@ ethphy_eqos: ethernet-phy@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_phy>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
@ -205,7 +205,7 @@ ethphy_fec: ethernet-phy@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;

36
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@ -43,6 +43,30 @@ map0 {
};
};
};
soc@0 {
npu@4a900000 {
compatible = "fsl,imx93-npu", "arm,ethos-u65";
reg = <0x4a900000 0x1000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mlmix>;
clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
clock-names = "core", "apb";
sram = <&sram>;
assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>,
<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <800000000>, <133000000>;
};
};
sram: sram@20480000 {
compatible = "mmio-sram";
reg = <0x0 0x20480000 0x0 0x18000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x20480000 0x18000>;
};
};
&aips1 {
@ -150,6 +174,18 @@ l3_cache: l3-cache {
};
};
&lcdif {
port {
lcdif_to_ldb: endpoint@1 {
reg = <1>;
};
lcdif_to_dsi: endpoint@2 {
reg = <2>;
};
};
};
&src {
mlmix: power-domain@44461800 {
compatible = "fsl,imx93-src-slice";

28
arch/arm64/boot/dts/freescale/imx93w-evk.dts Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
/dts-v1/;
#include "imx93w.dtsi"
#include "imx93-11x11-evk-common.dtsi"
/ {
model = "NXP i.MX93W EVK board";
compatible = "fsl,imx93-wireless-evk", "fsl,imx93";
};
&lpi2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
};
&iomuxc {
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e
>;
};
};

110
arch/arm64/boot/dts/freescale/imx93w.dtsi Normal file
View File

@ -0,0 +1,110 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
#include "imx93.dtsi"
/ {
aliases {
mmc2 = &usdhc3;
};
reg_usdhc3_vmmc: regulator-usdhc3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc3_vmmc>;
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_pwrseq>;
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>;
mmc-pwrseq = <&usdhc3_pwrseq>;
vmmc-supply = <&reg_usdhc3_vmmc>;
bus-width = <4>;
keep-power-in-suspend;
non-removable;
wakeup-source;
status = "okay";
};
&iomuxc {
pinctrl_reg_usdhc3_vmmc: regusdhc3vmmcgrp {
fsl,pins = <
/*
* Enable open drain and internal pull-up to allow the IW610 JTAG
* connector to control the PDn status.
*/
MX93_PAD_GPIO_IO29__GPIO2_IO29 0xb9e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe
>;
};
pinctrl_usdhc3_sleep: usdhc3grpsleepgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp {
fsl,pins = <
MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x39e
>;
};
};

12
arch/arm64/boot/dts/freescale/imx94-pinfunc.h
View File

@ -233,6 +233,7 @@
#define IMX94_PAD_GPIO_IO17__GPT_MUX_INOUT3 0x0054 0x0358 0x0704 0x05 0x01
#define IMX94_PAD_GPIO_IO17__FLEXPWM4_PWMB0 0x0054 0x0358 0x06e4 0x06 0x00
#define IMX94_PAD_GPIO_IO17__XBAR1_XBAR_INOUT31 0x0054 0x0358 0x08b4 0x07 0x00
#define IMX94_PAD_GPIO_IO17__XSPI1_IPP_IND_INTFA_B 0x0054 0x0358 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x035c 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO18__LPI2C4_SDA 0x0058 0x035c 0x0738 0x01 0x00
@ -242,6 +243,7 @@
#define IMX94_PAD_GPIO_IO18__GPT_MUX_INOUT6 0x0058 0x035c 0x0710 0x05 0x01
#define IMX94_PAD_GPIO_IO18__FLEXPWM4_PWMA1 0x0058 0x035c 0x06d8 0x06 0x00
#define IMX94_PAD_GPIO_IO18__XBAR1_XBAR_INOUT32 0x0058 0x035c 0x08b8 0x07 0x00
#define IMX94_PAD_GPIO_IO18__USB1_OTG_OC 0x0058 0x035c 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x0360 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO19__LPI2C4_SCL 0x005c 0x0360 0x0734 0x01 0x00
@ -251,6 +253,7 @@
#define IMX94_PAD_GPIO_IO19__GPT_MUX_INOUT9 0x005c 0x0360 0x071c 0x05 0x01
#define IMX94_PAD_GPIO_IO19__FLEXPWM4_PWMB1 0x005c 0x0360 0x06e8 0x06 0x00
#define IMX94_PAD_GPIO_IO19__XBAR1_XBAR_INOUT33 0x005c 0x0360 0x08bc 0x07 0x00
#define IMX94_PAD_GPIO_IO19__USB2_OTG_OC 0x005c 0x0360 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0364 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x0060 0x0364 0x0000 0x01 0x00
@ -413,6 +416,7 @@
#define IMX94_PAD_GPIO_IO37__FLEXPWM3_PWMB2 0x00a4 0x03a8 0x06c0 0x05 0x00
#define IMX94_PAD_GPIO_IO37__FLEXPWM2_PWMX1 0x00a4 0x03a8 0x06a4 0x06 0x00
#define IMX94_PAD_GPIO_IO37__XBAR1_XBAR_INOUT13 0x00a4 0x03a8 0x0890 0x07 0x00
#define IMX94_PAD_GPIO_IO37__XSPI1_IPP_IND_INTFA_B 0x00a4 0x03a8 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO38__GPIO3_IO6 0x00a8 0x03ac 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO38__NETC_1588MUX_INOUT0 0x00a8 0x03ac 0x064c 0x01 0x00
@ -574,6 +578,7 @@
#define IMX94_PAD_GPIO_IO55__TPM4_CH3 0x00ec 0x03f0 0x083c 0x05 0x01
#define IMX94_PAD_GPIO_IO55__SINC3_EMBIT0 0x00ec 0x03f0 0x0000 0x06 0x00
#define IMX94_PAD_GPIO_IO55__XBAR1_XBAR_INOUT19 0x00ec 0x03f0 0x08a8 0x07 0x00
#define IMX94_PAD_GPIO_IO55__XSPI1_IPP_IND_INTFA_B 0x00ec 0x03f0 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO56__GPIO3_IO24 0x00f0 0x03f4 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO56__NETC_1588MUX_INOUT6 0x00f0 0x03f4 0x0664 0x01 0x00
@ -592,6 +597,8 @@
#define IMX94_PAD_GPIO_IO57__TPM6_CH3 0x00f4 0x03f8 0x084c 0x05 0x01
#define IMX94_PAD_GPIO_IO57__SINC3_EMBIT1 0x00f4 0x03f8 0x0000 0x06 0x00
#define IMX94_PAD_GPIO_IO57__ENET_REF_CLK_ROOT 0x00f4 0x03f8 0x0000 0x07 0x00
#define IMX94_PAD_GPIO_IO57__XBAR1_XBAR_INOUT21 0x00f4 0x03f8 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO57__SAI3_RX_SYNC 0x00f4 0x03f8 0x0000 0x0200 0x00
#define IMX94_PAD_CCM_CLKO1__CLKO_1 0x00f8 0x03fc 0x0000 0x00 0x00
#define IMX94_PAD_CCM_CLKO1__NETC_1588MUX_INOUT8 0x00f8 0x03fc 0x066c 0x01 0x00
@ -619,6 +626,7 @@
#define IMX94_PAD_CCM_CLKO3__GPIO4_IO2 0x0100 0x0404 0x0000 0x05 0x00
#define IMX94_PAD_CCM_CLKO3__SINC3_EMCLK3 0x0100 0x0404 0x0000 0x06 0x00
#define IMX94_PAD_CCM_CLKO3__ENET_REF_CLK_ROOT 0x0100 0x0404 0x0000 0x07 0x00
#define IMX94_PAD_CCM_CLKO3__XBAR1_XBAR_INOUT24 0x0100 0x0404 0x0000 0x0105 0x00
#define IMX94_PAD_CCM_CLKO4__CLKO_4 0x0104 0x0408 0x0000 0x00 0x00
#define IMX94_PAD_CCM_CLKO4__NETC_1588MUX_INOUT11 0x0104 0x0408 0x0000 0x01 0x00
@ -872,6 +880,7 @@
#define IMX94_PAD_ETH4_MDIO_GPIO2__GPIO6_IO29 0x017c 0x0480 0x0000 0x05 0x00
#define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXPWM4_PWMX1 0x017c 0x0480 0x06f8 0x06 0x02
#define IMX94_PAD_ETH4_MDIO_GPIO2__SINC_FILTER_GLUE4_BREAK 0x017c 0x0480 0x0000 0x07 0x00
#define IMX94_PAD_ETH4_MDIO_GPIO2__XSPI2_IPP_IND_INTFA_B 0x017c 0x0480 0x0000 0x0105 0x00
#define IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x0180 0x0484 0x0648 0x00 0x00
#define IMX94_PAD_ETH4_TX_CLK__USDHC3_CLK 0x0180 0x0484 0x0000 0x01 0x00
@ -917,6 +926,7 @@
#define IMX94_PAD_ETH4_TXD2__GPIO7_IO2 0x0190 0x0494 0x0000 0x05 0x00
#define IMX94_PAD_ETH4_TXD2__FLEXPWM4_PWMA2 0x0190 0x0494 0x06dc 0x06 0x01
#define IMX94_PAD_ETH4_TXD2__ETH4_RMII_REF50_CLK 0x0190 0x0494 0x0000 0x07 0x00
#define IMX94_PAD_ETH4_TXD2__XBAR1_XBAR_INOUT34 0x0190 0x0494 0x0000 0x0105 0x00
#define IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x0194 0x0498 0x0000 0x00 0x00
#define IMX94_PAD_ETH4_TXD3__USDHC3_DATA3 0x0194 0x0498 0x0868 0x01 0x01
@ -965,6 +975,7 @@
#define IMX94_PAD_ETH4_RX_CTL__GPIO7_IO8 0x01a8 0x04ac 0x0000 0x05 0x00
#define IMX94_PAD_ETH4_RX_CTL__DIG_ENCODER2_DATA_OUT 0x01a8 0x04ac 0x0000 0x06 0x00
#define IMX94_PAD_ETH4_RX_CTL__XBAR1_XBAR_INOUT6 0x01a8 0x04ac 0x0874 0x07 0x01
#define IMX94_PAD_ETH4_RX_CTL__XSPI2_IPP_IND_INTFA_B 0x01a8 0x04ac 0x0000 0x0105 0x00
#define IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x01ac 0x04b0 0x0630 0x00 0x00
#define IMX94_PAD_ETH4_RX_CLK__XSPI2_A_DQS 0x01ac 0x04b0 0x0000 0x02 0x00
@ -1344,6 +1355,7 @@
#define IMX94_PAD_XSPI1_SS1_B__GPIO7_IO27 0x028c 0x0590 0x0000 0x05 0x00
#define IMX94_PAD_XSPI1_SS1_B__SINC1_MOD_CLK0 0x028c 0x0590 0x0000 0x06 0x00
#define IMX94_PAD_XSPI1_SS1_B__SINC_FILTER_GLUE1_BREAK 0x028c 0x0590 0x0000 0x07 0x00
#define IMX94_PAD_XSPI1_SS1_B__XSPI1_IPP_IND_INTFA_B 0x028c 0x0590 0x0000 0x0105 0x00
#define IMX94_PAD_SD2_CD_B__USDHC2_CD_B 0x0290 0x0594 0x0000 0x00 0x00
#define IMX94_PAD_SD2_CD_B__NETC_PINMUX_ETH4_RX_CTL 0x0290 0x0594 0x0634 0x01 0x01

127
arch/arm64/boot/dts/freescale/imx94.dtsi
View File

@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx94-clock.h"
#include "imx94-pinfunc.h"
@ -94,14 +95,27 @@ scmi_clk: protocol@14 {
#clock-cells = <1>;
};
scmi_sensor: protocol@15 {
reg = <0x15>;
#thermal-sensor-cells = <1>;
};
scmi_iomuxc: protocol@19 {
reg = <0x19>;
};
scmi_lmm: protocol@80 {
reg = <0x80>;
};
scmi_bbm: protocol@81 {
reg = <0x81>;
};
scmi_cpu: protocol@82 {
reg = <0x82>;
};
scmi_misc: protocol@84 {
reg = <0x84>;
};
@ -120,7 +134,7 @@ mqs2: mqs2 {
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@ -130,15 +144,22 @@ psci {
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
interrupt-parent = <&gic>;
arm,no-tick-in-suspend;
};
usbphynop: usbphynop {
compatible = "usb-nop-xceiv";
clocks = <&scmi_clk IMX94_CLK_HSIO>;
clock-names = "main_clk";
#phy-cells = <0>;
};
gic: interrupt-controller@48000000 {
compatible = "arm,gic-v3";
reg = <0 0x48000000 0 0x10000>,
@ -1205,6 +1226,48 @@ a55_irqsteer: interrupt-controller@446a0000 {
};
};
mailbox@47300000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47300000 0x0 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47310000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47310000 0x0 0x10000>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47330000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47330000 0x0 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47340000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47340000 0x0 0x10000>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47350000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47350000 0x0 0x10000>;
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47550000 {
compatible = "fsl,imx95-mu-ele";
reg = <0x0 0x47550000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
aips4: bus@49000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x0 0x49000000 0x0 0x800000>;
@ -1223,6 +1286,60 @@ wdog3: watchdog@49220000 {
};
};
usb3: usb@4c100000 {
compatible = "nxp,imx94-dwc3", "nxp,imx8mp-dwc3";
reg = <0x0 0x4c100000 0x0 0x10000>,
<0x0 0x4c010010 0x0 0x04>,
<0x0 0x4c1f0000 0x0 0x20>;
reg-names = "core", "blkctl", "glue";
clocks = <&scmi_clk IMX94_CLK_HSIO>,
<&scmi_clk IMX94_CLK_HSIO>,
<&scmi_clk IMX94_CLK_24M>,
<&scmi_clk IMX94_CLK_32K>;
clock-names = "hsio", "bus_early", "ref", "suspend";
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dwc_usb3", "wakeup";
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
phys = <&usb3_phy>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,gfladj-refclk-lpm-sel-quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
usb3_phy: phy@4c1f0040 {
compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";
reg = <0x0 0x4c1f0040 0x0 0x40>,
<0x0 0x4c1fc000 0x0 0x100>;
clocks = <&scmi_clk IMX94_CLK_HSIO>;
clock-names = "phy";
#phy-cells = <0>;
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
status = "disabled";
};
usb2: usb@4c200000 {
compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x0 0x4c200000 0x0 0x200>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX94_CLK_HSIO>,
<&scmi_clk IMX94_CLK_32K>;
clock-names = "usb_ctrl_root", "usb_wakeup";
power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
phys = <&usbphynop>;
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
usbmisc: usbmisc@4c200200 {
compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x0 0x4c200200 0x0 0x200>,
<0x0 0x4c010014 0x0 0x04>;
#index-cells = <1>;
};
netc_blk_ctrl: system-controller@4ceb0000 {
compatible = "nxp,imx94-netc-blk-ctrl";
reg = <0x0 0x4ceb0000 0x0 0x10000>,

292
arch/arm64/boot/dts/freescale/imx943-evk.dts
View File

@ -6,6 +6,14 @@
/dts-v1/;
#include "imx943.dtsi"
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/pwm/pwm.h>
#define BRD_SM_CTRL_BT_WAKE 0x8000 /*!< PCAL6416A-3 */
#define BRD_SM_CTRL_SD3_WAKE 0x8001 /*!< PCAL6416A-4 */
#define BRD_SM_CTRL_PCIE1_WAKE 0x8002 /*!< PCAL6416A-5 */
#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6416A-6 */
#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6416A-7 */
/ {
compatible = "fsl,imx943-evk", "fsl,imx94";
@ -20,7 +28,9 @@ aliases {
i2c5 = &lpi2c6;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &lpuart1;
serial5 = &lpuart6;
};
bt_sco_codec: bt-sco-codec {
@ -53,6 +63,32 @@ dmic: dmic {
#sound-dai-cells = <0>;
};
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-name = "M.2-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pcal6416_i2c3_u46 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
/*
* M.2 device only can be enabled(W_DISABLE1#) after all Power
* Rails reach their minimum operating voltage (PCI Express M.2
* Specification r5.1 3.1.4 Power-up Timing).
* Set a delay equal to the max value of Tsettle here.
*/
startup-delay-us = <5000>;
};
reg_m2_wlan: regulator-wlan {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_m2_pwr>;
gpio = <&pcal6416_i2c3_u46 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
@ -140,6 +176,11 @@ sound-wm8962 {
model = "wm8962-audio";
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6416_i2c3_u46 4 GPIO_ACTIVE_LOW>;
};
memory@80000000 {
reg = <0x0 0x80000000 0x0 0x80000000>;
device_type = "memory";
@ -197,6 +238,48 @@ pca9670_i2c3: gpio@23 {
gpio-controller;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
typec_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <0>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec_con_hs: endpoint {
remote-endpoint = <&usb3_data_hs>;
};
};
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
pca9548_i2c3: i2c-mux@77 {
compatible = "nxp,pca9548";
reg = <0x77>;
@ -253,6 +336,28 @@ wm8962: codec@1a {
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
};
fan_controller: pwm@2f {
compatible = "microchip,emc2301", "microchip,emc2305";
reg = <0x2f>;
#pwm-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
fan0: fan@0 {
reg = <0x0>;
pwms = <&fan_controller 26000 1 PWM_POLARITY_INVERTED>;
#cooling-cells = <2>;
};
};
ptn5150: tcpc@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&pcal6408_i2c3_u172>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
status = "disabled";
};
};
i2c@5 {
@ -437,6 +542,17 @@ &lpuart1 {
status = "okay";
};
&lpuart6 {
/* BT */
pinctrl-0 = <&pinctrl_uart6>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&micfil {
assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>,
@ -636,6 +752,12 @@ IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0 0x31e
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
IMX94_PAD_GPIO_IO44__GPIO3_IO12 0x30e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e
@ -643,6 +765,15 @@ IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
IMX94_PAD_GPIO_IO04__LPUART6_TX 0x31e
IMX94_PAD_GPIO_IO05__LPUART6_RX 0x31e
IMX94_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e
IMX94_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e
@ -739,6 +870,18 @@ IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
IMX94_PAD_GPIO_IO48__USDHC3_CLK 0x158e
/* Need to config the SION for CMD pad, refer to ERR053138 */
IMX94_PAD_GPIO_IO49__USDHC3_CMD 0x4000138e
IMX94_PAD_GPIO_IO50__USDHC3_DATA0 0x138e
IMX94_PAD_GPIO_IO51__USDHC3_DATA1 0x138e
IMX94_PAD_GPIO_IO52__USDHC3_DATA2 0x138e
IMX94_PAD_GPIO_IO53__USDHC3_DATA3 0x138e
>;
};
pinctrl_xspi1: xspi1grp {
fsl,pins = <
IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe
@ -756,6 +899,138 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe
};
};
&scmi_misc {
nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1
BRD_SM_CTRL_PCIE1_WAKE 1
BRD_SM_CTRL_BT_WAKE 1
BRD_SM_CTRL_PCIE2_WAKE 1
BRD_SM_CTRL_BUTTON 1>;
};
&thermal_zones {
a55-thermal {
trips {
atrip2: trip2 {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
atrip3: trip3 {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
atrip4: trip4 {
temperature = <75000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&atrip2>;
cooling-device = <&fan0 4 6>;
};
map2 {
trip = <&atrip3>;
cooling-device = <&fan0 6 8>;
};
map3 {
trip = <&atrip4>;
cooling-device = <&fan0 8 10>;
};
};
};
pf09-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&scmi_sensor 2>;
trips {
pf09_alert: trip0 {
temperature = <140000>;
hysteresis = <2000>;
type = "passive";
};
pf09_crit: trip1 {
temperature = <155000>;
hysteresis = <2000>;
type = "critical";
};
};
};
pf53soc-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&scmi_sensor 3>;
trips {
pf5302_alert: trip0 {
temperature = <140000>;
hysteresis = <2000>;
type = "passive";
};
pf5302_crit: trip1 {
temperature = <155000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
&usb2 {
dr_mode = "otg";
disable-over-current;
adp-disable;
hnp-disable;
srp-disable;
samsung,picophy-dc-vol-level-adjust = <10>;
status = "okay";
};
&usb3 {
dr_mode = "otg";
adp-disable;
hnp-disable;
srp-disable;
usb-role-switch;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_data_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usb3_phy {
orientation-switch;
fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>;
fsl,phy-pcs-tx-swing-full-percent = <100>;
fsl,phy-tx-preemp-amp-tune-microamp = <600>;
fsl,phy-tx-vboost-level-microvolt = <1156>;
fsl,phy-tx-vref-tune-percent = <100>;
status = "okay";
port {
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
&usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@ -781,6 +1056,23 @@ &usdhc2 {
status = "okay";
};
&usdhc3 {
/*
* Only enable SDIO2.0 mode as the corresponding GPIO pads are 3.3V, the
* max frequency is 50MHz.
*/
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3>;
pinctrl-names = "default", "sleep";
bus-width = <4>;
vmmc-supply = <&reg_m2_wlan>;
mmc-pwrseq = <&usdhc3_pwrseq>;
keep-power-in-suspend;
non-removable;
wakeup-source;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";

64
arch/arm64/boot/dts/freescale/imx943.dtsi
View File

@ -145,4 +145,68 @@ l3_cache: l3-cache {
cache-unified;
};
};
thermal_zones: thermal-zones {
a55-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&scmi_sensor 1>;
trips {
cpu_alert0: trip0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
ana-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&scmi_sensor 0>;
trips {
ana_alert: trip0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
ana_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&ana_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};

1
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
View File

@ -116,7 +116,6 @@ flexcan2_phy: can-phy {
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "M.2-power";

73
arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
View File

@ -243,6 +243,12 @@ codec {
};
};
sound-mqs {
compatible = "audio-graph-card2";
links = <&sai1_port1>;
label = "mqs-audio";
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>;
@ -473,6 +479,21 @@ &mu7 {
status = "okay";
};
&mqs1 {
clocks = <&scmi_clk IMX95_CLK_SAI1>;
clock-names = "mclk";
pinctrl-0 = <&pinctrl_mqs1>;
pinctrl-names = "default";
status = "okay";
mqs1_port: port {
mqs1_ep: endpoint {
dai-format = "left_j";
remote-endpoint = <&sai1_port1_ep>;
};
};
};
&netc_blk_ctrl {
status = "okay";
};
@ -534,6 +555,51 @@ &pcie0 {
status = "okay";
};
&sai1 {
clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>,
<&scmi_clk IMX95_CLK_SAI1>, <&dummy>,
<&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI1>;
assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>,
<24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* leave unconnected - no RX in the context of MQS */
port@0 {
reg = <0>;
endpoint {
};
};
sai1_port1: port@1 {
reg = <1>;
mclk-fs = <512>;
sai1_port1_ep: endpoint {
dai-format = "left_j";
system-clock-direction-out;
bitclock-master;
frame-master;
remote-endpoint = <&mqs1_ep>;
};
};
};
};
&scmi_iomuxc {
pinctrl_emdio: emdiogrp {
fsl,pins = <
@ -618,6 +684,13 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
>;
};
pinctrl_mqs1: mqs1grp {
fsl,pins = <
IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x31e
IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x31e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e

7
arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts
View File

@ -55,8 +55,11 @@ sound-wm8962 {
};
&edma2 {
/* channels 30 and 31 reserved for FW usage */
dma-channel-mask = <0xc0000000>, <0x0>;
/*
* channels 0 and 1 reserved for V2X fast hash,
* channels 30 and 31 reserved for FW usage
*/
dma-channel-mask = <0xc0000003>, <0x0>;
};
&sai3 {

2
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -475,7 +475,7 @@ &lpuart1 {
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "disabled";
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";

49
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
View File

@ -144,6 +144,14 @@ reg_wifi_en: regulator-wifi-en {
startup-delay-us = <2000>;
};
remoteproc-cm7 {
compatible = "fsl,imx95-cm7";
mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>;
mbox-names = "tx", "rx", "rxdb";
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -156,6 +164,42 @@ linux_cma: linux,cma {
alloc-ranges = <0 0x80000000 0 0x7f000000>;
linux,cma-default;
};
m7_reserved: memory@80000000 {
reg = <0 0x80000000 0 0x1000000>;
no-map;
};
rsc_table: rsc-table@88220000 {
reg = <0 0x88220000 0 0x1000>;
no-map;
};
vdev0vring0: vdev0vring0@88000000 {
reg = <0 0x88000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@88008000 {
reg = <0 0x88008000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@88010000 {
reg = <0 0x88010000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@88018000 {
reg = <0 0x88018000 0 0x8000>;
no-map;
};
vdevbuffer: vdevbuffer@88020000 {
compatible = "shared-dma-pool";
reg = <0 0x88020000 0 0x100000>;
no-map;
};
};
};
@ -262,7 +306,6 @@ &gpio3 {
"",
"",
"",
"",
"PMIC_SD2_VSEL";
status = "okay";
};
@ -572,6 +615,10 @@ &lpuart3 {
pinctrl-0 = <&pinctrl_uart3>;
};
&mu7 {
status = "okay";
};
/* SMARC MDIO, shared between all ethernet ports */
&netc_emdio {
pinctrl-names = "default";

595
arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts Normal file
View File

@ -0,0 +1,595 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Variscite Sonata carrier board for DART-MX95
*
* Link: https://variscite.com/carrier-boards/sonata-board/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
#include "imx95-var-dart.dtsi"
/ {
model = "Variscite DART-MX95 on Sonata-Board";
compatible = "variscite,var-dart-mx95-sonata",
"variscite,var-dart-mx95",
"fsl,imx95";
aliases {
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port1;
ethernet2 = &enetc_port2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
clk_osc_can0: clock-osc-40m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
typec_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <0>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec_con_hs: endpoint {
remote-endpoint = <&usb3_data_hs>;
};
};
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
button-back {
gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
label = "Back";
wakeup-source;
linux,code = <KEY_BACK>;
};
button-down {
gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
label = "Down";
wakeup-source;
linux,code = <KEY_DOWN>;
};
button-home {
gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
label = "Home";
wakeup-source;
linux,code = <KEY_HOME>;
};
button-up {
gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
label = "Up";
wakeup-source;
linux,code = <KEY_UP>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-heartbeat {
label = "Heartbeat";
gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_phy1_supply: regulator-phy1 {
compatible = "regulator-fixed";
regulator-name = "SUPPLY_PHY1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VDD_SD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <12000>;
};
sfp0: sfp {
compatible = "sff,sfp";
i2c-bus = <&lpi2c3>;
los-gpios = <&pca9534 1 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
};
&enetc_port1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc1>;
phy-handle = <&ethphy1>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
status = "okay";
};
&enetc_port2 {
phy-mode = "10gbase-r";
sfp = <&sfp0>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca9534: gpio@22 {
compatible = "nxp,pca9534";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
pcie2-sel-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "pcie-clk-sw";
};
sfp-sel-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "sfp-sw";
};
};
/* Capacitive touch controller */
ft5x06_ts: touchscreen@38 {
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_captouch>;
reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio5>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
wakeup-source;
};
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
interrupt-parent = <&gpio5>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
port {
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
};
/* DS1337 RTC module */
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio5>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c4>;
pinctrl-1 = <&pinctrl_lpi2c4>;
status = "okay";
};
&lpi2c8 {
pca6408_1: gpio@20 {
compatible = "nxp,pcal6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
pca6408_2: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
st33ktpm2xi2c: tpm@2e {
compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
reg = <0x2e>;
};
};
&lpspi7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi7>;
cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
status = "okay";
/* Resistive touch controller */
ads7846: touchscreen@0 {
compatible = "ti,ads7846";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_restouch>;
interrupt-parent = <&gpio2>;
interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
pendown-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
spi-max-frequency = <1500000>;
wakeup-source;
ti,x-min = /bits/ 16 <125>;
ti,x-max = /bits/ 16 <4008>;
ti,y-min = /bits/ 16 <282>;
ti,y-max = /bits/ 16 <3864>;
ti,x-plate-ohms = /bits/ 16 <180>;
ti,pressure-max = /bits/ 16 <255>;
ti,debounce-max = /bits/ 16 <10>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <1>;
ti,settle-delay-usec = /bits/ 16 <150>;
ti,keep-vref-on;
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* Header (J12.4, J12.6) */
&lpuart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
status = "okay";
};
&netc_emdio {
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
&pcie0 {
reset-gpio = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie1 {
reset-gpio = <&pca6408_2 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb2 {
dr_mode = "host";
adp-disable;
hnp-disable;
srp-disable;
disable-over-current;
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_data_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
port@1 {
reg = <1>;
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
};
&usb3_phy {
fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>;
fsl,phy-pcs-tx-swing-full-percent = <100>;
fsl,phy-tx-preemp-amp-tune-microamp = <600>;
fsl,phy-tx-vboost-level-microvolt = <1156>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&scmi_iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
/* GPIO Expanders shared IRQ */
IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x31e
>;
};
pinctrl_captouch: captouchgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e
>;
};
pinctrl_enetc1: enetc1grp {
fsl,pins = <
IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x57e
IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e
IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e
IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e
IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e
IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x57e
IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e
IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e
IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e
IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e
IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x37e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e
IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e
>;
};
pinctrl_gpio_leds: ledgrp {
fsl,pins = <
IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x31e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
fsl,pins = <
IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x31e
IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x31e
>;
};
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins = <
IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
>;
};
pinctrl_lpspi7: lpspi7grp {
fsl,pins = <
/* j16.4 ADS7846 */
IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe
/* j14.4 MCP2518FDT */
IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x3fe
/* j25.2 spidev */
IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x3fe
IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe
IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe
IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe
>;
};
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
>;
};
pinctrl_restouch: restouchgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x31e
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e
IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};

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arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite DART-MX95
*
* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx95.dtsi"
/ {
model = "Variscite DART-MX95 Module";
compatible = "variscite,var-dart-mx95", "fsl,imx95";
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8_SW";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SW";
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_audio: regulator-audio-vdd {
compatible = "regulator-fixed";
regulator-name = "wm8904_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x7F000000>;
reusable;
size = <0 0x3c000000>;
linux,cma-default;
};
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio2 27 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
phy-handle = <&ethphy0>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
status = "okay";
};
&lpi2c8 {
clock-frequency = <400000>;
pinctrl-names = "default","gpio","sleep";
pinctrl-0 = <&pinctrl_lpi2c8>;
pinctrl-1 = <&pinctrl_lpi2c8_gpio>;
pinctrl-2 = <&pinctrl_lpi2c8_gpio>;
scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
clock-names = "mclk";
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
DCVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
/* BT */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&mu7 {
status = "okay";
};
&netc_emdio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>;
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
&netc_timer {
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-3 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
wakeup-source;
keep-power-in-suspend;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&scmi_iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e
>;
};
pinctrl_emdio: emdiogrp {
fsl,pins = <
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e
>;
};
pinctrl_enetc0: enetc0grp {
fsl,pins = <
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
>;
};
pinctrl_lpi2c8: lpi2c8grp {
fsl,pins = <
IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e
IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e
>;
};
pinctrl_lpi2c8_gpio: lpi2c8gpiogrp {
fsl,pins = <
IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e
IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e
>;
};
pinctrl_phy0res: phy0resgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e
IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e
IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e
IMX95_PAD_GPIO_IO01__LPUART5_RX 0x31e
IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3_gpio: usdhc3gpiogrp {
fsl,pins = <
IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x31e
IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x31e
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
};

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