From a3959de80f55d46b9a4001622b1e328dd218e051 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 18 Jan 2026 11:27:58 -0500 Subject: [PATCH 001/139] arm64: dts: imx8mm-evk: replace space with tab Replace spaces with tabs to follow the coding style. Reviewed-by: Marco Felsch Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6eab8a6001db..f58d849a8709 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -691,7 +691,7 @@ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 pinctrl_ir: irgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f >; }; @@ -724,26 +724,26 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 pinctrl_pcie0: pcie0grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 >; }; pinctrl_pcie0_reg: pcie0reggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 >; }; pinctrl_pdm: pdmgrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 - MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 - MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 - MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 - MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 - MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 >; }; @@ -761,19 +761,19 @@ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 pinctrl_sai2: sai2grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 >; }; pinctrl_sai3: sai3grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 >; }; From 9184a2c9b1937c46f58fc419114efebec7a0b99b Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Sun, 18 Jan 2026 11:27:59 -0500 Subject: [PATCH 002/139] arm64: dts: imx8mm-evk: correct the spdif compatible string Correct the spdif compatible string to "fsl,imx8mm-spdif". Signed-off-by: Shengjiu Wang Reviewed-by: Marco Felsch Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 9f49c0b386d3..f2e1854f38a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -400,7 +400,7 @@ micfil: audio-controller@30080000 { }; spdif1: spdif@30090000 { - compatible = "fsl,imx35-spdif"; + compatible = "fsl,imx8mm-spdif"; reg = <0x30090000 0x10000>; interrupts = ; clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ From 193be56821bc417d14e28a58d2502bcf37c318e1 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Sun, 18 Jan 2026 11:28:00 -0500 Subject: [PATCH 003/139] arm64: dts: imx8mm-evk: add uart1 and bluetooth node Add uart1 and bluetooth node. Signed-off-by: Sherry Sun Reviewed-by: Marco Felsch Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index f58d849a8709..30b13b4d630f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -608,6 +608,19 @@ &spdif1 { status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -790,6 +803,15 @@ MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 From 09a38b6f101aaac7cd66ec4af818484f79b1ee20 Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Sun, 18 Jan 2026 11:28:02 -0500 Subject: [PATCH 004/139] arm64: dts: imx8mm-evk: add uart3 port Add uart3 port. Signed-off-by: Fugang Duan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 30b13b4d630f..8be44eaf4e1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -627,6 +627,15 @@ &uart2 { /* console */ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &usbphynop1 { wakeup-source; }; @@ -819,6 +828,15 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 From 556de0fc240d5a182cbff6526f7712066a6011cc Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Sun, 18 Jan 2026 11:28:03 -0500 Subject: [PATCH 005/139] arm64: dts: imx8mn-evk: add bluetooth dts node Add bluetooth dts node. Signed-off-by: Sherry Sun Reviewed-by: Marco Felsch Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 145355ff91b4..3e590afa4fab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -415,6 +415,10 @@ &uart1 { /* BT */ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; }; &uart2 { /* console */ From 7dd78559984d2dc2d69a5aa183b3efd19b7593da Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 18 Jan 2026 11:28:05 -0500 Subject: [PATCH 006/139] arm64: dts: imx8mp-evk: replace space with tab Replace spaces with tabs to follow the coding style. Reviewed-by: Marco Felsch Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 28 ++++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index b256be710ea1..053c5e91f5aa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -965,33 +965,33 @@ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 >; }; pinctrl_flexcan_phy: flexcanphygrp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 - MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 - MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 - MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 - MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 - MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 >; }; @@ -1044,8 +1044,8 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 pinctrl_i2c5: i2c5grp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 - MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 >; }; From 2d763a22a64c6960af35aeea1de2ba2a0344c831 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Sun, 18 Jan 2026 11:28:06 -0500 Subject: [PATCH 007/139] arm64: dts: imx8mp-evk: add bluetooth dts node Add bluetooth dts node. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 053c5e91f5aa..33e7094d0e10 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -825,6 +825,10 @@ &uart1 { /* BT */ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; }; &uart2 { From 89320a1b9b93cf83ba97e18c69568184f8f7fda8 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Thu, 23 Oct 2025 12:34:26 +0200 Subject: [PATCH 008/139] arm64: dts: freescale: imx93-phy{core,board}: Add i2c bus recovery Add bus recovery feature for I2C buses on the PHYTEC phyCORE-i.MX93 SoM based boards (that is phyBOARD-Nash-i.MX93 and phyBOARD-Segin-i.MX93). This enables the i2c-imx-lpi2c driver to recover the stuck I2C bus by switching the SCL and SDA pinmuxing and do the I2C bus bit-banging. Signed-off-by: Primoz Fiser Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx93-phyboard-nash.dts | 12 +++++++++++- .../boot/dts/freescale/imx93-phyboard-segin.dts | 12 +++++++++++- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 12 +++++++++++- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index 9e875e082ee8..eac389ed30f3 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -144,8 +144,11 @@ &flexcan1 { /* I2C2 */ &lpi2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; /* RTC */ @@ -277,6 +280,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; }; + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = < + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + >; + }; + pinctrl_lpspi6: lpspi6grp { fsl,pins = < MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386 diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index ac64abacc4a2..a982606de1ee 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -148,8 +148,11 @@ &flexcan1 { /* I2C2 */ &lpi2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; /* Codec */ @@ -262,6 +265,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; }; + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = < + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 3f069905cf0b..ebc57841f27f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -93,8 +93,11 @@ ethphy1: ethernet-phy@1 { /* I2C3 */ &lpi2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@25 { @@ -234,6 +237,13 @@ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e >; }; + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO28__GPIO2_IO28 0x31e + MX93_PAD_GPIO_IO29__GPIO2_IO29 0x31e + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e From 43eeae2b00013460193ae44fb71cf005098e16a1 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Thu, 15 Jan 2026 16:24:53 +0100 Subject: [PATCH 009/139] arm64: dts: imx93: Add parallel display output nodes Add required OF nodes to support the i.MX93 parallel output (DPI) path. On the i.MX93 a single LCDIF is connected to three bridges: DPI, LVDS LDB and the MIPI-DSI whereas the i.MX91 support only the DPI bridge. Map endpoint@0 as DPI bridge output since the i.MX93 TRM (Figure 485. MEDIAMIX block diagram) doesn't mention any port-number <-> bridge combination. Set the MEDIA-AXI and MEDIA-APB clocks to the overdrive (OD) values since the i.MX93 and i.MX91 use the overdrive (OD) clk settings per default. Signed-off-by: Marco Felsch Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91_93_common.dtsi | 54 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx93.dtsi | 12 +++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index 7958cef35376..5a8813df6bc9 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -1122,8 +1122,62 @@ media_blk_ctrl: system-controller@4ac10000 { <&clk IMX93_CLK_MIPI_DSI_GATE>; clock-names = "apb", "axi", "nic", "disp", "cam", "pxp", "lcdif", "isi", "csi", "dsi"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <400000000>, <133333333>; #power-domain-cells = <1>; status = "disabled"; + + dpi_bridge: dpi-bridge { + compatible = "nxp,imx93-pdfc"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dpi>; + }; + }; + + port@1 { + reg = <1>; + + dpi_to_panel: endpoint { + }; + }; + }; + }; + }; + + lcdif: display-controller@4ae30000 { + compatible = "fsl,imx93-lcdif"; + reg = <0x4ae30000 0x23c>; + interrupts = ; + clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + lcdif_to_dpi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpi_from_lcdif>; + }; + }; }; usbotg1: usb@4c100000 { diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 7b27012dfcb5..5436b48b30e8 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -150,6 +150,18 @@ l3_cache: l3-cache { }; }; +&lcdif { + port { + lcdif_to_ldb: endpoint@1 { + reg = <1>; + }; + + lcdif_to_dsi: endpoint@2 { + reg = <2>; + }; + }; +}; + &src { mlmix: power-domain@44461800 { compatible = "fsl,imx93-src-slice"; From 8940756346ec498727acce4dd3fb4659b1fd83d3 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 21 Jan 2026 19:13:46 +0800 Subject: [PATCH 010/139] arm64: dts: imx93-evk/qsb: add m2-pcm-level-shifter-hog to enable BT HFP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For i.MX93 11x11 EVK and 9x9 QSB boards, add the gpio-hog to enable the M.2 PCM pins level shifter connected between soc sai1 interface and M.2 PCM pins so that HFP feature can be supported. Since the HFP is only used at a later stage — after the BT firmware has been downloaded and the BT connection with the remote device has been established — both the pcal6524 expander and sai1 interface are already fully initialized and available by that time. Therefore, using a gpio-hog here will not introduce any probe ordering or dependency issues for the HFP use case. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 6 ++++++ arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 8dd5340e8141..acb160d3186c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -356,6 +356,12 @@ pcal6524: gpio@22 { #interrupt-cells = <2>; interrupt-parent = <&gpio3>; interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; }; pmic@25 { diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts index 0852067eab2c..11e08673083b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts @@ -349,6 +349,12 @@ mic-can-sel-hog { gpios = <17 GPIO_ACTIVE_HIGH>; output-low; }; + + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; }; pmic@25 { From c13e6652c7ea2984b3e3094a18e1e6c441a06ce3 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 20 Jan 2026 18:48:42 +0800 Subject: [PATCH 011/139] arm64: dts: imx95-19x19-evk: enable lpuart5 for Bluetooth support Enable lpuart5 on imx95-19x19-evk board for Bluetooth support. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index aaa0da55a22b..041fd838fabb 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -475,7 +475,7 @@ &lpuart1 { &lpuart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - status = "disabled"; + status = "okay"; bluetooth { compatible = "nxp,88w8987-bt"; From 5f93cce741bc9ffbc9ce4b8ca4a1ff6bf1a881f0 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 20 Jan 2026 11:02:20 +0100 Subject: [PATCH 012/139] arm64: dts: imx8-apalis: Disable the audmix The audmix is not used on apalis imx8, disable it. This solves the following warning message imx-audmix imx-audmix.0: failed to find SAI platform device imx-audmix imx-audmix.0: probe with driver imx-audmix failed with error -22 Signed-off-by: Francesco Dolcini Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi | 4 ---- arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi | 4 ---- 3 files changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi index 06790255a764..6f5af37ba9af 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi @@ -22,10 +22,6 @@ &adc1 { status = "okay"; }; -&amix { - status = "okay"; -}; - &asrc0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index 7022de46b8bf..97fcd865fe3e 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -62,10 +62,6 @@ &adc1 { status = "okay"; }; -&amix { - status = "okay"; -}; - &asrc0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index 12732ed7f811..b70cf3e8f8c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -94,10 +94,6 @@ &adc1 { status = "okay"; }; -&amix { - status = "okay"; -}; - &asrc0 { status = "okay"; }; From 722094c436d6e393ca16441da9642eb61d102145 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 20 Jan 2026 10:52:05 +0800 Subject: [PATCH 013/139] arm64: dts: imx93-14x14-evk: enable lpuart5 for Bluetooth Enable lpuart5 for Bluetooth support. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index 61843b2c1b1b..ec78c03f4788 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -25,6 +25,7 @@ aliases { mmc1 = &usdhc2; rtc0 = &bbnsm_rtc; serial0 = &lpuart1; + serial4 = &lpuart5; }; bt_sco_codec: bt-sco-codec { @@ -400,6 +401,17 @@ &lpuart1 { /* console */ status = "okay"; }; +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &mu1 { status = "okay"; }; From b2150811e0efc767928b45ccebc9671fdf5c4c18 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 19 Jan 2026 18:52:15 +0800 Subject: [PATCH 014/139] arm64: dts: imx943-evk: enable lpuart6 for Bluetooth Enable lpuart6 for Bluetooth support. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 31fa9675cee1..f54404c9bfc9 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -21,6 +21,7 @@ aliases { mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; + serial5 = &lpuart6; }; bt_sco_codec: bt-sco-codec { @@ -437,6 +438,17 @@ &lpuart1 { status = "okay"; }; +&lpuart6 { + /* BT */ + pinctrl-0 = <&pinctrl_uart6>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &micfil { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, @@ -643,6 +655,15 @@ IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e >; }; + pinctrl_uart6: uart6grp { + fsl,pins = < + IMX94_PAD_GPIO_IO04__LPUART6_TX 0x31e + IMX94_PAD_GPIO_IO05__LPUART6_RX 0x31e + IMX94_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e + IMX94_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e + >; + }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e From 3ae57df0b37e638e587c6d6076847d303db3438b Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 19 Jan 2026 11:36:53 +0100 Subject: [PATCH 015/139] arm64: dts: imx8-apalis: Remove obsolete TODO comment The GPU is supported since Linux v6.9, with changes in the SoC dtsi file. Remove the related obsolete TODO comment. Signed-off-by: Francesco Dolcini Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi | 2 -- arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index 97fcd865fe3e..2677bc761b39 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -85,8 +85,6 @@ &flexcan2 { status = "okay"; }; -/* TODO: GPU */ - /* Apalis I2C1 */ &i2c2 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index b70cf3e8f8c1..268d5167e948 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -119,8 +119,6 @@ &flexcan2 { status = "okay"; }; -/* TODO: GPU */ - /* Apalis I2C1 */ &i2c2 { status = "okay"; From 92ab53b9bb2a72581c32073755077af916eb9aee Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 19 Jan 2026 11:34:09 +0100 Subject: [PATCH 016/139] arm64: dts: imx8-apalis: Fix LEDs name collision Ixora boards have multiple instances of status leds, to avoid a name collision add the function-enumerator property. This fixes the following Linux kernel warnings: leds-gpio leds: Led green:status renamed to green:status_1 due to name collision leds-gpio leds: Led red:status renamed to red:status_1 due to name collision Fixes: c083131c9021 ("arm64: dts: freescale: add apalis imx8 aka quadmax carrier board support") Signed-off-by: Francesco Dolcini Reviewed-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index 2677bc761b39..93f485140b20 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -21,6 +21,7 @@ led-1 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; }; @@ -29,6 +30,7 @@ led-2 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; }; @@ -37,6 +39,7 @@ led-3 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; }; @@ -45,6 +48,7 @@ led-4 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index 268d5167e948..5c86bcee55fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -21,6 +21,7 @@ led-1 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; }; @@ -29,6 +30,7 @@ led-2 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; }; @@ -37,6 +39,7 @@ led-3 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; }; @@ -45,6 +48,7 @@ led-4 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; }; }; From 0c9d379d436e119285ef39a4f96b012f576ed74c Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Thu, 29 Jan 2026 11:47:35 +0100 Subject: [PATCH 017/139] arm64: dts: freescale: imx95-toradex-smarc: fix PMIC_SD2_VSEL label position Fix the PMIC_SD2_VSEL gpio-line-name position. It should be on line 19 of gpio3, not line 20. Fixes: 90bbe88e0ea6 ("arm64: dts: freescale: add Toradex SMARC iMX95") Cc: stable@vger.kernel.org Signed-off-by: Emanuele Ghidoli Reviewed-by: Frank Li Reviewed-by: Francesco Dolcini Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 5932ba238a8a..f64c05dc50f8 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -262,7 +262,6 @@ &gpio3 { "", "", "", - "", "PMIC_SD2_VSEL"; status = "okay"; }; From 77ae6ab96581773dc799739252e632263a29b58f Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Tue, 3 Feb 2026 02:03:31 -0800 Subject: [PATCH 018/139] arm64: dts: imx95: add AONMIX MQS node Add DT node for AONMIX MQS (i.e. MQS1). Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 55e2da094c88..0c55861d673c 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -391,6 +391,11 @@ scmi_misc: protocol@84 { }; }; + mqs1: mqs-1 { + compatible = "fsl,imx95-aonmix-mqs"; + status = "disabled"; + }; + pmu { compatible = "arm,cortex-a55-pmu"; interrupts = ; From 87e4207ddfe945907da45ea7d1d5eb26c879ec59 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Tue, 3 Feb 2026 02:03:32 -0800 Subject: [PATCH 019/139] arm64: dts: imx95-15x15-frdm: support AONMIX MQS Add support for AONMIX MQS (i.e. MQS1). Reviewed-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../boot/dts/freescale/imx95-15x15-frdm.dts | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts index ca1c4966c867..0f43e3be7058 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts @@ -243,6 +243,12 @@ codec { }; }; + sound-mqs { + compatible = "audio-graph-card2"; + links = <&sai1_port1>; + label = "mqs-audio"; + }; + usdhc3_pwrseq: usdhc3-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>; @@ -473,6 +479,21 @@ &mu7 { status = "okay"; }; +&mqs1 { + clocks = <&scmi_clk IMX95_CLK_SAI1>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; + + mqs1_port: port { + mqs1_ep: endpoint { + dai-format = "left_j"; + remote-endpoint = <&sai1_port1_ep>; + }; + }; +}; + &netc_blk_ctrl { status = "okay"; }; @@ -534,6 +555,51 @@ &pcie0 { status = "okay"; }; +&sai1 { + clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, + <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, + <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, + <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* leave unconnected - no RX in the context of MQS */ + port@0 { + reg = <0>; + + endpoint { + }; + }; + + sai1_port1: port@1 { + reg = <1>; + mclk-fs = <512>; + + sai1_port1_ep: endpoint { + dai-format = "left_j"; + system-clock-direction-out; + bitclock-master; + frame-master; + remote-endpoint = <&mqs1_ep>; + }; + }; + }; +}; + &scmi_iomuxc { pinctrl_emdio: emdiogrp { fsl,pins = < @@ -618,6 +684,13 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e >; }; + pinctrl_mqs1: mqs1grp { + fsl,pins = < + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x31e + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x31e + >; + }; + pinctrl_pcal6524: pcal6524grp { fsl,pins = < IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e From 3eb100e561953d36bb6d1eb4ee27d3676e17c0ab Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 4 Feb 2026 16:35:48 +0800 Subject: [PATCH 020/139] arm64: dts: imx93: Extract common EVK description into shared dtsi The i.MX93 Wireless EVK reuses most of the 11x11 EVK design. To avoid duplication and DTS-to-DTS includes, extract the common parts into a new imx93-11x11-evk-common.dtsi shared by both boards. Rename imx93-11x11-evk.dts to imx93-11x11-evk-common.dtsi and include it from imx93-11x11-evk.dts. Only structural changes are introduced, with no intended functional impact. Signed-off-by: Sherry Sun Reviewed-by: Krzysztof Kozlowski Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../dts/freescale/imx93-11x11-evk-common.dtsi | 1057 +++++++++++++++++ .../boot/dts/freescale/imx93-11x11-evk.dts | 1053 +--------------- 2 files changed, 1059 insertions(+), 1051 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi new file mode 100644 index 000000000000..6279b8eb4ea7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi @@ -0,0 +1,1057 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022,2026 NXP + */ + +#include + +/ { + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + }; + + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-name = "VDD_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&adp5585 0 100000 0>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + power-supply = <®_vdd_12v>; + enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm33 { + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + phys = <&flexcan_phy>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + wm8962: codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + inertial-meter@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + vdd-supply = <&buck4>; + gpio-controller; + #gpio-cells = <2>; + gpio-reserved-ranges = <5 1>; + #pwm-cells = <3>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + adp5585_isp: io-expander@34 { + compatible = "adi,adp5585-01", "adi,adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <3>; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-1 = <&pinctrl_pdm_sleep>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-1 = <&pinctrl_sai3_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; + no-mmc; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&xcvr { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif_sleep>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e + MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e + MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e + MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e + MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e + MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_spdif_sleep: spdifsleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index acb160d3186c..b88876bb7128 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -1,1063 +1,14 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2022 NXP + * Copyright 2022,2026 NXP */ /dts-v1/; -#include #include "imx93.dtsi" +#include "imx93-11x11-evk-common.dtsi" / { model = "NXP i.MX93 11X11 EVK board"; compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; - - aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - rtc0 = &bbnsm_rtc; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - }; - - chosen { - stdout-path = &lpuart1; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - alloc-ranges = <0 0x80000000 0 0x40000000>; - size = <0 0x10000000>; - linux,cma-default; - }; - - vdev0vring0: vdev0vring0@a4000000 { - reg = <0 0xa4000000 0 0x8000>; - no-map; - }; - - vdev0vring1: vdev0vring1@a4008000 { - reg = <0 0xa4008000 0 0x8000>; - no-map; - }; - - vdev1vring0: vdev1vring0@a4010000 { - reg = <0 0xa4010000 0 0x8000>; - no-map; - }; - - vdev1vring1: vdev1vring1@a4018000 { - reg = <0 0xa4018000 0 0x8000>; - no-map; - }; - - rsc_table: rsc-table@2021e000 { - reg = <0 0x2021e000 0 0x1000>; - no-map; - }; - - vdevbuffer: vdevbuffer@a4020000 { - compatible = "shared-dma-pool"; - reg = <0 0xa4020000 0 0x100000>; - no-map; - }; - - }; - - flexcan_phy: can-phy { - compatible = "nxp,tja1057"; - #phy-cells = <0>; - max-bitrate = <5000000>; - silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vdd_12v: regulator-vdd-12v { - compatible = "regulator-fixed"; - regulator-name = "VDD_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-name = "vref_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_audio_pwr: regulator-audio-pwr { - compatible = "regulator-fixed"; - regulator-name = "audio-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_m2_pwr: regulator-m2-pwr { - compatible = "regulator-fixed"; - regulator-name = "M.2-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <12000>; - enable-active-high; - }; - - reg_usdhc3_vmmc: regulator-usdhc3 { - compatible = "regulator-fixed"; - regulator-name = "WLAN_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_m2_pwr>; - gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; - /* - * IW612 wifi chip needs more delay than other wifi chips to complete - * the host interface initialization after power up, otherwise the - * internal state of IW612 may be unstable, resulting in the failure of - * the SDIO3.0 switch voltage. - */ - startup-delay-us = <20000>; - enable-active-high; - }; - - usdhc3_pwrseq: usdhc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; - }; - - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&adp5585 0 100000 0>; - brightness-levels = <0 100>; - num-interpolated-steps = <100>; - default-brightness-level = <100>; - power-supply = <®_vdd_12v>; - enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - bt_sco_codec: bt-sco-codec { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai1>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&bt_sco_codec 1>; - }; - }; - - sound-micfil { - compatible = "fsl,imx-audio-card"; - model = "micfil-audio"; - - pri-dai-link { - link-name = "micfil hifi"; - format = "i2s"; - - cpu { - sound-dai = <&micfil>; - }; - }; - }; - - sound-wm8962 { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC", - "IN1R", "AMIC"; - }; - - sound-xcvr { - compatible = "fsl,imx-audio-card"; - model = "imx-audio-xcvr"; - - pri-dai-link { - link-name = "XCVR PCM"; - - cpu { - sound-dai = <&xcvr>; - }; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&cm33 { - mbox-names = "tx", "rx", "rxdb"; - mboxes = <&mu1 0 1>, - <&mu1 1 1>, - <&mu1 3 1>; - memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, - <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; - status = "okay"; -}; - -&eqos { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_eqos>; - pinctrl-1 = <&pinctrl_eqos_sleep>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; -}; - -&fec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy2>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - phys = <&flexcan_phy>; - status = "okay"; -}; - -&lpi2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1>; - status = "okay"; - - wm8962: codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX93_CLK_SAI3_GATE>; - DCVDD-supply = <®_audio_pwr>; - DBVDD-supply = <®_audio_pwr>; - AVDD-supply = <®_audio_pwr>; - CPVDD-supply = <®_audio_pwr>; - MICVDD-supply = <®_audio_pwr>; - PLLVDD-supply = <®_audio_pwr>; - SPKVDD1-supply = <®_audio_pwr>; - SPKVDD2-supply = <®_audio_pwr>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - inertial-meter@6a { - compatible = "st,lsm6dso"; - reg = <0x6a>; - }; -}; - -&lpi2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c2>; - status = "okay"; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - reg = <0x22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6524>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - m2-pcm-level-shifter-hog { - gpio-hog; - gpios = <19 GPIO_ACTIVE_HIGH>; - output-high; - }; - }; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupt-parent = <&pcal6524>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <610000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <670000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <840000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - adp5585: io-expander@34 { - compatible = "adi,adp5585-00", "adi,adp5585"; - reg = <0x34>; - vdd-supply = <&buck4>; - gpio-controller; - #gpio-cells = <2>; - gpio-reserved-ranges = <5 1>; - #pwm-cells = <3>; - }; -}; - -&lpi2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c3>; - status = "okay"; - - adp5585_isp: io-expander@34 { - compatible = "adi,adp5585-01", "adi,adp5585"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <3>; - }; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x50>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - }; - }; - - ptn5110_2: tcpc@51 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x51>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - typec2_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec2_dr_sw: endpoint { - remote-endpoint = <&usb2_drd_sw>; - }; - }; - }; - }; - }; - - pcf2131: rtc@53 { - compatible = "nxp,pcf2131"; - reg = <0x53>; - interrupt-parent = <&pcal6524>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&lpuart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&lpuart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; - - bluetooth { - compatible = "nxp,88w8987-bt"; - }; -}; - -&micfil { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_pdm>; - pinctrl-1 = <&pinctrl_pdm_sleep>; - assigned-clocks = <&clk IMX93_CLK_PDM>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <49152000>; - status = "okay"; -}; - -&mu1 { - status = "okay"; -}; - -&mu2 { - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_sai1>; - pinctrl-1 = <&pinctrl_sai1_sleep>; - assigned-clocks = <&clk IMX93_CLK_SAI1>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_sai3>; - pinctrl-1 = <&pinctrl_sai3_sleep>; - assigned-clocks = <&clk IMX93_CLK_SAI3>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usbotg2 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb2_drd_sw: endpoint { - remote-endpoint = <&typec2_dr_sw>; - }; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; - no-mmc; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; - mmc-pwrseq = <&usdhc3_pwrseq>; - vmmc-supply = <®_usdhc3_vmmc>; - bus-width = <4>; - keep-power-in-suspend; - non-removable; - wakeup-source; - status = "okay"; -}; - -&wdog3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&xcvr { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_spdif>; - pinctrl-1 = <&pinctrl_spdif_sleep>; - assigned-clocks = <&clk IMX93_CLK_SPDIF>, - <&clk IMX93_CLK_AUDIO_XCVR>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <12288000>, <200000000>; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e - MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e - MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e - MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_eqos_sleep: eqossleepgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e - MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e - MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e - MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e - MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e - MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e - MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e - MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e - MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e - MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e - MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e - MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e - MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e - MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_fec_sleep: fecsleepgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e - MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e - MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e - MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e - MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e - MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e - MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e - MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e - MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e - MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e - MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e - MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e - MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e - MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX93_PAD_GPIO_IO25__CAN2_TX 0x139e - MX93_PAD_GPIO_IO27__CAN2_RX 0x139e - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e - MX93_PAD_DAP_TDI__LPUART5_RX 0x31e - MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e - MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e - MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e - MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = < - MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - }; - - pinctrl_pcal6524: pcal6524grp { - fsl,pins = < - MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e - >; - }; - - pinctrl_pdm: pdmgrp { - fsl,pins = < - MX93_PAD_PDM_CLK__PDM_CLK 0x31e - MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e - MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e - >; - }; - - pinctrl_pdm_sleep: pdmsleepgrp { - fsl,pins = < - MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e - MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e - MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e - MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e - MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e - MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e - >; - }; - - pinctrl_sai1_sleep: sai1sleepgrp { - fsl,pins = < - MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e - MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e - MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e - MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 - MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e - MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e - MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e - MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e - MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e - >; - }; - - pinctrl_sai3_sleep: sai3sleepgrp { - fsl,pins = < - MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e - MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e - MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e - MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e - MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e - MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e - >; - }; - - pinctrl_spdif_sleep: spdifsleepgrp { - fsl,pins = < - MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e - MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 - MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_sleep: usdhc2sleepgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e - MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e - MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e - MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e - MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e - MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e - MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 - MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 - MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 - MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 - MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 - MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e - MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e - MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e - MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e - MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e - MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe - MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe - MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe - MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe - MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe - MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe - >; - }; - - pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { - fsl,pins = < - MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e - MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e - MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e - MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e - MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e - MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e - >; - }; - - pinctrl_usdhc3_wlan: usdhc3wlangrp { - fsl,pins = < - MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e - >; - }; }; From f245e8eb168932a68c87c6e13d46eacb1893478d Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 4 Feb 2026 16:35:49 +0800 Subject: [PATCH 021/139] arm64: dts: imx93: Move 11x11 EVK specific parts back to imx93-11x11-evk.dts The previous patch renamed imx93-11x11-evk.dts to imx93-11x11-evk-common.dtsi to prepare for adding the i.MX93 Wireless EVK, which shares most of its design with the 11x11 EVK. Move the board specific differences out of imx93-11x11-evk-common.dtsi and back into imx93-11x11-evk.dts, ensuring that the common dtsi only contains the truly shared parts between the two EVK boards. No functional changes intended. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../dts/freescale/imx93-11x11-evk-common.dtsi | 198 ----------------- .../boot/dts/freescale/imx93-11x11-evk.dts | 206 ++++++++++++++++++ 2 files changed, 206 insertions(+), 198 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi index 6279b8eb4ea7..301e9f05122e 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi @@ -107,15 +107,6 @@ reg_audio_pwr: regulator-audio-pwr { enable-active-high; }; - reg_m2_pwr: regulator-m2-pwr { - compatible = "regulator-fixed"; - regulator-name = "M.2-power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -128,28 +119,6 @@ reg_usdhc2_vmmc: regulator-usdhc2 { enable-active-high; }; - reg_usdhc3_vmmc: regulator-usdhc3 { - compatible = "regulator-fixed"; - regulator-name = "WLAN_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_m2_pwr>; - gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; - /* - * IW612 wifi chip needs more delay than other wifi chips to complete - * the host interface initialization after power up, otherwise the - * internal state of IW612 may be unstable, resulting in the failure of - * the SDIO3.0 switch voltage. - */ - startup-delay-us = <20000>; - enable-active-high; - }; - - usdhc3_pwrseq: usdhc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; - }; - backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&adp5585 0 100000 0>; @@ -161,44 +130,6 @@ backlight_lvds: backlight-lvds { status = "disabled"; }; - bt_sco_codec: bt-sco-codec { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai1>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&bt_sco_codec 1>; - }; - }; - - sound-micfil { - compatible = "fsl,imx-audio-card"; - model = "micfil-audio"; - - pri-dai-link { - link-name = "micfil hifi"; - format = "i2s"; - - cpu { - sound-dai = <&micfil>; - }; - }; - }; - sound-wm8962 { compatible = "fsl,imx-audio-wm8962"; model = "wm8962-audio"; @@ -350,12 +281,6 @@ pcal6524: gpio@22 { #interrupt-cells = <2>; interrupt-parent = <&gpio3>; interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - m2-pcm-level-shifter-hog { - gpio-hog; - gpios = <19 GPIO_ACTIVE_HIGH>; - output-high; - }; }; pmic@25 { @@ -548,16 +473,6 @@ bluetooth { }; }; -&micfil { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_pdm>; - pinctrl-1 = <&pinctrl_pdm_sleep>; - assigned-clocks = <&clk IMX93_CLK_PDM>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <49152000>; - status = "okay"; -}; - &mu1 { status = "okay"; }; @@ -566,17 +481,6 @@ &mu2 { status = "okay"; }; -&sai1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_sai1>; - pinctrl-1 = <&pinctrl_sai1_sleep>; - assigned-clocks = <&clk IMX93_CLK_SAI1>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - &sai3 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_sai3>; @@ -647,21 +551,6 @@ &usdhc2 { no-mmc; }; -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; - pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; - mmc-pwrseq = <&usdhc3_pwrseq>; - vmmc-supply = <®_usdhc3_vmmc>; - bus-width = <4>; - keep-power-in-suspend; - non-removable; - wakeup-source; - status = "okay"; -}; - &wdog3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -808,40 +697,6 @@ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e >; }; - pinctrl_pdm: pdmgrp { - fsl,pins = < - MX93_PAD_PDM_CLK__PDM_CLK 0x31e - MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e - MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e - >; - }; - - pinctrl_pdm_sleep: pdmsleepgrp { - fsl,pins = < - MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e - MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e - MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e - MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e - MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e - MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e - >; - }; - - pinctrl_sai1_sleep: sai1sleepgrp { - fsl,pins = < - MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e - MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e - MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e - MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e - >; - }; - /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < @@ -996,59 +851,6 @@ MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e >; }; - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 - MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 - MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 - MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 - MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 - MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e - MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e - MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e - MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e - MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e - MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe - MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe - MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe - MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe - MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe - MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe - >; - }; - - pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { - fsl,pins = < - MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e - MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e - MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e - MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e - MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e - MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e - >; - }; - - pinctrl_usdhc3_wlan: usdhc3wlangrp { - fsl,pins = < - MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e - >; - }; - pinctrl_wdog: wdoggrp { fsl,pins = < MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index b88876bb7128..c6db9c85f2ac 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -11,4 +11,210 @@ / { model = "NXP i.MX93 11X11 EVK board"; compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + + aliases { + mmc2 = &usdhc3; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; + + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; +}; + +&micfil { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-1 = <&pinctrl_pdm_sleep>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&pcal6524 { + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__PDM_CLK 0x31e + MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e + MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e + MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e + MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; }; From 6c41fe5964c270d11fceb683c041ccc35c4434d1 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 4 Feb 2026 16:35:50 +0800 Subject: [PATCH 022/139] arm64: dts: imx93: Add imx93w.dtsi for i.MX93 Wireless SiP Introduce imx93w.dtsi to describe the new NXP i.MX93 Wireless SiP, which integrates the i.MX93 application processor with the NXP IW610 WLCSP (Wi-Fi + Bluetooth LE + 802.15.4) connectivity device. The new imx93w.dtsi is based on imx93.dtsi and adds the pieces required for the internal connection between i.MX93 and IW610 inside the SiP. This includes USDHC3 which is used as the host interface to the IW610 and the required GPIO settings(e.g. WL_RST, WL_REG_ON, etc.). These nodes reflect internal SiP wiring and are not board specific, so they are placed in a dedicated imx93w.dtsi file that can be reused by multiple boards adopting the i.MX93 Wireless SiP. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93w.dtsi | 110 ++++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93w.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx93w.dtsi b/arch/arm64/boot/dts/freescale/imx93w.dtsi new file mode 100644 index 000000000000..95fb025c3949 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93w.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +#include "imx93.dtsi" + +/ { + aliases { + mmc2 = &usdhc3; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc3_vmmc>; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_reg_usdhc3_vmmc: regusdhc3vmmcgrp { + fsl,pins = < + /* + * Enable open drain and internal pull-up to allow the IW610 JTAG + * connector to control the PDn status. + */ + MX93_PAD_GPIO_IO29__GPIO2_IO29 0xb9e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x39e + >; + }; +}; From 8c2d3dd02d1a22d3f2c00ba98e90e283c1d0db20 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 4 Feb 2026 16:35:51 +0800 Subject: [PATCH 023/139] arm64: dts: imx93: Add i.MX93 Wireless EVK board support i.MX93 Wireless SiP is created by integrating i.MX93 and IW610 WLCSP (Wi-Fi + BLE + 802.15.4). And i.MX93 Wireless EVK board with the i.MX93 Wireless SiP basically reuse the i.MX93 11x11 EVK board, with some minor functional and pin connection differences. Reuse the new imx93-11x11-evk-common.dtsi and add the board-specific changes here. Here are the detailed differences between i.MX93 Wireless EVK and i.MX93 11x11 EVK board. Function differences: Function i.MX93W EVK i.MX93 EVK WIFI/BT IW610 in i.MX93W IW612 M.2 module MQS N Y PDM MIC N Y M.2 N Y RPi 40-pin HDR Limited support(pin conflict) Y Pin connection differences: Function Signal name i.MX93W EVK i.MX93 EVK WIFI/BT SPI_FRM SAI1_TXFS (spi1.PCS0) GPIO_IO08 (spi3.PCS0) SPI_TXD SAI1_TXC (spi1.SIN) GPIO_IO09 (spi3.SIN) SPI_RXD SAI1_RXD0 (spi1.SOUT) GPIO_IO10 (spi3.SOUT) SPI_CLK SAI1_TXD0 (spi1.SCK) GPIO_IO11 (spi3.SCK) SPI_INT CCM_CLKO1 on-board IO expander NB_WAKE_IN PDM_CLK on-module IO expander WL_WAKE_IN PDM_BIT_STREAM0 on-module IO expander IND_RST_WL PDM_BIT_STREAM1 on-module IO expander IND_RST_NB GPIO_IO28 on-module IO expander PDn GPIO_IO29 on-module IO expander NB_WAKE_OUT GPIO_IO14 on-board IO expander WL_WAKE_OUT GPIO_IO15 CCM_CLKO1 I2C3 I2C3_SDA GPIO_IO00 GPIO_IO28 I2C3_SCL GPIO_IO01 GPIO_IO29 Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx93w-evk.dts | 28 ++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93w-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 700bab4d3e60..8837d7ec4f3e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -439,6 +439,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93w-evk.dts b/arch/arm64/boot/dts/freescale/imx93w-evk.dts new file mode 100644 index 000000000000..8e53e7384013 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93w-evk.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; + +#include "imx93w.dtsi" +#include "imx93-11x11-evk-common.dtsi" + +/ { + model = "NXP i.MX93W EVK board"; + compatible = "fsl,imx93-wireless-evk", "fsl,imx93"; +}; + +&lpi2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; +}; + +&iomuxc { + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e + >; + }; +}; From c915f81aa3c71247601edad955602d60d629fcdd Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Wed, 11 Feb 2026 17:28:25 +0800 Subject: [PATCH 024/139] arm64: dts: imx95: Reserve eDMA channels 0-1 for V2X Reserve eDMA channels 0 and 1 on the AXI eDMA controller for exclusive use by V2X (Vehicle-to-Everything) fast hash operations. Reviewed-by: Laurentiu Mihalcea Tested-by: Laurentiu Mihalcea Signed-off-by: Joy Zou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 0c55861d673c..5f61866e9df9 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -636,6 +636,8 @@ edma2: dma-controller@42000000 { reg = <0x42000000 0x210000>; #dma-cells = <3>; dma-channels = <64>; + /* channels 0 and 1 reserved for V2X fast hash */ + dma-channel-mask = <0x3>; interrupts = , , , From 12f56ee0ad2b7512808e06a804290bc7720530b1 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Wed, 11 Feb 2026 17:28:26 +0800 Subject: [PATCH 025/139] arm64: dts: imx95-evk: update the dma-channel-mask property Have reserved eDMA2 channels 0 and 1 for V2X fast hash in imx95.dtsi. So update the dma-channel-mask from 0xc0000000 to 0xc0000003 to mark channels 0, 1, 30, and 31 as reserved. Signed-off-by: Joy Zou Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts index 808a9fe3ebb2..264703f6eef6 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts @@ -55,8 +55,11 @@ sound-wm8962 { }; &edma2 { - /* channels 30 and 31 reserved for FW usage */ - dma-channel-mask = <0xc0000000>, <0x0>; + /* + * channels 0 and 1 reserved for V2X fast hash, + * channels 30 and 31 reserved for FW usage + */ + dma-channel-mask = <0xc0000003>, <0x0>; }; &sai3 { From 5ab0c76df2403137a6d0fb27a55e03cedf47f44c Mon Sep 17 00:00:00 2001 From: Luke Wang Date: Tue, 3 Feb 2026 19:23:10 +0800 Subject: [PATCH 026/139] arm64: dts: imx91-11x11-evk: change usdhc tuning step for eMMC and SD During system resume, the following errors occurred: [ 430.638625] mmc1: error -84 writing Cache Enable bit [ 430.643618] mmc1: error -84 doing runtime resume For eMMC and SD, there are two tuning pass windows and the gap between those two windows may only have one cell. If tuning step > 1, the gap may just be skipped and host assumes those two windows as a continuous windows. This will cause a wrong delay cell near the gap to be selected. Set the tuning step to 1 to avoid selecting the wrong delay cell. For SDIO, the gap is sufficiently large, so the default tuning step does not cause this issue. Fixes: 6772c4cffd87 ("arm64: dts: freescale: add i.MX91 11x11 EVK basic support") Signed-off-by: Luke Wang Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 03f460d62f7a..6a066a0d86bc 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -514,6 +514,7 @@ &usdhc1 { pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; + fsl,tuning-step = <1>; status = "okay"; }; @@ -528,6 +529,7 @@ &usdhc2 { pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; status = "okay"; }; From 399c6e3385a79e0e93837b504ad58477c22db841 Mon Sep 17 00:00:00 2001 From: Luke Wang Date: Tue, 3 Feb 2026 19:23:09 +0800 Subject: [PATCH 027/139] arm64: dts: imx93-11x11-evk: change usdhc tuning step for eMMC and SD During system resume, the following errors occurred: [ 430.638625] mmc1: error -84 writing Cache Enable bit [ 430.643618] mmc1: error -84 doing runtime resume For eMMC and SD, there are two tuning pass windows and the gap between those two windows may only have one cell. If tuning step > 1, the gap may just be skipped and host assumes those two windows as a continuous windows. This will cause a wrong delay cell near the gap to be selected. Set the tuning step to 1 to avoid selecting the wrong delay cell. For SDIO, the gap is sufficiently large, so the default tuning step does not cause this issue. Fixes: e37907bd8294 ("arm64: dts: freescale: add i.MX93 11x11 EVK basic support") Signed-off-by: Luke Wang Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi index 301e9f05122e..7d3fc4ad7b8b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi @@ -535,6 +535,7 @@ &usdhc1 { pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; + fsl,tuning-step = <1>; status = "okay"; }; @@ -547,6 +548,7 @@ &usdhc2 { cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; bus-width = <4>; + fsl,tuning-step = <1>; status = "okay"; no-mmc; }; From 973ec14af07f774c892e8e07f1e1340a1fc50031 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 25 Feb 2026 14:47:25 +0800 Subject: [PATCH 028/139] arm64: dts: imx952: Add xspi node Add xspi node for i.MX952 Signed-off-by: Haibo Chen Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index 91fe4916ac04..0f86b5626cdd 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -672,6 +672,25 @@ mu8: mailbox@42350000 { #mbox-cells = <2>; status = "disabled"; }; + + xspi1: spi@42400000 { + compatible = "nxp,imx952-xspi", "nxp,imx94-xspi"; + reg = <0x42400000 0x50000>, <0x28000000 0x8000000>; + reg-names = "base", "mmap"; + interrupts = , + , + , + , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_XSPI1>; + clock-names = "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_XSPI1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + status = "disabled"; + }; }; aips3: bus@42800000 { From 88d1b3336e797d8036710298590ff9e0e0d21488 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 25 Feb 2026 14:47:26 +0800 Subject: [PATCH 029/139] arm64: dts: imx952-evk: add MT35XU01G spi nor flash Add spi nor flash MT35XU01G support, it support OCT DTR mode at 200MHz. Signed-off-by: Haibo Chen Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index b838323468d4..509704c23e89 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -593,4 +593,45 @@ pinctrl_usdhc2_gpio: usdhc2gpiogrp { IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x39e + IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x39e + IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x39e + IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x39e + IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x39e + IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x39e + IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x39e + IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x39e + IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x39e + IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x39e + IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x39e + >; + }; + + pinctrl_xspi1_reset: xspi1-reset-grp { + fsl,pins = < + IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x39e + >; + }; +}; + +&xspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1>; + status = "okay"; + + mt35xu01gbba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1_reset>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; }; From 51c0c3d880acc45a9b57d505195d93541b38b3f5 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 4 Feb 2026 10:23:06 +0800 Subject: [PATCH 030/139] arm64: dts: imx943-evk: add usdhc3 for SDIO WiFi support Add usdhc3 to support M.2 SDIO WiFi on i.MX943 EVK board. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 61 ++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index f54404c9bfc9..c8ceabe3d923 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -20,6 +20,7 @@ aliases { i2c5 = &lpi2c6; mmc0 = &usdhc1; mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &lpuart1; serial5 = &lpuart6; }; @@ -54,6 +55,32 @@ dmic: dmic { #sound-dai-cells = <0>; }; + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6416_i2c3_u46 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * M.2 device only can be enabled(W_DISABLE1#) after all Power + * Rails reach their minimum operating voltage (PCI Express M.2 + * Specification r5.1 3.1.4 Power-up Timing). + * Set a delay equal to the max value of Tsettle here. + */ + startup-delay-us = <5000>; + }; + + reg_m2_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6416_i2c3_u46 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; off-on-delay-us = <12000>; @@ -141,6 +168,11 @@ sound-wm8962 { model = "wm8962-audio"; }; + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6416_i2c3_u46 4 GPIO_ACTIVE_LOW>; + }; + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; device_type = "memory"; @@ -760,6 +792,18 @@ IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e >; }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX94_PAD_GPIO_IO48__USDHC3_CLK 0x158e + /* Need to config the SION for CMD pad, refer to ERR053138 */ + IMX94_PAD_GPIO_IO49__USDHC3_CMD 0x4000138e + IMX94_PAD_GPIO_IO50__USDHC3_DATA0 0x138e + IMX94_PAD_GPIO_IO51__USDHC3_DATA1 0x138e + IMX94_PAD_GPIO_IO52__USDHC3_DATA2 0x138e + IMX94_PAD_GPIO_IO53__USDHC3_DATA3 0x138e + >; + }; + pinctrl_xspi1: xspi1grp { fsl,pins = < IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe @@ -802,6 +846,23 @@ &usdhc2 { status = "okay"; }; +&usdhc3 { + /* + * Only enable SDIO2.0 mode as the corresponding GPIO pads are 3.3V, the + * max frequency is 50MHz. + */ + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "sleep"; + bus-width = <4>; + vmmc-supply = <®_m2_wlan>; + mmc-pwrseq = <&usdhc3_pwrseq>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + &wdog3 { fsl,ext-reset-output; status = "okay"; From d1e7eab6033f9885a02c4b4e8f09e34d8e9d21ab Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Thu, 5 Feb 2026 15:34:53 +0800 Subject: [PATCH 031/139] arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO (M.2 W_DISABLE1) The current pin configuration for MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 sets the weak pull-up but does not enable the pull select field. Bit 8 in the IOMUX register must be set in order for the weak pull-up to actually take effect. Update the pinctrl setting from 0x40 to 0x140 to enable both the pull select and the weak pull-up, ensuring the line behaves as expected. Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support") Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 33e7094d0e10..70897289680c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -1068,7 +1068,7 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 pinctrl_pcie0_reg: pcie0reggrp { fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140 >; }; From feea0340ad290aac84f76b9886336419168b72a4 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Thu, 5 Feb 2026 15:34:54 +0800 Subject: [PATCH 032/139] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board. Signed-off-by: Sherry Sun Reviewed-by: Frank Li Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 61 +++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 70897289680c..aedc09937716 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -134,7 +134,7 @@ reg_audio_pwr: regulator-audio-pwr { enable-active-high; }; - reg_pcie0: regulator-pcie { + reg_m2_wlan: reg_pcie0: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0_reg>; @@ -250,6 +250,13 @@ cpu { }; }; + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_pwrseq>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -862,6 +869,19 @@ &uart3 { status = "okay"; }; +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + keep-power-in-suspend; + non-removable; + wakeup-source; + mmc-pwrseq = <&usdhc1_pwrseq>; + vmmc-supply = <®_m2_wlan>; + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; @@ -1168,6 +1188,45 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc1_pwrseq: usdhc1pwrseqgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 From 9c94cb52c80fce841fda417dc6168d6c9f3dbc60 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Thu, 5 Feb 2026 18:06:47 +0800 Subject: [PATCH 033/139] arm64: dts: imx91-11x11-evk: Add usdhc3 for SDIO WiFi support Add usdhc3 to support M.2 SDIO WiFi on i.MX91 11x11 EVK board. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-11x11-evk.dts | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 6a066a0d86bc..c083b97476a5 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -23,6 +23,7 @@ aliases { i2c2 = &lpi2c3; mmc0 = &usdhc1; mmc1 = &usdhc2; + mmc2 = &usdhc3; rtc0 = &bbnsm_rtc; serial0 = &lpuart1; serial1 = &lpuart2; @@ -57,6 +58,15 @@ reg_audio_pwr: regulator-audio-pwr { enable-active-high; }; + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; off-on-delay-us = <12000>; @@ -69,6 +79,23 @@ reg_usdhc2_vmmc: regulator-usdhc2 { enable-active-high; }; + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + reserved-memory { ranges; #address-cells = <2>; @@ -144,6 +171,11 @@ cpu { }; }; }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; }; &adc1 { @@ -246,6 +278,12 @@ pcal6524: gpio@22 { interrupt-parent = <&gpio3>; pinctrl-0 = <&pinctrl_pcal6524>; pinctrl-names = "default"; + + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; }; pmic@25 { @@ -533,6 +571,21 @@ &usdhc2 { status = "okay"; }; +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + &wdog3 { fsl,ext-reset-output; status = "okay"; @@ -852,4 +905,47 @@ MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e >; }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; }; From 9a7dded511a789ff4abb9b6db5db001d7cef06da Mon Sep 17 00:00:00 2001 From: Yanan Yang Date: Tue, 10 Feb 2026 19:47:55 +0900 Subject: [PATCH 034/139] arm64: dts: freescale: add NXP FRDM-IMX91S board support Add DeviceTree support for the NXP FRDM-IMX91S development board based on the i.MX91 SoC. FRDM-IMX91S is a cost-optimized variant of FRDM-IMX91 and differs in memory, storage, Ethernet, and PMIC configuration: - 512MB LPDDR4 (FRDM-IMX91 uses 1GB) - 256MB FlexSPI-NAND (FRDM-IMX91 uses 8GB eMMC) - Single GbE port (FRDM-IMX91 has dual GbE) - PMIC PF9453 (FRDM-IMX91 uses PCA9451A) This DT enables: - ADC1 - UART1 and UART5 - I2C bus and children nodes - USB and related nodes - uSDHC1 and uSDHC2 - FlexSPI NAND flash - Watchdog3 - Ethernet (eqos) - FlexCAN - MQS Link: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91S (FRDM-IMX91S board page) Link: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91 (FRDM-IMX91 board page) Co-developed-by: Lei Xu Signed-off-by: Lei Xu Co-developed-by: Xiaofeng Wei Signed-off-by: Xiaofeng Wei Signed-off-by: Yanan Yang Tested-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-11x11-frdm-s.dts | 769 ++++++++++++++++++ 2 files changed, 770 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 8837d7ec4f3e..dc1a8911035a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -406,6 +406,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts new file mode 100644 index 000000000000..62dc1dedfb0e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts @@ -0,0 +1,769 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-frdm-s", "fsl,imx91"; + model = "NXP FRDM-IMX91S board"; + + aliases { + ethernet0 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf2131; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan1_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_key>; + pinctrl-names = "default"; + + button { + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + gpios = <&gpio3 26 GPIO_PULL_UP>; + label = "User Button"; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + default-state = "on"; + gpios = <&pcal6524 7 GPIO_ACTIVE_LOW>; + label = "green:status"; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_usdhc1_vmmc: regulator-usdhc1 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + startup-delay-us = <20000>; + gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + bootph-pre-ram; + bootph-some-ram; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_VBUS"; + gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x20000000>; + reusable; + size = <0 0x2000000>; + linux,cma-default; + }; + }; + + soc@0 { + bootph-all; + bootph-pre-ram; + }; + + sound-mqs { + compatible = "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-codec = <&mqs1>; + audio-cpu = <&sai1>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 18 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&clk { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&flexcan1 { + phys = <&flexcan1_phy>; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x000000 0x800000>; + label = "bootloader"; + }; + + partition@1 { + reg = <0x800000 0x800000>; + label = "env"; + }; + + partition@2 { + reg = <0x1000000 0x2800000>; + label = "kernel"; + }; + + partition@3 { + reg = <0x3800000 0x20000>; + label = "dtb"; + }; + + partition@4 { + reg = <0x3820000 0xc7e0000>; + label = "rootfs"; + linux,rootfs; + }; + }; + }; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__CAN1_TX 0x139e + MX91_PAD_GPIO_IO29__CAN1_RX 0x139e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_flexcan1_sleep: flexcan1sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x3fe + MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x3fe + MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x3fe + MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x3fe + >; + }; + + pinctrl_gpio_key: gpiokeysgrp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + MX91_PAD_SD1_DATA5__GPIO3_IO15 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + bootph-pre-ram; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e + MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e + MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e + MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + + pmic@32 { + compatible = "nxp,pf9453"; + reg = <0x32>; + interrupt-parent = <&pcal6524>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3775000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK1"; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <12500>; + }; + + buck3: BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3775000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK3"; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3775000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO1"; + }; + + ldo2: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <500000>; + regulator-name = "LDO2"; + }; + + ldo_snvs: LDO-SNVS { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1200000>; + regulator-name = "LDO-SNVS"; + }; + }; + }; + + ptn5110: tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&mqs1 { + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&sai1 { + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc1_vmmc>; + wakeup-source; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&wdog3 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; From f9084ded66bb4d3801d57e7f355f872081158776 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Mon, 16 Feb 2026 14:07:09 +0100 Subject: [PATCH 035/139] arm64: dts: imx8mm: Add pinctrl config definitions Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this register is written in the dts, these values are not obvious. Add defines which describe the fields of this register which can be or-ed together to produce readable settings. Reviewed-by: Frank Li Signed-off-by: Maud Spierings Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx8mm-pinfunc.h | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h index b1f11098d248..31557b7b9ccc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -6,6 +6,39 @@ #ifndef __DTS_IMX8MM_PINFUNC_H #define __DTS_IMX8MM_PINFUNC_H +/* Drive Strength */ +#define MX8MM_DSE_X1 0x0 +#define MX8MM_DSE_X2 0x4 +#define MX8MM_DSE_X4 0x2 +#define MX8MM_DSE_X6 0x6 + +/* Slew Rate */ +#define MX8MM_FSEL_FAST 0x10 +#define MX8MM_FSEL_SLOW 0x0 + +/* Open Drain */ +#define MX8MM_ODE_ENABLE 0x20 +#define MX8MM_ODE_DISABLE 0x0 + +#define MX8MM_PULL_DOWN 0x0 +#define MX8MM_PULL_UP 0x40 + +/* Hysteresis */ +#define MX8MM_HYS_CMOS 0x0 +#define MX8MM_HYS_SCHMITT 0x80 + +#define MX8MM_PULL_ENABLE 0x100 +#define MX8MM_PULL_DISABLE 0x0 + +/* SION force input mode */ +#define MX8MM_SION 0x40000000 + +/* long defaults */ +#define MX8MM_USDHC_DATA_DEFAULT (MX8MM_FSEL_FAST | MX8MM_PULL_UP | \ + MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) +#define MX8MM_I2C_DEFAULT (MX8MM_DSE_X6 | MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | \ + MX8MM_PULL_ENABLE | MX8MM_SION) + /* * The pin function ID is a tuple of * From ce6765b80f8fcf5d5702a091546c72ccc5d2be6a Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Mon, 16 Feb 2026 14:07:10 +0100 Subject: [PATCH 036/139] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM The Ka-Ro Electronics tx8m-1610 is a COM based on the imx8mm SOC. It has 1 GB of ram and 4 GB of eMMC storage on board. Add it to enable boards based on this module Reviewed-by: Frank Li Signed-off-by: Maud Spierings Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-tx8m-1610.dtsi | 444 ++++++++++++++++++ 1 file changed, 444 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi new file mode 100644 index 000000000000..ba00f7063476 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 Lothar Waßmann + * 2025 Maud Spierings + */ + +#include "imx8mm.dtsi" + +/ { + model = "Ka-Ro Electronics TX8M-1610"; + compatible = "karo,tx8m-1610", "fsl,imx8mm"; + + reg_3v3_etn: regulator-3v3-etn { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_3v3_etn>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3-etn"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; +}; + +&fec1 { + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>, + <&clk IMX8MM_CLK_ENET_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>; + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + phy-reset-duration = <25>; + phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <1>; + phy-supply = <®_3v3_etn>; + pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_ethphy_rst>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + clocks = <&clk IMX8MM_CLK_ENET_REF>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_ethphy_int>; + pinctrl-names = "default"; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names = "SODIMM_152", "SODIMM_42", "SODIMM_153", "PMIC_IRQ_B", + "SODIMM_154", "SODIMM_155", "SODIMM_156", "SODIMM_157", + "SODIMM_158", "SODIMM_159", "SODIMM_161", "SODIMM_162", + "SODIMM_34", "SODIMM_36", "SODIMM_27", "SODIMM_28", + "", "", "", "", + "", "", "", "ENET_POWER", + "", "", "", "", + "ENET_nINT", "ENET_nRST", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "SODIMM_51", "SODIMM_57", "SODIMM_56", "SODIMM_52", + "SODIMM_53", "SODIMM_54", "SODIMM_55", "SODIMM_15", + "SODIMM_45", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "SODIMM_103", "SODIMM_104", "SODIMM_105", "SODIMM_106", + "SODIMM_107", "SODIMM_112", "SODIMM_108", "SODIMM_109", + "SODIMM_95", "SODIMM_110", "SODIMM_96", "SODIMM_97", + "SODIMM_98", "SODIMM_99", "SODIMM_113", "SODIMM_114", + "SODIMM_115", "SODIMM_101", "SODIMM_100", "SODIMM_77", + "SODIMM_72", "SODIMM_73", "SODIMM_74", "SODIMM_75", + "SODIMM_76", "SODIMM_43", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "SODIMM_178", "SODIMM_180", "SODIMM_184", "SODIMM_185", + "SODIMM_186", "SODIMM_187", "SODIMM_188", "SODIMM_189", + "SODIMM_190", "SODIMM_191", "SODIMM_179", "SODIMM_181", + "SODIMM_192", "SODIMM_193", "SODIMM_194", "SODIMM_195", + "SODIMM_196", "SODIMM_197", "SODIMM_198", "SODIMM_199", + "SODIMM_182", "SODIMM_79", "SODIMM_78", "SODIMM_84", + "SODIMM_87", "SODIMM_86", "SODIMM_85", "SODIMM_83", + "SODIMM_81", "SODIMM_80", "SODIMM_90", "SODIMM_93"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_92", "SODIMM_91", "SODIMM_89", "SODIMM_144", + "SODIMM_143", "SODIMM_146", "SODIMM_68", "SODIMM_67", + "SODIMM_70", "SODIMM_69", "SODIMM_48", "SODIMM_46", + "SODIMM_47", "SODIMM_44", "PMIC_SCL", "PMIC_SDA", + "SODIMM_41", "SODIMM_40", "SODIMM_148", "SODIMM_149", + "SODIMM_150", "SODIMM_151", "SODIMM_60", "SODIMM_59", + "SODIMM_64", "SODIMM_63", "SODIMM_62", "SODIMM_61", + "SODIMM_66", "SODIMM_65", "", ""; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + rohm,reset-snvs-powered; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <780000>; + regulator-name = "buck1"; + regulator-ramp-delay = <1250>; + }; + + reg_vdd_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <805000>; + regulator-name = "buck2"; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <950000>; + rohm,dvs-idle-voltage = <810000>; + }; + + BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <805000>; + regulator-name = "buck3"; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "buck4"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1700000>; + regulator-name = "buck5"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <(1350000 + 100000)>; + regulator-min-microvolt = <(1350000 - 67000)>; + regulator-name = "buck6"; + rohm,fb-pull-up-microvolt = <0>; + rohm,feedback-pull-up-r1-ohms = <2200>; + rohm,feedback-pull-up-r2-ohms = <499>; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1980000>; + regulator-min-microvolt = <1620000>; + regulator-name = "ldo1"; + }; + + LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <760000>; + regulator-name = "ldo2"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <1710000>; + regulator-name = "ldo3"; + }; + + LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <855000>; + regulator-name = "ldo4"; + }; + + LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "ldo5"; + }; + + LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1260000>; + regulator-min-microvolt = <1140000>; + regulator-name = "ldo6"; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ethphy_int: etnphy-intgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_ethphy_rst: etnphy-rstgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK + (MX8MM_FSEL_FAST | MX8MM_SION) + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_reg_3v3_etn: reg-3v3-etngrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + status = "okay"; +}; From 3ed539cb892f2d398543f78a0c94dbe1391bd245 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Mon, 16 Feb 2026 14:07:11 +0100 Subject: [PATCH 037/139] arm64: dts: freescale: Add the GOcontroll Moduline IV The Moduline IV is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. Features: - up to 8 Moduline IO modules - 4 CAN busses - 1 LIN bus - 1 Ethernet - 4 RGB leds - optional Wi-Fi/Bluetooth - optional 4G/GPS Signed-off-by: Maud Spierings Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mm-tx8m-1610-moduline-iv-306-d.dts | 799 ++++++++++++++++++ 2 files changed, 800 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dc1a8911035a..a89737bc18f5 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -158,6 +158,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts new file mode 100644 index 000000000000..6cc04aa90f21 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts @@ -0,0 +1,799 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings + */ + +/dts-v1/; + +#include + +#include "imx8mm-tx8m-1610.dtsi" + +/ { + chassis-type = "embedded"; + compatible = "gocontroll,moduline-iv-306-d", "karo,tx8m-1610", "fsl,imx8mm"; + hardware = "Moduline IV V3.06-D"; + model = "GOcontroll Moduline IV"; + + aliases { + spi0 = &ecspi2; /* spidev number compatibility */ + spi1 = &ecspi3; /* spidev number compatibility */ + spi2 = &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_3v3_m2: regulator-3v3-m2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_m2>; + pinctrl-names = "default"; + power-supply = <®_6v4>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3-m.2"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + power-supply = <®_6v4>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <6400000>; + regulator-min-microvolt = <6400000>; + regulator-name = "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can1_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 17 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can2_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + reg_can3_stby: regulator-can3-stby { + compatible = "regulator-fixed"; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can3_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can3-stby"; + }; + + reg_can4_stby: regulator-can4-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 8 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can4_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can4-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_wl_reg>; + pinctrl-names = "default"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; + reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI 2 */ +&ecspi1 { + cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>, + <&gpio1 0 GPIO_ACTIVE_LOW>, + <&gpio5 2 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio3 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + slot-number = <3>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + slot-number = <4>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@2 { + compatible = "gocontroll,moduline-module-slot"; + reg = <2>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + slot-number = <5>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@3 { + compatible = "gocontroll,moduline-module-slot"; + reg = <3>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number = <6>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + adc@4 { + compatible = "microchip,mcp3004"; + reg = <4>; + spi-max-frequency = <2300000>; + vref-supply = <®_vdd_3v3>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>, + <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio3 2 GPIO_ACTIVE_LOW>, + <&gpio5 25 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + slot-number = <7>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number = <8>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + can@2 { + compatible = "microchip,mcp25625"; + reg = <2>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can1>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can1_stby>; + }; + + can@3 { + compatible = "microchip,mcp25625"; + reg = <3>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can2>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can2_stby>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>, + <&gpio5 5 GPIO_ACTIVE_LOW>, + <&gpio5 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + slot-number = <1>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + slot-number = <2>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + can@2 { + compatible = "microchip,mcp25625"; + reg = <2>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can3>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can3_stby>; + }; + + can@3 { + compatible = "microchip,mcp25625"; + reg = <3>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can4>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can4_stby>; + }; +}; + +&gpu_2d { + status = "disabled"; +}; + +&gpu_3d { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + vled-supply = <®_6v4>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = ; + label = "case-led1"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + label = "case-led2"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + label = "case-led3"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = ; + label = "case-led4"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can3: can3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can3_reg: can3reggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can4: can4grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can4_reg: can4reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 + MX8MM_DSE_X1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_reg_m2: reg-m2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio3>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + max-speed = <921600>; + pinctrl-0 = <&pinctrl_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_m2>; + vddio-supply = <®_3v3_m2>; + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + sd-uhs-sdr25; + vmmc-supply = <®_3v3_m2>; + status = "okay"; + + wifi@1 { + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wl_int>; + pinctrl-names = "default"; + interrupt-names = "host-wake"; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type = "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status = "disabled"; +}; + +&vpu_g1 { + status = "disabled"; +}; + +&vpu_g2 { + status = "disabled"; +}; + +&wdog1 { + status = "okay"; +}; From 081a4a78b6e64e2bac5a18bc6a548bc80cd8ae44 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Mon, 16 Feb 2026 14:07:12 +0100 Subject: [PATCH 038/139] arm64: dts: freescale: Add the GOcontroll Moduline Mini The Moduline Mini is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. Features: - up to 4 Moduline IO modules - 2 CAN busses - 1 Ethernet - 4 RGB leds - 1 3D accelerometer - optional Wi-Fi/Bluetooth - optional 4G/GPS Signed-off-by: Maud Spierings Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mm-tx8m-1610-moduline-mini-111.dts | 687 ++++++++++++++++++ 2 files changed, 688 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a89737bc18f5..25793aa7c0ab 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts new file mode 100644 index 000000000000..39b7d9077e8e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts @@ -0,0 +1,687 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings + */ + +/dts-v1/; + +#include + +#include "imx8mm-tx8m-1610.dtsi" + +/ { + chassis-type = "embedded"; + compatible = "gocontroll,moduline-mini-111", "karo,tx8m-1610", "fsl,imx8mm"; + hardware = "Moduline Mini V1.11"; + model = "GOcontroll Moduline Mini"; + + aliases { + spi0 = &ecspi2; /* spidev number compatibility */ + spi1 = &ecspi3; /* spidev number compatibility */ + spi2 = &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_3v3_comm: regulator-3v3-communication { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_comm>; + pinctrl-names = "default"; + power-supply = <®_6v4>; + /* also powers the cellular modem which can't vote on the regulator */ + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_comm"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + power-supply = <®_6v4>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <6400000>; + regulator-min-microvolt = <6400000>; + regulator-name = "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + gpio = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can1_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can2_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_wl_reg>; + pinctrl-names = "default"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio3 23 GPIO_ACTIVE_LOW>, + <&gpio3 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number = <3>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number = <4>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + adc@2 { + compatible = "microchip,mcp3004"; + reg = <2>; + spi-max-frequency = <2300000>; + vref-supply = <®_vdd_3v3>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 9 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + status = "okay"; + + can@0 { + compatible = "microchip,mcp25625"; + reg = <0>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can1>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can1_stby>; + }; + + can@1 { + compatible = "microchip,mcp25625"; + reg = <1>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can2>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can2_stby>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>, + <&gpio1 2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + slot-number = <1>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + slot-number = <2>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; +}; + +&gpu_2d { + status = "disabled"; +}; + +&gpu_3d { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + vled-supply = <®_6v4>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = ; + label = "case-led1"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + label = "case-led2"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + label = "case-led3"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = ; + label = "case-led4"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + }; + + accelerometer@18 { + compatible = "st,lis2dw12"; + reg = <0x18>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>, <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&pinctrl_lis_int>; + pinctrl-names = "default"; + vddio-supply = <®_vdd_3v3>; + vdd-supply = <®_vdd_3v3>; + }; + + humidity-sensor@5f { + compatible = "st,hts221"; + reg = <0x5f>; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&pinctrl_hts_int>; + pinctrl-names = "default"; + vdd-supply = <®_vdd_3v3>; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 + MX8MM_DSE_X1 + >; + }; + + pinctrl_hts_int: htsintgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_lis_int: lisintgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_reg_comm: reg_commgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + MX8MM_DSE_X1 + >; + }; + + pinctrl_sysfs_gpios: sysfsgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 + MX8MM_DSE_X1 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio3>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + max-speed = <921600>; + pinctrl-0 = <&pinctrl_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_comm>; + vddio-supply = <®_3v3_comm>; + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + sd-uhs-sdr25; + vmmc-supply = <®_3v3_comm>; + status = "okay"; + + wifi@1 { + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wl_int>; + pinctrl-names = "default"; + interrupt-names = "host-wake"; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type = "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status = "disabled"; +}; + +&vpu_g1 { + status = "disabled"; +}; + +&vpu_g2 { + status = "disabled"; +}; + +&wdog1 { + status = "okay"; +}; From a251f9ed77f01f16adaaa1b3d2f568fc1b5acbfd Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 13 Jan 2026 20:06:08 +0100 Subject: [PATCH 039/139] arm64: dts: imx93-phyboard-segin: Add peb-av-02 overlay Add overlay for Audio-Video module PEB-AV-02. Add support for panel display, capacitive touchscreen and backlight. The pwm-backlight uses the GPIO based PWM implementation for now. Switch to the FlexIO PWM support once available. Signed-off-by: Andrej Picej [rework commit message, use local regulator, remove compatible] Signed-off-by: Primoz Fiser Signed-off-by: Christian Hemp [m.felsch@pengutronix.de: cleanup downstream commit] Tested-by: Primoz Fiser Signed-off-by: Marco Felsch Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx93-phyboard-segin-peb-av-02.dtso | 146 ++++++++++++++++++ 2 files changed, 148 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 25793aa7c0ab..e0738525d37e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -428,12 +428,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb imx93-phyboard-nash-jtag-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-jtag.dtbo imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo imx93-phyboard-nash-pwm-fan-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-pwm-fan.dtbo +imx93-phyboard-segin-peb-av-02-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-av-02.dtbo imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-jtag.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-pwm-fan.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-02.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso new file mode 100644 index 000000000000..af330756abfd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Copyright (C) 2025 Pengutronix + * + * Author: Andrej Picej + * Author: Marco Felsch + */ + +#include +#include +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + power-supply = <®_vcc_3v3_con>; + pwms = <&pwm7 0 5000000 0>; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + + backlight = <&backlight>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_vcc_3v3_con>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_to_panel>; + }; + }; + }; + + /* TODO: Convert to FlexIO PWM once supported */ + pwm7: pwm-7 { + compatible = "pwm-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + #pwm-cells = <3>; + }; + + reg_vcc_3v3_con: regulator-vcc-3v3-con { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_CON"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; +}; + +&dpi_bridge { + status = "okay"; +}; + +&dpi_to_panel { + remote-endpoint = <&panel_in>; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <332600000>; + status = "okay"; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + vcc-supply = <®_vcc_3v3_con>; + iovcc-supply = <®_vcc_3v3_con>; + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + wakeup-source; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x50e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x50e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x50e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x50e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x50e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x50e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x50e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x50e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x50e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x51e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x50e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x50e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x50e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x50e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x50e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x50e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x506 + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x506 + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x506 + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x506 + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x506 + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x506 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x11e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x1133e + >; + }; +}; From 058c53476dde9937877e93d964a283bbb5e1e4c7 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Fri, 20 Feb 2026 11:36:16 +0100 Subject: [PATCH 040/139] arm64: dts: imx8mp-kontron: Fix touch reset configuration on DL devices The reset signal needs a pullup, but there is no hardware pullup. As a workaround, enable the internal pullup to fix the touchscreen. As this deviates from the default generic GPIO settings in the OSM devicetree, add a new node for the touch pinctrl and redefine the generic gpio1 pinctrl. Fixes: 946ab10e3f40f ("arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board") Signed-off-by: Frieder Schrempf Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-kontron-dl.dtso | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso index a3cba41d2b53..7131e9a499ae 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso @@ -77,6 +77,8 @@ &i2c1 { touchscreen@5d { compatible = "goodix,gt928"; reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; interrupt-parent = <&gpio1>; interrupts = <6 8>; irq-gpios = <&gpio1 6 0>; @@ -98,6 +100,16 @@ &lvds_bridge { status = "okay"; }; +/* redefine to remove touch controller GPIOs */ +&pinctrl_gpio1 { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x19 /* GPIO_A_0 */ + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x19 /* GPIO_A_1 */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 /* GPIO_A_2 */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19 /* GPIO_A_5 */ + >; +}; + &pwm1 { status = "okay"; }; @@ -108,4 +120,11 @@ pinctrl_panel_stby: panelstbygrp { MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x19 >; }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 + >; + }; }; From d2ce84eecf081056b1d18d7524de52f849281ba7 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Fri, 20 Feb 2026 11:36:17 +0100 Subject: [PATCH 041/139] arm64: dts: imx8mp-kontron: Drop vmmc-supply to fix SD card on SMARC eval carrier The SMARC evaluation carrier provides an SD card power switch that complies with the OSM standard definition. The OSM base devicetree already describes this correctly. Stop overriding the vmmc-supply in the board devicetree and rely on the definition from the OSM base DTS instead to fix the power supply configuration for the SD card. Fixes: 6fe1ced5ccab7 ("arm64: dts: Add support for Kontron i.MX8MP SMARC module and eval carrier") Signed-off-by: Frieder Schrempf Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts index 2173a36ff691..74d620dd06b7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts @@ -249,6 +249,5 @@ &usb3_phy1 { }; &usdhc2 { - vmmc-supply = <®_vdd_3v3>; status = "okay"; }; From 93190b6eab824454223e355477d7ef621d1d8dae Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Fri, 20 Feb 2026 11:36:19 +0100 Subject: [PATCH 042/139] arm64: dts: imx8mp-kontron: Use GPIO/IRQ defines in DL devicetree To make the code more readable, use the macros for the GPIO and IRQ settings. Signed-off-by: Frieder Schrempf Reviewed-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso index 7131e9a499ae..41a2bb74f156 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso @@ -7,6 +7,7 @@ /plugin/; #include +#include #include "imx8mp-pinfunc.h" &{/} { @@ -80,11 +81,11 @@ touchscreen@5d { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch>; interrupt-parent = <&gpio1>; - interrupts = <6 8>; - irq-gpios = <&gpio1 6 0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; AVDD28-supply = <®_vcc_panel>; VDDIO-supply = <®_vcc_panel>; - reset-gpios = <&gpio1 7 0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; }; From 713527940c8c4afcdf142e900f71d391bfe7d6a9 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 26 Feb 2026 14:02:20 +0100 Subject: [PATCH 043/139] arm64: dts: tqma8mpql-mba8mpxl: Configure multiple queues on eqos The MBa8MPxL mainboard has an integrated PHY connected to the EQOS ethernet controller which can support up to five queues. Configure these queues in the same manor as done on the imx8mp-evk. Setting DMA to threas mode is necessary to prevent FIFO overflows, see commit 0bc3e333a0c82 ("arm64: dts: imx8mp-evk: configure multiple queues on eqos") Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ad49bf85a04d..890d1e525a48 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -336,6 +336,9 @@ &eqos { pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; phy-mode = "rgmii-id"; phy-handle = <ðphy3>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { @@ -359,6 +362,70 @@ ethphy3: ethernet-phy@3 { interrupts = <3 IRQ_TYPE_LEVEL_LOW>; }; }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; }; &fec { From 6fb408d59b74dbb9a69a0f075c177eaed0c884f8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 26 Feb 2026 14:02:21 +0100 Subject: [PATCH 044/139] arm64: dts: tqma8mpql-mba8mp-ras314: Configure multiple queues on eqos The MBa8MP-RAS314 mainboard has an integrated PHY connected to the EQOS ethernet controller which can support up to five queues. Configure these queues in the same manor as done on the imx8mp-evk. Setting DMA to threas mode is necessary to prevent FIFO overflows, see commit 0bc3e333a0c82 ("arm64: dts: imx8mp-evk: configure multiple queues on eqos") Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../imx8mp-tqma8mpql-mba8mp-ras314.dts | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index b7f69c92b774..04f4c2fdf299 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -184,6 +184,9 @@ &eqos { pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <ðphy3>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { @@ -209,6 +212,70 @@ ethphy3: ethernet-phy@3 { ti,clk-output-sel = ; }; }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; }; &fec { From 3147e56028a4e7afff47ffd77e99178e7fe113f0 Mon Sep 17 00:00:00 2001 From: Wig Cheng Date: Thu, 26 Feb 2026 22:48:19 +0800 Subject: [PATCH 045/139] arm64: dts: freescale: add pixpaper display overlay for i.MX93 FRDM Add device tree overlay to support the MayQueen PixPaper e-paper display on the NXP i.MX93 FRDM board. The display is connected via LPSPI3 interface and uses GPIO pins for reset, busy and DC control. The overlay configures: - LPSPI3 pinmux for SPI communication (MOSI, MISO, CLK, CE0) - PixPaper display device with proper GPIO assignments - SPI frequency set to 1MHz for stable operation Enable Open-EP Community pixpaper-213-c support on NXP i.MX93. Signed-off-by: Wig Cheng Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++ .../freescale/imx93-11x11-frdm-pixpaper.dtso | 50 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e0738525d37e..0bea667e7e47 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -420,6 +420,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb + +imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm-pixpaper.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso new file mode 100644 index 000000000000..d220d7e07df2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Overlay for Mayqueen (Open-EP Community) pixpaper display + * support on NXP FRDM i.MX 93 Development Board + * + * Copyright (C) 2026 Wig Cheng + */ + +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&iomuxc { + pinctrl_epd_ctrl: epdctrlgrp { + fsl,pins = < + MX93_PAD_GPIO_IO05__GPIO2_IO05 0x31e /* DC pin */ + MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e /* RESET pin */ + MX93_PAD_GPIO_IO26__GPIO2_IO26 0x31e /* BUSY pin */ + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe /* SPI3 CE0 */ + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe /* SPI3 MISO */ + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe /* SPI3 MOSI */ + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe /* SPI3 CLK */ + >; + }; +}; + +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_lpspi3>, <&pinctrl_epd_ctrl>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "mayqueen,pixpaper"; + reg = <0>; + busy-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + dc-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <1000000>; + }; +}; From f1a26bc43c87813183220f1f7a067c3e39dde2d8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 26 Feb 2026 16:38:51 +0100 Subject: [PATCH 046/139] arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe IRQ mapping is already present. Add the missing DMA interrupt. This is similar to commit 0b4c46f9ad79c ("arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe") Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index bd6e0aa27efe..f2c94cdb682b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -20,8 +20,9 @@ pcie0: pciea: pcie@5f000000 { ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>, <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pciea_lpcg IMX_LPCG_CLK_6>, From 70ecea46d36b3b0ddcbe71f9cde8d0df00c11f87 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 26 Feb 2026 18:36:31 +0200 Subject: [PATCH 047/139] arm64: dts: imx8mp-hummingboard-pulse/cubox-m: fix vmmc gpio polarity Fix the polarity in vmmc regulator node for the gpio from active-high to active-low. This is a cosmetic change as regulator default to active-low unless property enable-active-high was also specified - ignoring the flag on gpio handle. Fixes: a009c0c66ecb ("arm64: dts: add description for solidrun imx8mp som and cubox-m") Fixes: 2a222aa2bee9 ("arm64: dts: add description for solidrun imx8mp hummingboard variants") Reviewed-by: Frank Li Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts | 2 +- .../boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts index 8290f187b79f..7bc213499f09 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts @@ -68,7 +68,7 @@ vmmc: regulator-mmc { regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; startup-delay-us = <250>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi index fa7cb9759d01..0b4e5f300eb1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi @@ -73,7 +73,7 @@ vmmc: regulator-mmc { regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; startup-delay-us = <250>; }; From 1d1d14d4253e6f373c247e67f3716768910be81e Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 26 Feb 2026 18:36:32 +0200 Subject: [PATCH 048/139] arm64: dts: imx8mp-hummingboard-pulse: fix mini-hdmi dsi port reference imx8mp.dtsi includes a default port@1 node with an empty placeholder endpoint intended for linking to a dsi bridge or panel. HummingBoard Pulse mini-hdmi dtsi described a new endpoint node with a different label attached. This duplicate label causes confusion and is suspected to also cause errors during dsi_attach. Remove the duplicate node and link to the one defined in soc dtsi. Further remove the unnecessary attach-bridge property. Fixes: 2a222aa2bee9 ("arm64: dts: add description for solidrun imx8mp hummingboard variants") Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../imx8mp-hummingboard-pulse-mini-hdmi.dtsi | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi index 46916ddc0533..0e5f4607c7c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi @@ -41,7 +41,7 @@ port@0 { reg = <0>; adv7535_from_dsim: endpoint { - remote-endpoint = <&dsim_to_adv7535>; + remote-endpoint = <&mipi_dsi_out>; }; }; @@ -71,11 +71,8 @@ &lcdif1 { &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; - - port@1 { - dsim_to_adv7535: endpoint { - remote-endpoint = <&adv7535_from_dsim>; - attach-bridge; - }; - }; +}; + +&mipi_dsi_out { + remote-endpoint = <&adv7535_from_dsim>; }; From 9117e20a36d005abb68e0e3f4ca0080eeacb71ca Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 26 Feb 2026 18:36:33 +0200 Subject: [PATCH 049/139] arm64: dts: imx8mp-sr-som: build dtbs with symbols for overlay support Build all dtbs based on SolidRun i.MX8MP SoM with symbols (adding -@ to dtc flags) to allow applying of device-tree overlays e.g. by the bootloader. The SoM has a basler camera connector that can be configured for a particular camera by device-tree overlay. By extension all boards based on this SoM have this connector and should support device-tree overlays. Reviewed-by: Frank Li Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0bea667e7e47..5e8156f90fd3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -225,6 +225,7 @@ imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp- dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb +DTC_FLAGS_imx8mp-cubox-m := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb @@ -236,9 +237,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb +DTC_FLAGS_imx8mp-hummingboard-mate := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb +DTC_FLAGS_imx8mp-hummingboard-pro := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb +DTC_FLAGS_imx8mp-hummingboard-pulse := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb +DTC_FLAGS_imx8mp-hummingboard-ripple := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb From bf68c18150efcd24b5b18522dd40700837af30e1 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Fri, 27 Feb 2026 09:58:37 +0800 Subject: [PATCH 050/139] arm64: dts: imx8mp-ab2: add support for NXP i.MX8MP audio board (version 2) i.MX Audio Board is a configurable and functional audio processing platform. Integrating a variety of audio input and output interfaces into the system, the i.MX Audio Board supports HDMI input, HDMI eARC, S/PDIF I/O, 2-ch ADC line-in, 24-ch DAC line-out and more. Based on these features, rich audio application cases can be realized. This is a basic device tree supporting with i.MX8M Plus SoC and Audio board (version 2). - Quad Cortex-A53 - 6GB LPDDR4 DRAM - PCA9450C PMIC with regulators - NXP PCAL6416 GPIO expanders - RGB LEDs via GPIO expander - I2C1, I2C2, I2C3 controllers - UART2 (console) and UART3 (with RTS/CTS) - USDHC3 (8-bit eMMC) - SNVS power key (onboard power button) - Three DAC (AK4458) - One ADC (AK5552) Squash Correct PAD settings (enable PUE and PU) for PMIC_nINT (GPIO1_IO3) to avoid irq storm. Signed-off-by: Viorel Suman Signed-off-by: Shengjiu Wang Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 912 +++++++++++++++++++ 2 files changed, 913 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-ab2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 5e8156f90fd3..c74e5b926917 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -219,6 +219,7 @@ imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8m dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-usbotg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ab2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-adpismarc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios.dtb imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-aristainetos3-helios-lvds.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts new file mode 100644 index 000000000000..dbbc0df0e3d1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2026 NXP + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + compatible = "fsl,imx8mp-ab2", "fsl,imx8mp"; + model = "NXP i.MX8MP SOM on AB2"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_gpio_led>; + pinctrl-names = "default"; + + status { + default-state = "on"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + label = "yellow:status"; + }; + }; + + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "akcodec"; + fsl,mclk-equal-bclk; + + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + + cpu { + sound-dai = <&sai1>; + }; + }; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-card"; + model = "ak5552-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "akcodec"; + fsl,mclk-equal-bclk; + + codec { + sound-dai = <&ak5552>; + }; + + cpu { + sound-dai = <&sai3>; + }; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + model = "audio-hdmi"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + device_type = "memory"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&aud2htx { + status = "okay"; +}; + +&dsp { + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "okay"; +}; + +&dsp_reserved { + status = "okay"; +}; + +&easrc { + #sound-dai-cells = <0>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&flexspi { + pinctrl-0 = <&pinctrl_flexspi0>; + pinctrl-names = "default"; + status = "okay"; + + mt25qu256aba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-0 = <&pinctrl_hdmi>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-names = "default"; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-names = "default"; + status = "okay"; + + pca6408: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-names = "default"; + status = "okay"; + + ak4458_1: audio-codec@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + sound-name-prefix = "0"; + }; + + ak4458_2: audio-codec@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + sound-name-prefix = "1"; + }; + + ak4458_3: audio-codec@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + }; + + ak5552: audio-codec@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_LOW>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + pinctrl-names = "default"; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x10 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6 + MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6 + MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6 + MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6 + MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6 + MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6 + MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_xcvr: xcvrgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0xd6 + MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 + MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 + >; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&micfil { + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm4 { + pinctrl-0 = <&pinctrl_pwm4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sai1 { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-names = "default"; + fsl,dataline = <2 0xff 0xff>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-asynchronous; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_xcvr>; + pinctrl-names = "default"; + status = "okay"; +}; From 5aee26a0e7ae87136c13034cf917333eba92f49d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 26 Feb 2026 15:19:47 -0500 Subject: [PATCH 051/139] arm64: dts: imx8mp-beacon: remove fallback ethernet-phy-ieee802.3-c22 Remove the fallback compatible string "ethernet-phy-ieee802.3-c22" from the Ethernet PHY node to fix below CHECK_DTB warning: arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: ethernet-phy@3 (ethernet-phy-id0022.1640): compatible: ['ethernet-phy-id0022.1640', 'ethernet-phy-ieee802.3-c22'] is too long from schema $id: http://devicetree.org/schemas/net/micrel,gigabit.yaml Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts | 3 +-- arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index 31c33acb560c..385aa6bae520 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -266,8 +266,7 @@ mdio { #size-cells = <0>; ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <3>; reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi index 6a62cb32e22e..1007f7db85e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi @@ -60,8 +60,7 @@ mdio { #size-cells = <0>; ethphy0: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <3>; reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio1>; From bef7b4f58d4a93e6e4d37e46b6c5dea536d10aee Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Fri, 27 Feb 2026 10:14:05 +0800 Subject: [PATCH 052/139] arm64: dts: imx93-9x9-qsb: Add ontat,kd50g21-40nt-a1 panel Support ontat,kd50g21-40nt-a1 DPI panel on i.MX93 9x9 QSB. The panel connects with the QSB board through Adafruit DPI Display Kippah adapter board[1]. Link: https://learn.adafruit.com/adafruit-dpi-display-kippah-ttl-tft/downloads [1] Signed-off-by: Liu Ying Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso | 110 ++++++++++++++++++ 2 files changed, 112 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c74e5b926917..a6fe56bb93aa 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -421,8 +421,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo +imx93-9x9-qsb-ontat-kd50g21-40nt-a1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso new file mode 100644 index 000000000000..d167c9fc3b8f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx93-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + }; + + panel { + compatible = "ontat,kd50g21-40nt-a1"; + backlight = <&backlight>; + power-supply = <®_rpi_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_to_panel>; + }; + }; + }; +}; + +&dpi_bridge { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dpi_to_panel: endpoint { + remote-endpoint = <&panel_in>; + bus-width = <18>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&pcal6524 { + /* + * exp-sel-hog has property 'output-low' while DT overlay doesn't + * support /delete-property/. Both 'output-low' and 'output-high' + * will exist under hog nodes if DT overlay file sets 'output-high'. + * Workaround is to disable this hog and create new hog with + * 'output-high'. + */ + exp-sel-hog { + status = "disabled"; + }; + + exp-high-sel-hog { + gpio-hog; + gpios = <22 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&sai3 { + /* disable due to GPIO12 and GPIO17~20 pin conflicts with LCDIF */ + status = "disabled"; +}; From b8d785a9f360abcd6a6f8f10a2adf222f8494d66 Mon Sep 17 00:00:00 2001 From: Nora Schiffer Date: Mon, 2 Mar 2026 09:45:48 +0100 Subject: [PATCH 053/139] arm64: dts: freescale: imx8mp-tqma8mpql-mba8mp-ras314: fix UART1 RTS/CTS muxing UART1 operates in DCE mode, but the RTS/CTS pins were incorrectly configured using the DTE pinmux setting. Correct the pinmux to match DCE mode. Switching the RTS and CTS signals is fine for this board, as UART1 is routed to a pin header. Existing functionality is unaffected, as RTS/CTS could never have worked with the incorrect pinmux. Fixes: ddabb3ce3f90 ("arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314") Signed-off-by: Nora Schiffer Reviewed-by: Alexander Stein Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 04f4c2fdf299..94e2a7df3556 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -915,8 +915,8 @@ pinctrl_tlv320aic3x04: tlv320aic3x04grp { pinctrl_uart1: uart1grp { fsl,pins = , , - , - ; + , + ; }; pinctrl_uart1_gpio: uart1gpiogrp { From 95f56afadb0905e2181f3e966b4e5173780a05a6 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Mon, 2 Mar 2026 15:38:04 +0200 Subject: [PATCH 054/139] arm64: dts: imx8mp: Make MX8MP_I2C_DEFAULT independent on drive strength Currently MX8MP_I2C_DEFAULT macro includes a fixed drive strength (MX8MP_DSE_X6) thus limiting its use to only I2C pins that require X6 drive. There are many pinctrl configurations for I2C that use different drive strength while still using the common I2C default configurations (pull-up, Schmitt input, pull enable, SION). So make the MX8MP_I2C_DEFAULT macro more flexible and reusable by removing DSE_X6 drive strength from it's definition but add or it in all places it is necessary. Reviewed-by: Maud Spierings Signed-off-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 2 +- .../imx8mp-tx8p-ml81-moduline-display-106.dts | 16 ++++++++-------- .../boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 8 ++++---- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h index 16f5899de415..26e7a9428c4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -36,7 +36,7 @@ /* long defaults */ #define MX8MP_USDHC_DATA_DEFAULT (MX8MP_FSEL_FAST | MX8MP_PULL_UP | \ MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) -#define MX8MP_I2C_DEFAULT (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | \ +#define MX8MP_I2C_DEFAULT (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | \ MX8MP_PULL_ENABLE | MX8MP_SION) /* diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts index 399230144ce3..87b20b856458 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts @@ -302,36 +302,36 @@ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c2_gpio: i2c2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c4_gpio: i2c4-gpiogrp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi index 761ee046eb72..bf49ae942d41 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi @@ -425,18 +425,18 @@ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c1_gpio: i2c1-gpiogrp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; From 2b5b97cd3978f230ee57b1d1b6abbf0f984e466e Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Mon, 2 Mar 2026 15:38:05 +0200 Subject: [PATCH 055/139] arm64: dts: imx8mp-frdm: Use symbolic macros for IOMUXC_SW_PAD_CTL_PAD Currently, in order to configure IOMUXC_SW_PAD_CTL_PAD a magic raw value is written in this register. This makes code not obvious to read and modify. Use symbolic macros instead of the magic values to improve code readability. Signed-off-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 132 +++++++++++------- 1 file changed, 84 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts index 55690f5e53d7..d69d78fed4e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -252,104 +252,140 @@ &usdhc3 { &iomuxc { pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) >; }; pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 + (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; pinctrl_pcal6416_0_int: pcal6416-0-int-grp { fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146 + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) >; }; pinctrl_pcal6416_1_int: pcal6416-1-int-grp { fsl,pins = < - MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146 + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 - MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; }; From 5bc539bb19b7bfc1273018dde63215bf5f2c2810 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 5 Mar 2026 12:10:36 +0100 Subject: [PATCH 056/139] arm64: dts: tqma9352-mba93xx*: Change Ethernet PHY IRQ to IRQ_TYPE_LEVEL_LOW Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 4760d07ea24b..9108181e6592 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -242,7 +242,7 @@ ethphy_eqos: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; @@ -275,7 +275,7 @@ ethphy_fec: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 8a88c98ac05a..a78bbc46c59b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -172,7 +172,7 @@ ethphy_eqos: ethernet-phy@0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos_phy>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; reset-assert-us = <500000>; reset-deassert-us = <50000>; @@ -205,7 +205,7 @@ ethphy_fec: ethernet-phy@0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec_phy>; interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; reset-assert-us = <500000>; reset-deassert-us = <50000>; From 5397ea118c111f1cb5b4bd7dac6503365d79f6c3 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 5 Mar 2026 12:10:37 +0100 Subject: [PATCH 057/139] arm64: dts: tqma9352-mba91xxca: Change Ethernet PHY IRQ to IRQ_TYPE_LEVEL_LOW Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts index 2673d9dccbf4..737326ba1b2a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts @@ -232,7 +232,7 @@ ethphy_eqos: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; @@ -265,7 +265,7 @@ ethphy_fec: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; From 53a0485304f11f5371fddf9fb06b95268154bf82 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 5 Mar 2026 17:42:22 +0100 Subject: [PATCH 058/139] arm64: dts: imx91: Remove TMU's superfluous sensor ID Currently a sensor ID is added to the reference, but thermal-sensor@44482000 has #thermal-sensor-cells = <0>, so parsing fails. This also has the effect that other hwmon sensors (jc42) fail to probe. Fix this by removing the superfluous sensor ID. Fixes: f0ed0e844452 ("arm64: dts: imx91: Add thermal-sensor and thermal-zone support") Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi index f075592bfc01..d63569b39bbc 100644 --- a/arch/arm64/boot/dts/freescale/imx91.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -11,7 +11,7 @@ thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; - thermal-sensors = <&tmu 0>; + thermal-sensors = <&tmu>; trips { cpu_alert: cpu-alert { From 8c021406cbbf89332d21daf8882f26af98362f13 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Mon, 9 Mar 2026 18:08:06 +0800 Subject: [PATCH 059/139] arm64: dts: imx94: add USB nodes add USB2.0, USB3.0 controller and USB phy nodes. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index d2f31c8caf6e..38488147a3ef 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -139,6 +139,13 @@ timer { arm,no-tick-in-suspend; }; + usbphynop: usbphynop { + compatible = "usb-nop-xceiv"; + clocks = <&scmi_clk IMX94_CLK_HSIO>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + gic: interrupt-controller@48000000 { compatible = "arm,gic-v3"; reg = <0 0x48000000 0 0x10000>, @@ -1223,6 +1230,60 @@ wdog3: watchdog@49220000 { }; }; + usb3: usb@4c100000 { + compatible = "nxp,imx94-dwc3", "nxp,imx8mp-dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>, + <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + reg-names = "core", "blkctl", "glue"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_24M>, + <&scmi_clk IMX94_CLK_32K>; + clock-names = "hsio", "bus_early", "ref", "suspend"; + interrupts = , + ; + interrupt-names = "dwc_usb3", "wakeup"; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + + usb3_phy: phy@4c1f0040 { + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; + reg = <0x0 0x4c1f0040 0x0 0x40>, + <0x0 0x4c1fc000 0x0 0x100>; + clocks = <&scmi_clk IMX94_CLK_HSIO>; + clock-names = "phy"; + #phy-cells = <0>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + status = "disabled"; + }; + + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + phys = <&usbphynop>; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbmisc: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x04>; + #index-cells = <1>; + }; + netc_blk_ctrl: system-controller@4ceb0000 { compatible = "nxp,imx94-netc-blk-ctrl"; reg = <0x0 0x4ceb0000 0x0 0x10000>, From ae823891de84c2a03751094dbaafae5c2b7c16b9 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Mon, 9 Mar 2026 18:08:07 +0800 Subject: [PATCH 060/139] arm64: dts: imx943-evk: add Type-C and USB related nodes Add Type-C and USB related nodes. There are two Type-C ports, one is USB2 only and another is USB3. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 100 +++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index c8ceabe3d923..1d834379f602 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx943.dtsi" +#include / { compatible = "fsl,imx943-evk", "fsl,imx94"; @@ -230,6 +231,48 @@ pca9670_i2c3: gpio@23 { gpio-controller; }; + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + pca9548_i2c3: i2c-mux@77 { compatible = "nxp,pca9548"; reg = <0x77>; @@ -286,6 +329,14 @@ wm8962: codec@1a { SPKVDD1-supply = <®_audio_pwr>; SPKVDD2-supply = <®_audio_pwr>; }; + + ptn5150: tcpc@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + interrupt-parent = <&pcal6408_i2c3_u172>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; }; i2c@5 { @@ -680,6 +731,12 @@ IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0 0x31e >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + IMX94_PAD_GPIO_IO44__GPIO3_IO12 0x30e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e @@ -821,6 +878,49 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe }; }; +&usb2 { + dr_mode = "otg"; + disable-over-current; + adp-disable; + hnp-disable; + srp-disable; + samsung,picophy-dc-vol-level-adjust = <10>; + status = "okay"; +}; + +&usb3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; From ca2932ae84f47da0fc0963fd83746b47933151eb Mon Sep 17 00:00:00 2001 From: Eduard Bostina Date: Mon, 9 Mar 2026 20:15:23 +0200 Subject: [PATCH 061/139] arm64: dts: imx8mp-dhcom-pdk3: Use symbolic macro for IOMUXC_SAI2_TXC__GPIO4_IO25 Currently, in order to configure IOMUXC_SAI2_TXC__GPIO4_IO25 a magic raw value is written in this register. This makes the code not obvious to read and modify. Use the MX8MP_SION symbolic macro instead of the magic value to improve code readability. Signed-off-by: Eduard Bostina Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index ef012e8365b1..6ad824a7e07e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -345,7 +345,7 @@ &pinctrl_dhcom_l pinctrl_ptn5150: ptn5150grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000 + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 MX8MP_SION >; }; }; From b6219083012756cd77966caf1c2b408178ee5a79 Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Wed, 11 Mar 2026 09:11:53 +0100 Subject: [PATCH 062/139] arm64: dts: freescale: Add NXP S32N79 SoC support Add device tree support for the NXP S32N79 automotive SoC [1]. The S32N79 features eight Arm Cortex-A78AE cores organized in four dual-core clusters, with a three-level cache hierarchy (L1/L2 per core, L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3 for IOMMU functionality. On S32N79 SoC, peripherals are organized into subsystems, such as: - CIS (Coherent Interconnect Subsystem) - COSS (Connectivity Subsystem) - FSS (Foundation Subsystem) This initial support includes basic peripherals: - GICv3, SMMUv3 from CIS Subsystem - PL011 UARTs and IRQ steering controller from COSS Subsystem - uSDHC from FSS Subsystem Clock and Pin multiplexing settings for the chip are managed over SCMI. [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Co-developed-by: Andra-Teodora Ilie Signed-off-by: Andra-Teodora Ilie Co-developed-by: Andrei Cherechesu Signed-off-by: Andrei Cherechesu Signed-off-by: Ciprian Marian Costea Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32n79.dtsi | 362 ++++++++++++++++++++++ 1 file changed, 362 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32n79.dtsi diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi new file mode 100644 index 000000000000..94ab58783fdc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * NXP S32N79 SoC + * + * Copyright 2026 NXP + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cis-bus { + compatible = "simple-bus"; + ranges = <0x4f200000 0x0 0x4f200000 0xc00000>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@4f200000 { + compatible = "arm,gic-v3"; + reg = <0x4f200000 0x10000>, /* GIC Dist */ + <0x4f260000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + /* GICR (RD_base + SGI_base) */ + ranges; + + its: msi-controller@4f240000 { + compatible = "arm,gic-v3-its"; + reg = <0x4f240000 0x20000>; + #msi-cells = <1>; + msi-controller; + }; + }; + + smmu: iommu@4fc00000 { + compatible = "arm,smmu-v3"; + reg = <0x4fc00000 0x200000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + dma-coherent; + status = "disabled"; + }; + }; + + coss-bus { + compatible = "simple-bus"; + ranges = <0x4a000000 0x0 0x4a000000 0xff0000>, + <0x4e000000 0x0 0x4e000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@4a030000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4a030000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <264>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart5: serial@4a060000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4a060000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <269>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart6: serial@4aa30000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4aa30000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <270>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart7: serial@4aa40000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4aa40000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <271>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + irqsteer_coss: interrupt-controller@4ed00000 { + compatible = "nxp,s32n79-irqsteer"; + reg = <0x4ed00000 0x10000>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clks 0x9a>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + status = "disabled"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_1>; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_2>; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_3>; + }; + + l3_0: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + l3_1: l3-cache1 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + l3_2: l3-cache2 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + l3_3: l3-cache3 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a78ae"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a78ae"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + cpu2: cpu@10000 { + compatible = "arm,cortex-a78ae"; + reg = <0x10000>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_1>; + }; + + cpu3: cpu@10100 { + compatible = "arm,cortex-a78ae"; + reg = <0x10100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_1>; + }; + + cpu4: cpu@20000 { + compatible = "arm,cortex-a78ae"; + reg = <0x20000>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_2>; + }; + + cpu5: cpu@20100 { + compatible = "arm,cortex-a78ae"; + reg = <0x20100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_2>; + }; + + cpu6: cpu@30000 { + compatible = "arm,cortex-a78ae"; + reg = <0x30000>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_3>; + }; + + cpu7: cpu@30100 { + compatible = "arm,cortex-a78ae"; + reg = <0x30100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_3>; + }; + }; + + firmware { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_shbuf>; + arm,smc-id = <0xc20000fe>; + status = "okay"; + + clks: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + fss-bus { + compatible = "simple-bus"; + ranges = <0x5b490000 0x0 0x5b490000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usdhc0: mmc@5b490000 { + compatible = "nxp,s32n79-usdhc"; + reg = <0x5b490000 0x1000>; + interrupts = ; + clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + status = "disabled"; + }; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From cb7b1131885b6a1ee2a60969d433d66069151bb5 Mon Sep 17 00:00:00 2001 From: Ciprian Marian Costea Date: Wed, 11 Mar 2026 09:11:54 +0100 Subject: [PATCH 063/139] arm64: dts: freescale: Add NXP S32N79-RDB board support Add device tree support for the NXP S32N79 Reference Design Board (RDB) [1]. The S32N79-RDB enables the following peripherals: - PL011 UART controllers (uart0, uart5, uart6, uart7) - uSDHC controller - IRQ steering controller The board has 32GB of DRAM memory with 28GB usable and 4GB reserved for ECC logic. [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Co-developed-by: Andra-Teodora Ilie Signed-off-by: Andra-Teodora Ilie Signed-off-by: Ciprian Marian Costea Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/s32n79-rdb.dts | 70 ++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32n79-rdb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a6fe56bb93aa..bae24b53bce6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -519,4 +519,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb +dtb-$(CONFIG_ARCH_S32) += s32n79-rdb.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts new file mode 100644 index 000000000000..1feccd61258e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2026 NXP + * + * NXP S32N79 Reference Design Board (S32N79-RDB) + */ + +/dts-v1/; +#include "s32n79.dtsi" + +/ { + compatible = "nxp,s32n79-rdb", "nxp,s32n79"; + model = "NXP S32N79-RDB"; + + aliases { + serial0 = &uart0; + serial1 = &uart5; + serial2 = &uart6; + serial3 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + scmi_shbuf: memory@93000000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x93000000 0x0 0x80>; + no-map; + }; + }; + + memory@80000000 { + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x88 0x00000000 0x03 0x40000000>, + <0xc0 0x00000000 0x03 0x40000000>; + device_type = "memory"; + }; +}; + +&irqsteer_coss { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&usdhc0 { + disable-wp; + no-sdio; + status = "okay"; +}; From 496c73bd62cc451030c763aa6f8c352273a1f3a9 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:02:20 +0100 Subject: [PATCH 064/139] arm64: dts: imx8mp-tqma8mpql-mba8mpxl-g133han01: Remove compatible from overlay Override of board compatible is unexpected, especially when the same dtso override difference mainboard. So remove it and update the copyright year. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso index 5058cd9409c7..129b02a69ccf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2023 TQ-Systems GmbH , + * Copyright (c) 2023-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; -}; - &backlight_lvds { status = "okay"; }; From 793b851ac90fff31fc6628a8582520fc65733122 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:02:21 +0100 Subject: [PATCH 065/139] arm64: dts: imx8mp-tqma8mpql-mba8mpxl-tm070jvhg33: Remove compatible from overlay Override of board compatible is unexpected, especially when the same dtso override difference mainboard. So remove it and update the copyright year. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso index ea44d605342b..f6aaad91d7f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022 TQ-Systems GmbH , + * Copyright (c) 2022-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -8,10 +8,6 @@ /dts-v1/; /plugin/; -&{/} { - compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; -}; - &backlight_lvds { status = "okay"; }; From 4aa57a1c8eb6cd5ee7e53bb76813ddd788d0d14f Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:02:22 +0100 Subject: [PATCH 066/139] arm64: dts: imx8mq-tqma8mq-mba8mx-tm070jvhg33: Remove compatible from overlay Override of board compatible is unexpected, especially when the same dtso override difference mainboard. So remove it and update the copyright year. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso index 306977d6ba0c..78f24f72cc69 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2019-2023 TQ-Systems GmbH , + * Copyright (c) 2019-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq"; -}; - &backlight_lvds { status = "okay"; }; From 404ef04083541fb5e052f2e32aa6f470666558d0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:02:23 +0100 Subject: [PATCH 067/139] arm64: dts: imx8mn-tqma8mqnl-mba8mx-tm070jvhg33: Remove compatible from overlay Override of board compatible is unexpected, especially when the same dtso override difference mainboard. So remove it and update the copyright year. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso index 29235e390a5d..0f4cf1855bf3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; -}; - &backlight_lvds { status = "okay"; }; From d5b16c79260d88fae73d0538cbb4826aa11e8bf0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:02:24 +0100 Subject: [PATCH 068/139] arm64: dts: imx8mm-tqma8mqml-mba8mx-tm070jvhg33: Remove compatible from overlay Override of board compatible is unexpected, especially when the same dtso override difference mainboard. So remove it and update the copyright year. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso index e44249c6d8a0..e5425653ea7e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; -}; - &backlight_lvds { status = "okay"; }; From 6b7a9871e171e374d208822a02f02aa9d9a4d102 Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 3 Mar 2026 22:01:07 +0100 Subject: [PATCH 069/139] arm64: dts: freescale: imx95-toradex-smarc: Support Cortex M7 Enable Cortex M7, the vring nodes, a mailbox and reserve DDR memory for the M7. The remoteproc framework is so capable to load and run the M7 firmware. Signed-off-by: Emanuele Ghidoli Signed-off-by: Frank Li --- .../dts/freescale/imx95-toradex-smarc.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index f64c05dc50f8..7a73958f6eec 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -144,6 +144,14 @@ reg_wifi_en: regulator-wifi-en { startup-delay-us = <2000>; }; + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -156,6 +164,42 @@ linux_cma: linux,cma { alloc-ranges = <0 0x80000000 0 0x7f000000>; linux,cma-default; }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; }; }; @@ -571,6 +615,10 @@ &lpuart3 { pinctrl-0 = <&pinctrl_uart3>; }; +&mu7 { + status = "okay"; +}; + /* SMARC MDIO, shared between all ethernet ports */ &netc_emdio { pinctrl-names = "default"; From 6bacabb9580aeec6f22ea029c0060197a5e47f07 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:07:33 +0100 Subject: [PATCH 070/139] arm64: dts: imx93-tqma9352-mba91xxca: Add parallel display overlay Add support for CDTech S070SWV29HG-DC44 display on parallel interface X3 on MBa91xxCA. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++ ...93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso | 66 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index bae24b53bce6..b3fb319a491d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -455,6 +455,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb + +imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso new file mode 100644 index 000000000000..869e3ad1d828 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&backlight { + status = "okay"; +}; + +&display { + compatible = "cdtech,s070swv29hg-dc44"; + status = "okay"; +}; + +&dpi_bridge { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgbdisp>; + status = "okay"; +}; + +&dpi_to_panel { + remote-endpoint = <&panel_in>; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <333333333>; + status = "okay"; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&expander2 0 GPIO_ACTIVE_LOW>; + iovcc-supply = <®_3v3>; + vcc-supply = <®_3v3>; + gain = <20>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&panel_in { + remote-endpoint = <&dpi_to_panel>; +}; From 00ffd51cf5322bdce771acf07f95d5ce485410c0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:07:34 +0100 Subject: [PATCH 071/139] arm64: dts: imx93-tqma9352-mba91xxca: Add LVDS display overlay This adds support for Tianma TM070JVHG33 LVDS display on interface X11/X12 on MBa91xxCA. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...3-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso | 56 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b3fb319a491d..98711777e81d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -456,7 +456,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb +imx93-tqma9352-mba91xxca-lvds-tm070jvhg33-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..40a519e9c91e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include + +/dts-v1/; +/plugin/; + +&backlight { + status = "okay"; +}; + +&display { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; + +&dpi_bridge { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgbdisp>; + status = "okay"; +}; + +&dpi_to_panel { + remote-endpoint = <&lvds_encoder_input>; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <477400000>; + status = "okay"; +}; + +&lvds_encoder { + status = "okay"; +}; + +&lvds_encoder_input { + remote-endpoint = <&dpi_to_panel>; +}; + +&lvds_encoder_output { + remote-endpoint = <&panel_in>; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&panel_in { + remote-endpoint = <&lvds_encoder_output>; +}; From 5c0bf61401b4ab0150245566555e043193654ee1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:07:35 +0100 Subject: [PATCH 072/139] arm64: dts: imx91-tqma9131-mba91xxca: Add parallel display overlay Add support for CDTech S070SWV29HG-DC44 display on parallel interface X3 on MBa91xxCA. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 98711777e81d..4e7b60041a9a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -417,6 +417,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb + +imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-rgb-cdtech-dc44.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo From b426ee9833092e193d8ead13ceba467df14565be Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:07:36 +0100 Subject: [PATCH 073/139] arm64: dts: imx91-tqma9131-mba91xxca: Add LVDS display overlay Add support for Tianma TM070JVHG33 LVDS display on interface X11/X12 on MBa91xxCA. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 4e7b60041a9a..31bc80586c68 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -418,7 +418,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb +imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-rgb-cdtech-dc44.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb From d213404642af732fe73f35dfd1c7ed6801556362 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 6 Mar 2026 14:31:02 -0600 Subject: [PATCH 074/139] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world. Signed-off-by: Rob Herring (Arm) Reviewed-by: Peter Robinson Tested-by: Peter Robinson # Tested on a NXP Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 5436b48b30e8..b9abe143cb56 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -43,6 +43,30 @@ map0 { }; }; }; + + soc@0 { + npu@4a900000 { + compatible = "fsl,imx93-npu", "arm,ethos-u65"; + reg = <0x4a900000 0x1000>; + interrupts = ; + power-domains = <&mlmix>; + clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + clock-names = "core", "apb"; + sram = <&sram>; + assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <800000000>, <133000000>; + }; + }; + + sram: sram@20480000 { + compatible = "mmio-sram"; + reg = <0x0 0x20480000 0x0 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x20480000 0x18000>; + }; }; &aips1 { From 130d90114c5255a7a729158da8fd8298a02017f1 Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 9 Mar 2026 09:57:43 +0100 Subject: [PATCH 075/139] arm64: dts: imx8mp-kontron: Fix boot order for PMIC and RTC The PMIC provides a level-shifter for the I2C lines to the RTC. As the level shifter needs to be enabled before the RTC can be accessed, make sure that the PMIC driver is probed first. As the PMIC also provides the supply voltage for the RTC through the 3.3V regulator, simply express this in the DT to create the required dependency. Avoid sporadic boot hangs that occurred when the RTC was accessed before the level-shifter was enabled. Fixes: 946ab10e3f40f ("arm64: dts: Add support for Kontron OSM-S i.MX8MP SoM and BL carrier board") Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi index b97bfeb1c30f..bc1a261bb000 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi @@ -330,6 +330,12 @@ rv3028: rtc@52 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; interrupts-extended = <&gpio3 24 IRQ_TYPE_LEVEL_LOW>; + /* + * While specifying the vdd-supply is normally not strictly necessary, + * here it also makes sure that the PMIC driver enables the level- + * shifter for the RTC before the RTC is probed. + */ + vdd-supply = <®_vdd_3v3>; }; }; From 2cf0902ca88d489d50346464b8c71545561b61b9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 Mar 2026 18:11:00 +0100 Subject: [PATCH 076/139] arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index e7f9c9319319..f4ba3d16ab86 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -114,14 +114,10 @@ optee: optee { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; pmu { @@ -138,8 +134,7 @@ gic: interrupt-controller@6000000 { <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ #interrupt-cells = <3>; interrupt-controller; - interrupts = ; + interrupts = ; its: msi-controller@6020000 { compatible = "arm,gic-v3-its"; msi-controller; From accb1e186434f8fb40a722b61e74a5888113e58e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 4 Mar 2026 18:11:01 +0100 Subject: [PATCH 077/139] arm64: dts: freescale: imx: Drop CPU masks from GICv3 PPI interrupts Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 11 +++++------ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 11 +++++------ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 +++++------ arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 3 +-- arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/imx94.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/imx95.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/imx952.dtsi | 10 +++++----- 8 files changed, 36 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f2e1854f38a0..2a82e656b9fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -220,16 +220,15 @@ psci { pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; timer { compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ clock-frequency = <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 3199bc0966b0..79b169b07c4f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -215,8 +215,7 @@ clk_ext4: clock-ext4 { pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -258,10 +257,10 @@ map0 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9b2b3a9bf9e8..90d7bb8f5619 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -310,8 +310,7 @@ dsp_reserved: dsp@92400000 { pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -397,10 +396,10 @@ map0 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 9b5d98766512..1de3ad60c6aa 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -86,8 +86,7 @@ gic: interrupt-controller@2d400000 { pmu { compatible = "arm,cortex-a35-pmu"; interrupt-parent = <&gic>; - interrupts = ; + interrupts = ; interrupt-affinity = <&A35_0>, <&A35_1>; }; diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index 5a8813df6bc9..46a5d2df074d 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -69,7 +69,7 @@ clk_ext1: clock-ext1 { pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -79,10 +79,10 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; arm,no-tick-in-suspend; interrupt-parent = <&gic>; diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 38488147a3ef..04c562eddc3b 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -120,7 +120,7 @@ mqs2: mqs2 { pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -130,10 +130,10 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; interrupt-parent = <&gic>; arm,no-tick-in-suspend; diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 5f61866e9df9..acb10bc14dd4 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -398,7 +398,7 @@ mqs1: mqs-1 { pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; thermal_zones: thermal-zones { @@ -475,10 +475,10 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; arm,no-tick-in-suspend; interrupt-parent = <&gic>; diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index 0f86b5626cdd..b26e6e3dc773 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -285,7 +285,7 @@ its: msi-controller@48040000 { pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -295,10 +295,10 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; arm,no-tick-in-suspend; interrupt-parent = <&gic>; From d89573876d9fa8ddc7ca50e005a4896ed890ece2 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:21 +0100 Subject: [PATCH 078/139] arm64: dts: freescale: imx8mm-var-som: Move UART4 description to Symphony The VAR-SOM-MX8MM module does not provide an onboard debug console. UART4 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART. Move the UART4 node from the SOM device tree to the imx8mm-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mm-var-som-symphony.dts | 18 ++++++++++++++++++ .../boot/dts/freescale/imx8mm-var-som.dtsi | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index affbc67c2ef6..819707e6f3bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -11,6 +11,10 @@ / { model = "Variscite VAR-SOM-MX8MM Symphony evaluation board"; compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm"; + chosen { + stdout-path = &uart4; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -156,6 +160,13 @@ &uart3 { status = "okay"; }; +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usbotg1 { disable-over-current; extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; @@ -251,4 +262,11 @@ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 190bde4edcd7..b6560c03639e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -9,10 +9,6 @@ / { model = "Variscite VAR-SOM-MX8MM module"; - chosen { - stdout-path = &uart4; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x80000000>; @@ -274,13 +270,6 @@ &uart2 { status = "okay"; }; -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - &usbotg1 { dr_mode = "otg"; usb-role-switch; @@ -418,13 +407,6 @@ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 From af88e34bf2374b638393f84f3f50b0453361041e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:22 +0100 Subject: [PATCH 079/139] arm64: dts: freescale: imx8mm-var-som: Align fsl,pins tables Reformat the fsl,pins tables in the i.MX8MM VAR-SOM device tree to use consistent column alignment across all pinctrl groups. Align the entries to match the formatting already used in the pinctrl_fec1 group, which contains the longest pin definitions, for improved readability and consistency. No functional changes intended. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-var-som.dtsi | 170 +++++++++--------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index b6560c03639e..da3c7332ec34 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -368,171 +368,171 @@ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 >; }; pinctrl_reg_eth_phy: regethphygrp { fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 >; }; pinctrl_restouch: restouchgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; From b58a110d8efe944315a29c0bc1af0d77b86e7bd5 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:23 +0100 Subject: [PATCH 080/139] arm64: dts: freescale: imx8mm-var-som: Update FEC support with MaxLinear PHY Update the FEC Ethernet controller on the i.MX8MM VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY. Add the PHY VDDIO supply regulator, adjust reset timings and add a pinctrl sleep state for low-power operation. The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring. Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony). Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mm-var-som-symphony.dts | 20 +++++++++- .../boot/dts/freescale/imx8mm-var-som.dtsi | 39 +++++++++++++++++-- 2 files changed, 55 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 819707e6f3bf..9f4e004f0a37 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8mm-var-som.dtsi" / { @@ -71,7 +72,24 @@ led { }; ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; &i2c2 { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index da3c7332ec34..24924ee1e8c7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -24,6 +24,13 @@ reg_eth_phy: regulator-eth-phy { gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &A53_0 { @@ -99,12 +106,17 @@ touchscreen@0 { }; &fec1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-supply = <®_eth_phy>; - fsl,magic-packet; status = "okay"; mdio { @@ -116,7 +128,8 @@ ethphy: ethernet-phy@4 { reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - reset-deassert-us = <10000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; }; }; }; @@ -366,6 +379,26 @@ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 >; }; + pinctrl_fec1_sleep: fec1sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 + MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 + MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 + MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 + MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 + MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 From 3eb24db8fadfcf9c22a1534e4da2824c80e5f97b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:24 +0100 Subject: [PATCH 081/139] arm64: dts: freescale: imx8mm-var-som: Add support for WM8904 audio codec The VAR-SOM-MX8MM can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications. Add the WM8904 device to the appropriate I2C bus, enable the SAI peripheral, and introduce the sound node to expose the sound card to the system. Add I3C recovery gpio properties. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-var-som.dtsi | 100 +++++++++++++++++- 1 file changed, 97 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 24924ee1e8c7..7cedef8add32 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -14,6 +14,14 @@ memory@40000000 { reg = <0x0 0x40000000 0 0x80000000>; }; + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_eth_phy: regulator-eth-phy { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -31,6 +39,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; }; &A53_0 { @@ -257,18 +293,57 @@ ldo6_reg: LDO6 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - /* TODO: configure audio, as of now just put a placeholder */ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - status = "disabled"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI5_ROOT>; + clock-names = "mclk"; + AVDD-supply = <&ldo5_reg>; + CPVDD-supply = <&ldo5_reg>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <&ldo5_reg>; + MICVDD-supply = <&ldo5_reg>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; }; }; +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + #sound-dai-cells = <0>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + dma-names = "rx", "tx"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -413,6 +488,13 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 @@ -431,6 +513,18 @@ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 From 4c2d9f56f49667362c31b5426e083de3666b33b4 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:25 +0100 Subject: [PATCH 082/139] arm64: dts: freescale: imx8mm-var-som: Add MCP251xFD CAN controller Add support for the Microchip MCP251xFD CAN-FD controller connected to the SPI bus on the i.MX8MM VAR-SOM. The controller uses a 40 MHz external oscillator and requires an interrupt line and a dedicated RX interrupt GPIO. Add the fixed clock, the MCP251xFD device node with the required properties, and the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-var-som.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 7cedef8add32..749342b9a0a7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -14,6 +14,13 @@ memory@40000000 { reg = <0x0 0x40000000 0 0x80000000>; }; + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + reg_audio_supply: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "wm8904-supply"; @@ -139,6 +146,19 @@ touchscreen@0 { ti,keep-vref-on; wakeup-source; }; + + /* CAN controller */ + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + clocks = <&clk40m>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <20000000>; + microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + }; }; &fec1 { @@ -424,6 +444,13 @@ &wdog1 { }; &iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x16 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 From 8e7ce17e6df46e33857a1d1b416ccea2504988bc Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:26 +0100 Subject: [PATCH 083/139] arm64: dts: freescale: imx8mm-var-som: Rework WiFi/BT and add legacy dts The VAR-SOM-MX8MM currently integrates the NXP IW61x wireless module, providing WiFi over SDIO and Bluetooth over UART. Move the wireless module configuration out of the base imx8mm-var-som.dtsi and provide dedicated variant includes. The IW61x configuration is moved to imx8mm-var-som-wifi-bt-iw61x.dtsi and used by the Symphony evaluation board device tree. A separate imx8mm-var-som-wifi-brcm-legacy.dtsi include is added to keep the configuration for the legacy Broadcom SDIO WiFi module used on earlier SOM revisions. To preserve compatibility with older SOM revisions, add a separate imx8mm-var-som-symphony-legacy.dtb, which disables the IW61x setup and applies the Broadcom-specific configuration. The Broadcom-based SOM revision is no longer in production, but support is kept for existing users. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mm-var-som-symphony-legacy.dts | 19 ++++++++ .../dts/freescale/imx8mm-var-som-symphony.dts | 1 + .../imx8mm-var-som-wifi-brcm-legacy.dtsi | 12 +++++ .../imx8mm-var-som-wifi-bt-iw61x.dtsi | 45 +++++++++++++++++++ .../boot/dts/freescale/imx8mm-var-som.dtsi | 6 --- 6 files changed, 78 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 31bc80586c68..960fa4adaefb 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -161,6 +161,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts new file mode 100644 index 000000000000..faa707402de9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +#include "imx8mm-var-som-symphony.dts" +#include "imx8mm-var-som-wifi-brcm-legacy.dtsi" + +&bluetooth_iw61x { + status = "disabled"; +}; + +&iw61x_pwrseq { + status = "disabled"; +}; + +&usdhc1 { + /delete-property/ mmc-pwrseq; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 9f4e004f0a37..2b608470da8e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -7,6 +7,7 @@ #include #include "imx8mm-var-som.dtsi" +#include "imx8mm-var-som-wifi-bt-iw61x.dtsi" / { model = "Variscite VAR-SOM-MX8MM Symphony evaluation board"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi new file mode 100644 index 000000000000..f44a846ea6f9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/* WIFI */ +&usdhc1 { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi new file mode 100644 index 000000000000..15990d141d2a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/ { + iw61x_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_bt>; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + mmc-pwrseq = <&iw61x_pwrseq>; +}; + +&iomuxc { + pinctrl_bt: bluetoothgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 749342b9a0a7..4c863fe2284a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -390,7 +390,6 @@ &usbotg2 { status = "okay"; }; -/* WIFI */ &usdhc1 { #address-cells = <1>; #size-cells = <0>; @@ -402,11 +401,6 @@ &usdhc1 { non-removable; keep-power-in-suspend; status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; }; /* SD */ From 4e9088abeacb9fca16c3774bd3d57a696924a0f2 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:27 +0100 Subject: [PATCH 084/139] arm64: dts: imx8mm-var-som-symphony: Move USB configuration from SOM Move the USB controller configuration out of the i.MX8MM VAR-SOM dtsi and into the VAR-SOM Symphony carrier board dts. The SOM does not provide any USB connectors and carrier boards may choose whether and how to route USB, therefore USB should be described in the carrier-specific device tree instead of the SOM include. While moving the nodes, align the Symphony USB description with the carrier design by enabling both USB controllers, wiring USB1 to the PTN5150 Type-C controller for dual-role operation, and updating the PHY tuning and VBUS regulator pinctrl (including a sleep state). Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mm-var-som-symphony.dts | 48 ++++++++++++------- .../boot/dts/freescale/imx8mm-var-som.dtsi | 12 ----- 2 files changed, 32 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 2b608470da8e..a425ee0ed8a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -32,6 +32,7 @@ reg_usb_otg2_vbus: regulator-usb-otg2-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>; + pinctrl-1 = <&pinctrl_reg_usb_otg2_vbus_sleep>; regulator-name = "usb_otg2_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -133,13 +134,20 @@ enet-sel-hog { }; }; - extcon_usbotg1: typec@3d { + /* USB Type-C Controller */ + ptn5150: typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; interrupt-parent = <&gpio1>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; }; }; @@ -187,27 +195,29 @@ &uart4 { }; &usbotg1 { - disable-over-current; - extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; }; &usbotg2 { dr_mode = "host"; vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; disable-over-current; - /delete-property/ usb-role-switch; - /* - * FIXME: having USB2 enabled hangs the boot just after: - * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller - * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1 - * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00 - * [ 1.977203] hub 1-0:1.0: USB hub found - * [ 1.980987] hub 1-0:1.0: 1 port detected - */ - status = "disabled"; + status = "okay"; }; &pinctrl_fec1 { @@ -262,6 +272,12 @@ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16 >; }; + pinctrl_reg_usb_otg2_vbus_sleep: regusbotg2vbus-sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x120 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 4c863fe2284a..d05b1ab17fed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -378,18 +378,6 @@ &uart2 { status = "okay"; }; -&usbotg1 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - &usdhc1 { #address-cells = <1>; #size-cells = <0>; From 20aa2aee5050473d83bd96a6ebbde9f3735e8b84 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:28 +0100 Subject: [PATCH 085/139] arm64: dts: imx8mm-var-som-symphony: Enable uSD on USDHC2 Enable the microSD slot on the VAR-SOM Symphony carrier board. Configure USDHC2 with card-detect GPIO, pinctrl states for the supported bus speeds and the required VMMC supply. Update the VMMC regulator to match the latest carrier revision by moving the enable GPIO to GPIO4_IO22 and adding the required off-on delay. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mm-var-som-symphony.dts | 59 ++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index a425ee0ed8a9..6da29845985f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -24,7 +24,8 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -220,6 +221,18 @@ &usbotg2 { status = "okay"; }; +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + &pinctrl_fec1 { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -280,7 +293,7 @@ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x120 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 >; }; @@ -304,4 +317,46 @@ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 >; }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 + >; + }; }; From 9681db803b0544c66eacc062ac29cc80b27c0fd0 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:29 +0100 Subject: [PATCH 086/139] arm64: dts: imx8mm-var-som-symphony: Add TPM2 support Add support for the TPM2 device on the VAR-SOM Symphony carrier board. The ST33K TPM2 is connected over I2C, and A PCA6408 GPIO expander is used to control the reset signal required to release the TPM from reset. Add the PCA6408 GPIO expander and the ST33K TPM2 device node. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 6da29845985f..6112e4392c59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -153,6 +153,20 @@ typec1_dr_sw: endpoint { }; &i2c3 { + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5406"; From 47fc77cb042d48712d9dee6068066abff4d3e737 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:30 +0100 Subject: [PATCH 087/139] arm64: dts: imx8mm-var-som-symphony: Enable I2C4 Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mm-var-som-symphony.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 6112e4392c59..fbad5d2d4a97 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -188,6 +188,16 @@ rtc@68 { }; }; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -281,6 +291,20 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 From b06c76fcd88c4c3f7ec2dc88c368d1fd2770ad91 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 19 Mar 2026 19:40:31 +0100 Subject: [PATCH 088/139] arm64: dts: imx8mm-var-som-symphony: Enable PCIe Enable PCIe support on the VAR-SOM Symphony carrier board by adding the external reference clock, configuring the PHY and providing the required clock and reset properties. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mm-var-som-symphony.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index fbad5d2d4a97..857325ef4461 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "imx8mm-var-som.dtsi" #include "imx8mm-var-som-wifi-bt-iw61x.dtsi" @@ -17,6 +18,12 @@ chosen { stdout-path = &uart4; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -198,6 +205,29 @@ &i2c4 { status = "okay"; }; +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + fsl,clkreq-unsupported; + status = "okay"; +}; + +&pcie0 { + reset-gpio = <&pca6408 1 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; From 8da7bfdcda753ef4d7890f55966ffdbda785e72e Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Fri, 13 Mar 2026 14:30:57 +0200 Subject: [PATCH 089/139] arm64: dts: freescale: add support for SolidRun i.MX8MP HummingBoard IIoT Introduce support for the SolidRun i.MX8MP HummingBoard IIoT platform. This board is a new design based on the i.MX8MP System on Module and does not share much hardware with previous HummingBoard variants. It comes with some common features: - 3x USB-3.0 Type A connector - 2x 1Gbps RJ45 Ethernet - USB Type-C Console Port - microSD connector - RTC with backup battery - RGB Status LED - 1x M.2 M-Key connector with PCI-E Gen. 3 x1 - 1x M.2 B-Key connector with USB-2.0/3.0 + SIM card holder - 1x LVDS Display Connector - 1x DSI Display Connector - GPIO header - 2x RS232/RS485 ports (configurable) - 2x CAN In addition there is a board-to-board expansion connector to support custom daughter boards with access to SPI, a range of GPIOs and - notably - CAN and UART. Both 2x CAN and 2x UART can be muxed either to this b2b connector, or a terminal block connector on the base board. The routing choice for UART and CAN is expressed through gpio mux-controllers in DT and can be changed by applying dtb overlays. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx8mp-hummingboard-iiot.dts | 716 ++++++++++++++++++ 2 files changed, 718 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 960fa4adaefb..82175304bdb1 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb +DTC_FLAGS_imx8mp-hummingboard-iiot := -@ +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb DTC_FLAGS_imx8mp-hummingboard-mate := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb DTC_FLAGS_imx8mp-hummingboard-pro := -@ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts new file mode 100644 index 000000000000..7c5b77c928d3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts @@ -0,0 +1,716 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Yazan Shhady + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include +#include + +#include "imx8mp-sr-som.dtsi" + +/ { + compatible = "solidrun,imx8mp-hummingboard-iiot", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + model = "SolidRun i.MX8MP HummingBoard IIoT"; + + /* power for M.2 B-Key connector (J6) */ + regulator-m2-b { + compatible = "regulator-fixed"; + regulator-name = "m2-b"; + gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + enable-active-high; + }; + + /* power for M.2 M-Key connector (J4) */ + regulator-m2-m { + compatible = "regulator-fixed"; + regulator-name = "m2-m"; + gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + enable-active-high; + }; + + /* power for USB-A J27 behind USB Hub Port 3 */ + regulator-vbus-2 { + compatible = "regulator-fixed"; + regulator-name = "vbus2"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power for USB-A J27 behind USB Hub Port 4 */ + regulator-vbus-3 { + compatible = "regulator-fixed"; + regulator-name = "vbus3"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + aliases { + /* J10 */ + ethernet0 = &eqos; + /* J11 */ + ethernet1 = &fec; + gpio5 = &tca6408_u48; + gpio6 = &tca6408_u37; + gpio7 = &tca6416_u20; + gpio8 = &tca6416_u21; + i2c6 = &i2c_exp; + i2c7 = &i2c_csi; + i2c8 = &i2c_dsi; + i2c9 = &i2c_lvds; + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + gpio-keys { + compatible = "gpio-keys"; + + wakeup-event { + interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>; + label = "m2-m-wakeup"; + wakeup-source; + linux,code = ; + }; + }; + + can_mux: mux-controller-0 { + compatible = "gpio-mux"; + /* + * Mux routes CAN bus signals between SoM connector pins, + * expansion connector (J22) and on-board transceivers using + * two GPIO: + * - IO3: 0 = on-board transceivers, 1 = expansion connector + * - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56 + */ + mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>, + <&tca6416_u20 4 GPIO_ACTIVE_HIGH>; + /* default J7-12/16 & J9-54/56 to on-board transceivers */ + idle-state = <2>; + #mux-control-cells = <0>; + }; + + spi_mux: mux-controller-1 { + compatible = "gpio-mux"; + /* default on-board */ + idle-state = <0>; + /* + * Mux switches spi bus between on-board tpm + * and expansion connector (J22). + */ + mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + uart3_uart4_b2b_mux: mux-controller-2 { + compatible = "gpio-mux"; + /* default on-board */ + idle-state = <0>; + /* + * Mux switches both uart3 and uart4 tx/rx between expansion + * connector (J22) and on-board rs232/rs485 transceivers + * using one GPIO: 0 = on-board, 1 = connector. + */ + mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + uart3_rs_232_485_mux: mux-controller-3 { + compatible = "gpio-mux"; + /* default rs232 */ + idle-state = <0>; + /* + * Mux switches uart3 tx/rx between rs232 and rs485 + * transceivers. using one GPIO: 0 = rs232, 1 = rs485. + */ + mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + uart4_rs_232_485_mux: mux-controller-4 { + compatible = "gpio-mux"; + /* default rs232 */ + idle-state = <0>; + /* + * Mux switches uart4 tx/rx between rs232 and rs485 + * transceivers. using one GPIO: 0 = rs232, 1 = rs485. + */ + mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_dsi_panel: regulator-dsi-panel { + compatible = "regulator-fixed"; + regulator-name = "dsi-panel"; + gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <11200000>; + regulator-min-microvolt = <11200000>; + enable-active-high; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + pinctrl-0 = <&vmmc_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <250>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power for USB-A J5003 */ + vbus1: regulator-vbus-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus1"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rfkill-m2-b-gnss { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>; + label = "m2-b gnss"; + radio-type = "gps"; + }; + + rfkill-m2-b-wwan { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>; + label = "m2-b radio"; + radio-type = "wwan"; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-0 = <&ecspi2_pins>; + pinctrl-names = "default"; + status = "okay"; + + ecspi2_muxed: spi@0 { + compatible = "spi-mux"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mux-controls = <&spi_mux>; + /* mux bandwidth is 2GHz, soc max. spi clock is 166MHz */ + spi-max-frequency = <166000000>; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + spi-max-frequency = <43000000>; + }; + }; +}; + +&flexcan1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&flexcan2 { + pinctrl-0 = <&can2_pins>; + pinctrl-names = "default"; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&i2c2 { + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + /* + * This reset is open drain, + * but reset core does not support GPIO_OPEN_DRAIN flag. + */ + reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>; + + /* channel 0 routed to expansion connector (J22) */ + i2c_exp: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* channel 1 routed to mipi-csi connector (J23) */ + i2c_csi: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* channel 2 routed to mipi-dsi connector (J25) */ + i2c_dsi: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + tca6408_u48: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "CAM_RST#", "DSI_RESET", + "DSI_STBYB", "DSI_PWM_BL", + "DSI_L/R", "DSI_U/D", + "DSI_CTP_/RST", "CAM_TRIG"; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + * + * reset-gpios = <&tca6416_u21 4 + * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + */ + }; + + }; + + /* channel 2 routed to lvds connector (J24) */ + i2c_lvds: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + tca6408_u37: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "SELB", "LVDS_RESET", + "LVDS_STBYB", "LVDS_PWM_BL", + "LVDS_L/R", "LVDS_U/D", + "LVDS_CTP_/RST", ""; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + * + * reset-gpios = <&tca6416_u21 4 + * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + */ + }; + + }; + }; +}; + +&i2c3 { + /* highest i2c clock supported by all peripherals is 400kHz */ + clock-frequency = <400000>; + + tca6416_u20: gpio@20 { + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485", + "TCA_UARTB_232/485", "TCA_INT/EXT_CAN", + "TCA_NXP/REN", "TCA_M.2B_3V3_EN", + "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#", + "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#", + "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#", + "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN", + "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN"; + /* + * This is a TI TCAL6416 using same programming model as + * NXP PCAL6416, not to be confused with TI TCA6416. + */ + compatible = "nxp,pcal6416"; + + m2-b-reset-hog { + gpios = <8 GPIO_ACTIVE_LOW>; + gpio-hog; + line-name = "m2-b-reset"; + output-low; + }; + }; + + tca6416_u21: gpio@21 { + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#", + "TCA_I2C_RST", "TCA_RS232_SHTD#", + "TCA_LCD_I2C_RST", "TCA_DIG_OUT1", + "TCA_bDIG_IN1", "TCA_SENS_INT", + "TCA_ALERT#", "TCA_TPM_PIRQ#", + "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN", + "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#", + "", "TCA_POE_AT"; + interrupts-extended = <&gpio1 15 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&tca6416_u21_int_pins>; + pinctrl-names = "default"; + /* + * This is a TI TCAL6416 using same programming model as + * NXP PCAL6416, not to be confused with TI TCA6416. + */ + compatible = "nxp,pcal6416"; + + lcd-i2c-reset-hog { + gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + line-name = "lcd-i2c-reset"; + output-low; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + */ + gpio-hog; + }; + + m2-m-clkreq-hog { + gpios = <12 GPIO_ACTIVE_LOW>; + gpio-hog; + input; + line-name = "m2-m-clkreq"; + }; + + rs232_shutdown: rs232-shutdown-hog { + gpios = <3 GPIO_ACTIVE_LOW>; + gpio-hog; + line-name = "rs232-shutdown"; + output-low; + }; + }; + + led-controller@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + /* use internal clock, could use external generated by rtc */ + clock-mode = /bits/ 8 <1>; + + multi-led@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + color = ; + label = "D7"; + + led@0 { + reg = <0x0>; + color = ; + led-cur = /bits/ 8 <0x32>; + max-cur = /bits/ 8 <0x64>; + }; + + led@1 { + reg = <0x1>; + color = ; + led-cur = /bits/ 8 <0x19>; + max-cur = /bits/ 8 <0x32>; + }; + + led@2 { + reg = <0x2>; + color = ; + led-cur = /bits/ 8 <0x19>; + max-cur = /bits/ 8 <0x32>; + }; + }; + + led@3 { + reg = <0x3>; + chan-name = "D8"; + color = ; + label = "D8"; + led-cur = /bits/ 8 <0x19>; + max-cur = /bits/ 8 <0x64>; + }; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */ + interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; + }; + + accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */ + interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT1"; + }; + + carrier_eeprom: eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + pagesize = <8>; + }; + + carrier_rtc: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + /* + * AM1805 RTC used on this board has only nTIRQ pins wired, + * which is for countdown timer irqs only. + * Driver does not support this, disable for now. + * + * interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_EDGE_FALLING>; + */ + }; +}; + +&iomuxc { + can1_pins: pinctrl-can1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + can2_pins: pinctrl-can2-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + ecspi2_pins: pinctrl-ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + tca6416_u21_int_pins: pinctrl-tca6416-u21-int-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x0 + >; + }; + + /* UARTA */ + uart3_pins: pinctrl-uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 + >; + }; + + /* UARTB */ + uart4_pins: pinctrl-uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0 + >; + }; +}; + +&pcie { + reset-gpio = <&tca6416_u20 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* M.2 M-Key (J4) */ +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&phy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = ; + default-state = "keep"; + function = LED_FUNCTION_LAN; + }; + }; +}; + +&phy1 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = ; + default-state = "keep"; + function = LED_FUNCTION_LAN; + }; + }; +}; + +&uart3 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + rts-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart4 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + pinctrl-0 = <&uart4_pins>; + pinctrl-names = "default"; + rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <&vbus1>; + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; +}; + +&usb_dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + + hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; + + hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; +}; + +&usdhc2 { + bus-width = <4>; + cap-power-off-card; + full-pwr-cycle; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&vmmc>; + status = "okay"; +}; From 514a34d75b9d16760971472af4f5f6550bf575ed Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Fri, 13 Mar 2026 14:30:58 +0200 Subject: [PATCH 090/139] arm64: dts: imx8mp-hummingboard-iiot: add dt overlays for muxable ports The SolidRun i.MX8MP HummingBoard IIoT has a variety of connectors, and configurable ports: - 2x RS232 - 2x RS485 - DSI Panel Connector - LVDS Panel Connector RS232 and RS485 each share a single UART from the SoC via a mux, which are configured from the base dts for RS232 by default. Provide addons for: 1. Reconfigure UART A from RS232 to RS485. 2. Reconfigure UART B from RS232 to RS485. 3. Configure DSI Connector for Winstar WJ70N3TYJHMNG0 Panel. 4. Configure LVDS Connector for Winstar WF70A8SYJHLNGA Panel. A variation of the base dtb is generated for each addon to ensure that make dtbs_check covers the resulting dtb, and applying overlay is tested during build. It is however expected that bootloader should apply any combination of addons based on runtime configuration. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 12 +++ ...ngboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso | 67 +++++++++++++ ...gboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso | 97 +++++++++++++++++++ .../imx8mp-hummingboard-iiot-rs485-a.dtso | 18 ++++ .../imx8mp-hummingboard-iiot-rs485-b.dtso | 18 ++++ 5 files changed, 212 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 82175304bdb1..164fd3c3bc10 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -241,6 +241,18 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb DTC_FLAGS_imx8mp-hummingboard-iiot := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo +imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtbo +imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-a.dtbo +imx8mp-hummingboard-iiot-rs485-a-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-rs485-a.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-a.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-b.dtbo +imx8mp-hummingboard-iiot-rs485-b-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-rs485-b.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-b.dtb DTC_FLAGS_imx8mp-hummingboard-mate := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb DTC_FLAGS_imx8mp-hummingboard-pro := -@ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso new file mode 100644 index 000000000000..6c41f2633f14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT MIPI-DSI connector + * with Winstar WJ70N3TYJHMNG0 panel. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + dsi_backlight: dsi-backlight { + compatible = "gpio-backlight"; + gpios = <&tca6408_u48 3 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c_dsi { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili2130"; + reg = <0x41>; + interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6408_u48 6 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + panel@0 { + /* This is a Winstar panel, but the ronbo panel uses same controls. */ + compatible = "ronbo,rb070d30"; + reg = <0>; + /* reset is active-low but driver inverts it internally */ + reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>; + backlight = <&dsi_backlight>; + power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>; + shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>; + updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>; + vcc-lcd-supply = <®_dsi_panel>; + + port { + panel_from_dsim: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; +}; + +&mipi_dsi_out { + data-lanes = <1 2 3 4>; + remote-endpoint = <&panel_from_dsim>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso new file mode 100644 index 000000000000..ca4e7b8fee8e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT LVDS connector + * with Winstar WF70A8SYJHLNGA panel. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + lvds_backlight: lvds-backlight { + compatible = "gpio-backlight"; + gpios = <&tca6408_u37 3 GPIO_ACTIVE_LOW>; + }; + + panel-lvds { + compatible = "winstar,wf70a8syjhlnga", "panel-lvds"; + backlight = <&lvds_backlight>; + data-mapping = "vesa-24"; + enable-gpios = <&tca6408_u37 2 GPIO_ACTIVE_HIGH>; + height-mm = <86>; + power-supply = <®_dsi_panel>; + reset-gpios = <&tca6408_u37 1 GPIO_ACTIVE_HIGH>; + width-mm = <154>; + + panel-timing { + /* + * Note: NXP BSP hard-codes 74MHz clock in ldb driver: + * drivers/gpu/drm/imx/imx8mp-ldb.c + * SolidRun BSP carries patch. + */ + clock-frequency = <49500000>; + de-active = <1>; + hactive = <1024>; + hback-porch = <144>; + hfront-porch = <40>; + hsync-active = <0>; + hsync-len = <104>; + vactive = <600>; + vback-porch = <11>; + vfront-porch = <3>; + vsync-active = <1>; + vsync-len = <10>; + }; + + port { + panel_from_lvds: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&i2c_lvds { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili2130"; + reg = <0x41>; + interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6408_u37 6 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&ldb_lvds_ch0 { + remote-endpoint = <&panel_from_lvds>; +}; + +&lvds_bridge { + status = "okay"; +}; + +&tca6408_u37 { + lvds-lr-hog { + gpios = <4 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "lvds-l/r"; + output-high; + }; + + lvds-ud-hog { + gpios = <5 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "lvds-u/d"; + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso new file mode 100644 index 000000000000..ae64d6efad9d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004. + */ + +/dts-v1/; +/plugin/; + +&uart3 { + linux,rs485-enabled-at-boot-time; +}; + +&uart3_rs_232_485_mux { + /* select rs485 */ + idle-state = <1>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso new file mode 100644 index 000000000000..2718fa5b2c66 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004. + */ + +/dts-v1/; +/plugin/; + +&uart4 { + linux,rs485-enabled-at-boot-time; +}; + +&uart4_rs_232_485_mux { + /* select rs485 */ + idle-state = <1>; +}; From 79f63593c7b07109f79c1d3fc54bb4fc3eeaf29e Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Fri, 13 Mar 2026 14:30:59 +0200 Subject: [PATCH 091/139] arm64: dts: freescale: add support for solidrun solidsense-n8 board Add support for the SolidRun SolidSense N8 Compact. The board is designed around the i.MX8MN SoC and comes as a complete product including enclosure and labels. Features: - USB-2.0 Type A connector - 1Gbps RJ45 Ethernet with PoE - microSD connector - eMMC - Cellular Modem + SIM holder - WiFi + Bluetooth - RS485 - CAN - 802.15.1 radio - supercapacitor backup power supply This is a headless design without display. The board includes an internal expansion connector for daughterboards which may be described by dt addon. The supercap is not currently described due to lack of suitable bindings. Vendor BSP uses gpio-keys driver to trigger shutdown on power loss. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8mn-solidsense-n8-compact.dts | 851 ++++++++++++++++++ 2 files changed, 853 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 164fd3c3bc10..0ab8ce394945 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -192,6 +192,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-rve-gateway.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb +DTC_FLAGS_imx8mn-solidsense-n8-compact += -@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts b/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts new file mode 100644 index 000000000000..c8c6760524db --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts @@ -0,0 +1,851 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for SolidSense N8 Compact + * + * Copyright 2024 Josua Mayer + */ + +/dts-v1/; + +#include + +#include "imx8mn.dtsi" + +/ { + compatible = "solidrun,solidsense-n8-compact", "fsl,imx8mn"; + model = "SolidRun SolidSense N8 Compact"; + + /* LED labels based on enclosure, schematic names differ. */ + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + /* D20 */ + led1 { + default-state = "off"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + label = "led1"; + }; + + /* D18 */ + led2 { + default-state = "off"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + label = "led2"; + }; + + /* D19 */ + led3 { + default-state = "off"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + label = "led3"; + }; + }; + + aliases { + gpio5 = &expander; + rtc0 = &rtc; + rtc1 = &snvs_rtc; + usb0 = &usbotg1; + watchdog0 = &wdog1; + watchdog1 = &rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + reg_modem_vbat: regulator-modem-vbat { + compatible = "regulator-fixed"; + regulator-name = "modem-vbat"; + pinctrl-0 = <®ulator_modem_vbat_pins>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <3800000>; + regulator-min-microvolt = <3800000>; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power to lte modems behind hub ports 2/3 */ + reg_modem_vbus: regulator-modem-vbus { + compatible = "regulator-fixed"; + regulator-name = "modem-vbus"; + pinctrl-0 = <®ulator_modem_vbus_pins>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power to usb hub, and type-a behind hub port 1 */ + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + pinctrl-0 = <®ulator_usb1_vbus_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "usdhc2-vmmc"; + off-on-delay-us = <250>; + pinctrl-0 = <®ulator_usdhc2_vmmc_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd-1v8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + rfkill { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "rfkill-wwan"; + pinctrl-0 = <&modem_pins>; + pinctrl-names = "default"; + radio-type = "wwan"; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + +&ecspi2 { + /* native chip-select causes reading 0xffffffff */ + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-0 = <&ecspi2_pins>; + pinctrl-names = "default"; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk IMX8MN_CLK_CLKOUT1>; + /* generate 8MHz clock from soc-internal 24mhz reference */ + assigned-clock-parents = <&clk IMX8MN_CLK_24M>, <0>; + assigned-clock-rates = <0>, <8000000>; + assigned-clocks = <&clk IMX8MN_CLK_CLKOUT1_SEL>, + <&clk IMX8MN_CLK_CLKOUT1_DIV>; + pinctrl-0 = <&can_pins>; + pinctrl-names = "default"; + spi-max-frequency = <20000000>; + }; +}; + +&fec1 { + phy-handle = <&phy4>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&fec1_pins>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Depending on board revision two different phys are used: + * - v1.1: atheros phy at address 4 + * - v1.2+: analog devices phy at address 0 + * Configure first version by default. + * On v1.2 and later, U-Boot will enable the correct phy + * based on runtime detection and patch dtb accordingly. + */ + + /* ADIN1300 */ + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + adi,led-polarity = ; + adi,link-st-polarity = ; + status = "disabled"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + active-low; + color = ; + default-state = "keep"; + function = LED_FUNCTION_LAN; + }; + }; + }; + + /* AR8035 */ + phy4: ethernet-phy@4 { + reg = <4>; + reset-assert-us = <10000>; + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; +}; + +&gpio5 { + usb-hub-reset-hog { + line-name = "usb-hub-reset"; + gpios = <3 GPIO_ACTIVE_LOW>; + gpio-hog; + /* deasserted */ + output-low; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&osc_32k>; + #clock-cells = <0>; + clock-output-names = "clk-32k-out"; + pinctrl-0 = <&pmic_pins>; + pinctrl-names = "default"; + rohm,reset-snvs-powered; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + // supplies soc vdd, soc mipi vdd @ 0.9V + regulator-name = "buck1"; + rohm,dvs-run-voltage = <850000>; + rohm,dvs-suspend-voltage = <750000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + rohm,dvs-idle-voltage = <900000>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-suspend-voltage = <0>; + }; + + BUCK3 { + // BUCK5 in datasheet + // output floating + regulator-name = "buck3"; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + }; + + BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + // BUCK6 in datasheet + // supplies ldo3, ldo5, muxsw + regulator-name = "buck4"; + }; + + BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + // BUCK7 in datasheet + // supplies ldo4, ldo6, muxsw + // enables dram vpp @ 2.5V + regulator-name = "buck5"; + }; + + BUCK6 { + // BUCK8 in datasheet + // supplies dram @ 1.2V + regulator-name = "buck6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + }; + + LDO1 { + // supplies soc snvs @ 1.8V + regulator-name = "ldo1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + }; + + LDO2 { + // supplies soc snvs @ 0.8V + regulator-name = "ldo2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <800000>; + }; + + LDO3 { + // supplies soc vdd @ 1.8V + regulator-name = "ldo3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + LDO4 { + // output floating + regulator-name = "ldo4"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + + LDO5 { + // output floating + regulator-name = "ldo5"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + }; + + LDO6 { + // supplies soc vdd mipi @ 1.2V + regulator-name = "ldo6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + }; + }; +}; + +&i2c2 { + /* + * routed to various connectors: + * - basler camera (CON2) + * - touchscreen (J3) + * - expansion connector (J14) + */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + expander: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "SYSGD", "PFO#", "CAPGD", "CAPFLT#", + "CHGEN#", "BSTEN#", "", ""; + pinctrl-0 = <&gpio_expander_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + }; + + accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + }; + + /* battery-charger@68 */ + + rtc: rtc@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&rtc_pins>; + pinctrl-names = "default"; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + }; +}; + +&i2c4 { + /* routed to expansion connector (J14) */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&tamper_pins>, <&usb_hub_pins>; + pinctrl-names = "default"; + + can_pins: pinctrl-can-grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x140 + >; + }; + + ecspi2_pins: pinctrl-ecspi2-grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x96 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x1d6 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1d6 + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1d6 + >; + }; + + fec1_pins: pinctrl-fec1-grp { + /* + * Some pins are sampled at phy reset to apply configuration: + * - AR803x PHY (revision 1.1) + * - RXD[1:0]: phy address bits [1:0] + * - RXD[3:2],RX_CTL: mac interface select bits 3,1,0 + * - ADIN1300 PHY (revision 1.2 or later) + * - RXD[3:0]: phy address bits [3:0] + * - RX_CTL,RXC: mac interface select bits 1,0 + * SoC enables pull-down at reset, PHYs have internal + * pull-down, so pinmux may unset pull-enable. + */ + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x2 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1e + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1e + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1e + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1e + /* RD[3:0] sampled at phy reset for address bits [3:0] */ + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x10 + /* phy reset */ + MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0 + /* phy interrupt */ + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 + >; + }; + + gpio_expander_pins: pinctrl-gpio-expander-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x140 + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + >; + }; + + i2c1_pins: pinctrl-i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c2 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c2 + >; + }; + + i2c2_pins: pinctrl-i2c2-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + i2c4_pins: pinctrl-i2c4-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 + >; + }; + + ieee802151_radio_pins: pinctrl-ieee802151-radio-grp { + fsl,pins = < + /* RESETN */ + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x0 + /* VDD_EN */ + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0 + /* SWDCLK */ + MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0 + /* SDIO */ + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0 + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x100 + MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x100 + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x100 + >; + }; + + modem_pins: pinctrl-modem-grp { + fsl,pins = < + /* RESET_N: modem-internal pull-down */ + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0 + /* PWRKEY: pull-down ensures always-on */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x100 + >; + }; + + pmic_pins: pinctrl-pmic-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 + >; + }; + + regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0 + >; + }; + + regulator_modem_vbus_pins: pinctrl-regulator-modem-vbus-grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0 + >; + }; + + regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x0 + >; + }; + + regulator_usdhc2_vmmc_pins: pinctrl-regulator-usdhc2-vmmc-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0 + >; + }; + + rtc_pins: pinctrl-rtc-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x100 + >; + }; + + tamper_pins: pinctrl-tamper-grp { + /* + * Routed to physical tamper input (J12), + * accelerometer and light-sensor interrupts. + */ + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x140 + >; + }; + + uart1_pins: pinctrl-uart1-grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + /* BT_REG_ON */ + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 + /* BT_WAKE_DEV */ + MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0 + /* BT_WAKE_HOST */ + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100 + >; + }; + + uart2_pins: pinctrl-uart2-grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + uart3_pins: pinctrl-uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x140 + >; + }; + + uart4_pins: pinctrl-uart4-grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + usb_hub_pins: pinctrl-usb-hub-grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x0 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + /* wifi refclk */ + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0 + /* WL_WAKE_HOST */ + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100 + /* WL_REG_ON */ + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + /* usdhc2 signalling voltage pmic control */ + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + /* usdhc2 signalling voltage pmic control */ + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + /* usdhc2 signalling voltage pmic control */ + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + wdog1_pins: pinctrl-wdog1-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 + >; + }; +}; + +/* Bluetooth */ +&uart1 { + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +/* console */ +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* RS485 */ +&uart3 { + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + fsl,dte-mode; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* 802.15.1 radio */ +&uart4 { + pinctrl-0 = <&uart4_pins &ieee802151_radio_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +/* WiFi */ +&usdhc1 { + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + pinctrl-0 = <&usdhc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + broken-cd; + bus-width = <4>; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&usdhc3_pins>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + /* + * Use lowest drive strength for all high-speed modes to minimise + * electro-magnetic emissions. + * In this particular design HS-400 still works okay, no extra + * pinctrl for 100mhz and 200mhz are required. + */ + pinctrl-names = "default"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&wdog1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From 21f0002238a534e1060db6218617fd6eab13b253 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Fri, 13 Mar 2026 14:31:00 +0200 Subject: [PATCH 092/139] arm64: dts: freescale: add support for solidrun i.mx8mm som and evb Add support for the SolidRun i.MX8M Mini SoM on HummingBoard Ripple. The SoM features: - 1Gbps Ethernet with PHY - eMMC - 1/2GB DDR - NPU (assembly option) - WiFi + Bluetooth The HummingBoard Ripple features: - 2x USB-2.0 Type-A connector - 1Gbps RJ45 Ethernet with PoE - microSD connector - microHDMI connector - mpcie connector with USB-2.0 interface + SIM card holder - microUSB connector for console (using fdtdi chip) - RTC with backup battery Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx8mm-hummingboard-ripple.dts | 335 +++++++++++++++ .../boot/dts/freescale/imx8mm-sr-som.dtsi | 393 ++++++++++++++++++ 3 files changed, 730 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0ab8ce394945..47ad6e7ac810 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -126,6 +126,8 @@ imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-hummingboard-ripple.dtb +DTC_FLAGS_imx8mm-hummingboard-ripple += -@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts new file mode 100644 index 000000000000..18b58634d3c2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include + +#include "imx8mm-sr-som.dtsi" + +/ { + compatible = "solidrun,imx8mm-hummingboard-ripple", + "solidrun,imx8mm-sr-som", "fsl,imx8mm"; + model = "SolidRun i.MX8MM HummingBoard Ripple"; + + aliases { + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "c"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led-0 { + color = ; + default-state = "on"; + gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + label = "D30"; + }; + + led-1 { + color = ; + default-state = "on"; + gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + label = "D31"; + }; + + led-2 { + color = ; + default-state = "on"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + label = "D32"; + }; + + led-3 { + color = ; + default-state = "on"; + gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + label = "D33"; + }; + + led-4 { + color = ; + default-state = "on"; + gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + label = "D34"; + }; + }; + + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + pinctrl-0 = <&vmmc_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <250>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; + }; + + vbus1: regulator-vbus-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus1"; + pinctrl-0 = <&vbus1_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus2: regulator-vbus-2 { + compatible = "regulator-fixed"; + regulator-name = "vbus2"; + pinctrl-0 = <&vbus2_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rfkill-mpcie-wifi { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + label = "mpcie WiFi"; + pinctrl-0 = <&pcie_rfkill_pins>; + pinctrl-names = "default"; + radio-type = "wlan"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + a2vdd-supply = <&v_1_8>; + avdd-supply = <&v_1_8>; + dvdd-supply = <&v_1_8>; + pd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_pins>; + pinctrl-names = "default"; + pvdd-supply = <&v_1_8>; + v3p3-supply = <&v_3_3>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_from_dsim: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; + + carrier_rtc: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + }; +}; + +&iomuxc { + hdmi_pins: pinctrl-hdmi-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0 + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x0 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x0 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0 + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x0 + MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x0 + MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x0 + >; + }; + + pcie_rfkill_pins: pinctrl-pcie-rfkill-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0 + >; + }; + + usb_hub_pins: pinctrl-usb-hub-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x0 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + >; + }; + + vbus1_pins: pinctrl-vbus-1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x20 + >; + }; + + vbus2_pins: pinctrl-vbus-2-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x20 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&adv7535_from_dsim>; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <&vbus2>; + status = "okay"; +}; + +&usbotg2 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + pinctrl-0 = <&usb_hub_pins>; + pinctrl-names = "default"; + vbus-supply = <&vbus1>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; + + /* this device is not visible because host supports 2.0 only */ + hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; +}; + +&usdhc2 { + bus-width = <4>; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi new file mode 100644 index 000000000000..8d0249f1e92d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +#include + +#include "imx8mm.dtsi" + +/ { + compatible = "solidrun,imx8mm-sr-som", "fsl,imx8mm"; + model = "SolidRun i.MX8MM SoM"; + + chosen { + bootargs = "earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + v_1_8: regulator-1-8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + v_3_3: regulator-3-3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&fec1 { + phy = <&phy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&fec1_pins>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x4>; + phy-reset-duration = <10>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + vddio-supply = <&vddio>; + qca,smarteee-tw-us-1g = <24>; + + vddio: vddio-regulator { + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&osc_32k>; + #clock-cells = <0>; + clock-output-names = "clk-32k-out"; + pinctrl-0 = <&pmic_pins>; + pinctrl-names = "default"; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + rohm,dvs-idle-voltage = <900000>; + rohm,dvs-run-voltage = <1000000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <800000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + }; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c01", "atmel,24c01"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&iomuxc { + fec1_pins: pinctrl-fec1-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + i2c1_pins: pinctrl-i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pcie_pins: pinctrl-pcie-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0 + >; + }; + + pmic_pins: pinctrl-pmic-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 + >; + }; + + uart1_pins: pinctrl-uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + /* BT_REG_ON */ + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 + /* BT_WAKE_DEV */ + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0 + /* BT_WAKE_HOST */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100 + >; + }; + + uart2_pins: pinctrl-uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + /* wifi refclk */ + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0 + /* WL_REG_ON */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0 + /* WL_WAKE_HOST */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100 + >; + }; + + usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + wdog1_pins: pinctrl-wdog1-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 + >; + }; +}; + +/* assembly-option for AI accelerator on SoM, otherwise routed to carrier */ +&pcie0 { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pcie_phy { + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&uart1 { + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usdhc1 { + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + pinctrl-0 = <&usdhc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&usdhc3_pins>; + pinctrl-1 = <&usdhc3_100mhz_pins>; + pinctrl-2 = <&usdhc3_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&wdog1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From 248d61177b10d6cbc952c07f5a34ff434350462f Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:10:23 +0100 Subject: [PATCH 093/139] arm64: dts: imx8mm: Explicitly set DSI_PHY_REF clock as a child of CLK_24M Since commit a0deedcc0cf0 ("arm64: dts: imx8mm: Slow default video_pll1 clock rate") and commit 5fe6ec93f10b0 ("clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate") VIDEO_PLL1 is dynamically programmed by CLK_LCDIF_PIXEL. On imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso this results in a VIDEO_PLL1 frequency of 68.2 MHz and DSI_PHY_REF of 17.05MHz (1/4). Instead use the 24 MHz clock as parent for DSI PHY reference clock. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 2a82e656b9fb..4cc5ad01d0e2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1148,8 +1148,10 @@ mipi_dsi: dsi@32e10000 { clocks = <&clk IMX8MM_CLK_DSI_CORE>, <&clk IMX8MM_CLK_DSI_PHY_REF>; clock-names = "bus_clk", "sclk_mipi"; - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; interrupts = ; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; status = "disabled"; From 70c6b1b4261a9bdded32821773cea9a7b14657e1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:10:24 +0100 Subject: [PATCH 094/139] arm64: dts: imx8mm-tqma8mqml-mba8mx: LVDS overlay: Reduce DSI burst clock to 600Mhz The DSI burst clock frequency is too high resulting in flickering. Reduce the frequency. While at it, remove the burst clock from board configuration as it is display specific. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso | 3 ++- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso index e5425653ea7e..046399a455ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso @@ -32,7 +32,8 @@ &lcdif { }; &mipi_dsi { - status = "okay"; + samsung,burst-clock-frequency = <600000000>; + status = "okay"; }; &panel { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index 8dcc5cbcb8f6..8490b7b04e9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -76,7 +76,6 @@ expander2: gpio@27 { }; &mipi_dsi { - samsung,burst-clock-frequency = <891000000>; samsung,esc-clock-frequency = <20000000>; }; From 1bc7c90aa1cec5ef098d8f686c3f555addcc3509 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 08:10:25 +0100 Subject: [PATCH 095/139] arm64: dts: imx8mn-tqma8mqnl-mba8mx: LVDS overlay: Reduce DSI burst clock to 600Mhz The DSI burst clock frequency is too high resulting in flickering. Reduce the frequency. While at it, remove the burst clock from board configuration as it is display specific. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- .../dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso | 1 + arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso index 0f4cf1855bf3..046399a455ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso @@ -32,6 +32,7 @@ &lcdif { }; &mipi_dsi { + samsung,burst-clock-frequency = <600000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index 664f4a6950a8..01d565cdbfea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -65,7 +65,6 @@ expander2: gpio@27 { }; &mipi_dsi { - samsung,burst-clock-frequency = <891000000>; samsung,esc-clock-frequency = <20000000>; }; From c7af54e6944be1508b251a255386e256bea14e99 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 13 Mar 2026 15:13:04 +0100 Subject: [PATCH 096/139] arm64: dts: imx95: Move funnel outside from soc The 'funnel' node does not contain a register range, so it should be placed outside of the soc node to fix schema warnings from simple-bus.yaml. Change is similar to commit 9cfe3c892b761 ("arm64: dts: imx8mp: Move funnel outside from soc") Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 92 ++++++++++++------------ 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index acb10bc14dd4..71394871d8dd 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -391,6 +391,52 @@ scmi_misc: protocol@84 { }; }; + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + + funnel1: funnel-sys { + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + mqs1: mqs-1 { compatible = "fsl,imx95-aonmix-mqs"; status = "disabled"; @@ -537,52 +583,6 @@ etm0_out_port: endpoint { }; }; - funnel0: funnel { - /* - * non-configurable funnel don't show up on the AMBA - * bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-funnel"; - status = "disabled"; - - in-ports { - port { - ca_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - }; - - out-ports { - port { - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - }; - }; - - funnel1: funnel-sys { - compatible = "arm,coresight-static-funnel"; - status = "disabled"; - - in-ports { - port { - hugo_funnel_in_port0: endpoint { - remote-endpoint = <&ca_funnel_out_port0>; - }; - }; - }; - - out-ports { - port { - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - }; - }; - etf: etf@41030000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x0 0x41030000 0x0 0x1000>; From d3ad2ce2116f1de4616a17414a186eb671cb83cf Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 13 Mar 2026 17:20:02 +0100 Subject: [PATCH 097/139] arm64: dts: freescale: Add support for Variscite DART-MX91 Add device tree support for the Variscite DART-MX91 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX91 MPU processor - Up to 2GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/ Signed-off-by: Stefano Radaelli Reviewed-by: Frank Li Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-var-dart.dtsi | 468 ++++++++++++++++++ 1 file changed, 468 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi new file mode 100644 index 000000000000..a9e44efad13f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX91 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx91.dtsi" + +/ { + model = "Variscite DART-MX91 Module"; + compatible = "variscite,var-dart-mx91", "fsl,imx91"; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + snps,clk-csr = <5>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + pinctrl-2 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_GATE>; + clock-names = "mclk"; + AVDD-supply = <&buck5>; + CPVDD-supply = <&buck5>; + DBVDD-supply = <&buck4>; + DCVDD-supply = <&buck5>; + MICVDD-supply = <&buck5>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + /* DMIC is connected to IN1L */ + wlf,in1l-as-dmicdat1; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +/* BT module */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&wifi_pwrseq>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e + >; + }; + + pinctrl_eqos_sleep: eqos-sleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e + MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e + MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1-sleepgrp { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e + MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e + MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e + >; + }; +}; From a69ba865a7c12bdbec6f4d9c346da31d5f577d4b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 13 Mar 2026 17:20:03 +0100 Subject: [PATCH 098/139] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board Add device tree support for the Variscite Sonata carrier board with the DART-MX91 system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - GPIO Expanders - RTC module - TPM module Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx91-var-dart-sonata.dts | 471 ++++++++++++++++++ 2 files changed, 472 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 47ad6e7ac810..88b16bb5b05c 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -441,6 +441,7 @@ imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb i imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-rgb-cdtech-dc44.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts new file mode 100644 index 000000000000..afa39dab240a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX91 + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx91-var-dart.dtsi" + +/ { + model = "Variscite DART-MX91 on Sonata-Board"; + compatible = "variscite,var-dart-mx91-sonata", + "variscite,var-dart-mx91", + "fsl,imx91"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + }; + + chosen { + stdout-path = &lpuart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label = "Up"; + linux,code = ; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label = "Down"; + linux,code = ; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-emmc { + label = "eMMC"; + gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x40000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +/* Use external instead of internal RTC */ +&bbnsm_rtc { + status = "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + /* USB Type-C Controller */ + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +/* Console (J10) */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header (J12.4, J12.6) */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO Expanders shared IRQ */ + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x37e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { + fsl,pins = < + MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e + MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX91_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX91_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; +}; From bec2988b470ef278c2e7238e8d7edd097853a4ea Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 13 Mar 2026 18:47:02 +0100 Subject: [PATCH 099/139] arm64: dts: freescale: Add support for Variscite DART-MX95 Add device tree support for the Variscite DART-MX95 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX95 MPU processor - Up to 16GB of LPDDR5 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx95-var-dart.dtsi | 425 ++++++++++++++++++ 1 file changed, 425 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi new file mode 100644 index 000000000000..a20fadacaa6d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX95 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx95.dtsi" + +/ { + model = "Variscite DART-MX95 Module"; + compatible = "variscite,var-dart-mx95", "fsl,imx95"; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio: regulator-audio-vdd { + compatible = "regulator-fixed"; + regulator-name = "wm8904_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 27 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + status = "okay"; +}; + +&lpi2c8 { + clock-frequency = <400000>; + pinctrl-names = "default","gpio","sleep"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + pinctrl-2 = <&pinctrl_lpi2c8_gpio>; + scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + DCVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +/* BT */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&mu7 { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>; + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-3 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + wakeup-source; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e + >; + }; + + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = < + IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e + IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = < + IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e + IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e + >; + }; + + pinctrl_phy0res: phy0resgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e + IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e + IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e + IMX95_PAD_GPIO_IO01__LPUART5_RX 0x31e + IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e + IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins = < + IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x31e + IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x31e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; From 496d258cf339743ba7fade3c6949b0cca64af80b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 13 Mar 2026 18:47:03 +0100 Subject: [PATCH 100/139] arm64: dts: imx95-var-dart: Add support for Variscite Sonata board Add device tree support for the Variscite Sonata carrier board with the DART-MX95 system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - 10Gb Ethernet SFP+ connector - Uart interfaces - OV5640 Camera support - GPIO Expanders - RTC module - TPM module - PCIE support Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx95-var-dart-sonata.dts | 595 ++++++++++++++++++ 2 files changed, 596 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 88b16bb5b05c..2da6dc4f8a14 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -496,6 +496,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts new file mode 100644 index 000000000000..0f3d2e488f4a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX95 + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +#include "imx95-var-dart.dtsi" + +/ { + model = "Variscite DART-MX95 on Sonata-Board"; + compatible = "variscite,var-dart-mx95-sonata", + "variscite,var-dart-mx95", + "fsl,imx95"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + ethernet2 = &enetc_port2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + clk_osc_can0: clock-osc-40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-back { + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + label = "Back"; + wakeup-source; + linux,code = ; + }; + + button-down { + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + label = "Down"; + wakeup-source; + linux,code = ; + }; + + button-home { + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + label = "Home"; + wakeup-source; + linux,code = ; + }; + + button-up { + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + label = "Up"; + wakeup-source; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-heartbeat { + label = "Heartbeat"; + gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_phy1_supply: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "SUPPLY_PHY1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; + + sfp0: sfp { + compatible = "sff,sfp"; + i2c-bus = <&lpi2c3>; + los-gpios = <&pca9534 1 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; +}; + +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; + phy-handle = <ðphy1>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + status = "okay"; +}; + +&enetc_port2 { + phy-mode = "10gbase-r"; + sfp = <&sfp0>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + pinctrl-2 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + pcie2-sel-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "pcie-clk-sw"; + }; + + sfp-sel-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sfp-sw"; + }; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio5>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; + + /* DS1337 RTC module */ + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio5>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; +}; + +&lpi2c8 { + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; +}; + +&lpspi7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi7>; + cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + spi-max-frequency = <1500000>; + wakeup-source; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header (J12.4, J12.6) */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&netc_emdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; +}; + +&pcie0 { + reset-gpio = <&pca6408_2 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1 { + reset-gpio = <&pca6408_2 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + adp-disable; + hnp-disable; + srp-disable; + disable-over-current; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; + + port@1 { + reg = <1>; + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; +}; + +&usb3_phy { + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO Expanders shared IRQ */ + IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x31e + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x57e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x57e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x37e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x31e + IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x31e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_lpspi7: lpspi7grp { + fsl,pins = < + /* j16.4 ADS7846 */ + IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe + /* j14.4 MCP2518FDT */ + IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x3fe + /* j25.2 spidev */ + IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x3fe + IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe + IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe + IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e + IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; From ab092e22218d2135e22660a931ad3588e0bb2b94 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 16 Mar 2026 10:14:36 +0800 Subject: [PATCH 101/139] arm64: dts: imx952: Add audio device nodes Add audio device nodes, include SAI, MICFIL, ASRC, Audio Mixer. Signed-off-by: Shengjiu Wang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952.dtsi | 203 ++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index b26e6e3dc773..b30707837f35 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -823,6 +823,160 @@ usdhc3: mmc@42c40000 { }; }; + aips5: bus@43000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x43000000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x43000000 0x0 0x43000000 0x800000>; + + asrc1: asrc@43000000 { + compatible = "fsl,imx952-asrc"; + reg = <0x43000000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_ASRC1>, + <&scmi_clk IMX952_CLK_ASRC2>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 97 0 0>, <&edma2 98 0 0>, <&edma2 99 0 0>, + <&edma2 100 0 FSL_EDMA_RX>, <&edma2 101 0 FSL_EDMA_RX>, + <&edma2 102 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + #sound-dai-cells = <0>; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; + }; + + asrc2: asrc@430f0000 { + compatible = "fsl,imx952-asrc"; + reg = <0x430f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_ASRC1>, + <&scmi_clk IMX952_CLK_ASRC2>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 103 0 0>, <&edma2 104 0 0>, <&edma2 105 0 0>, + <&edma2 106 0 FSL_EDMA_RX>, <&edma2 107 0 FSL_EDMA_RX>, + <&edma2 108 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + #sound-dai-cells = <0>; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; + }; + + amix: amix@431f0000 { + compatible = "fsl,imx952-audmix"; + reg = <0x431f0000 0x10000>; + clocks = <&scmi_clk IMX952_CLK_AUDMIX1>; + clock-names = "ipg"; + status = "disabled"; + }; + + sai3: sai@433e0000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x433e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai4: sai@433f0000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x433f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI4>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai5: sai@43400000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x43400000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI5>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai6: sai@43410000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x43410000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 96 0 FSL_EDMA_RX>, <&edma2 95 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + }; + gpio2: gpio@43810000 { compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; reg = <0x0 0x43810000 0x0 0x1000>; @@ -1062,6 +1216,40 @@ flexcan1: can@443a0000 { status = "disabled"; }; + sai1: sai@443b0000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x443b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI1>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx943-micfil"; + reg = <0x44520000 0x10000>; + interrupts = , + , + , + ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_PDM>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&clk_dummy>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&edma1 6 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>; + dma-names = "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + adc1: adc@44530000 { compatible = "nxp,imx93-adc"; reg = <0x44530000 0x10000>; @@ -1281,5 +1469,20 @@ usbmisc2: usbmisc@4c200200 { reg = <0x0 0x4c200200 0x0 0x200>, <0x0 0x4c010014 0x0 0x4>; }; + + sai2: sai@4c880000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x0 0x4c880000 0x0 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSNETCMIX>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI2>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + power-domains = <&scmi_devpd IMX952_PD_NETC>; + status = "disabled"; + }; }; }; From 1e191b6cd973fe331873b845400d1dc66d50547f Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 16 Mar 2026 10:14:37 +0800 Subject: [PATCH 102/139] arm64: dts: imx952-evk: Add sound-wm8962 support Add wm8962 sound card. By connecting with ASRC1, the sound card support sample rate conversion. ASRC2 is also enabled, which can provide memory to memory user interface. Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 119 +++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 509704c23e89..ef0058b98573 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -110,6 +110,15 @@ reg_vref_1v8: regulator-adc-vref { regulator-max-microvolt = <1800000>; }; + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&i2c4_pcal6408 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -131,6 +140,51 @@ reg_usb_vbus: regulator-vbus { enable-active-high; }; + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + audio-asrc = <&asrc1>; + audio-codec = <&wm8962>; + audio-cpu = <&sai3>; + audio-routing = "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + model = "wm8962-audio"; + pinctrl-0 = <&pinctrl_hp>; + pinctrl-names = "default"; + }; +}; + +&asrc1 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_ASRC1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc2 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_ASRC2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + fsl,asrc-rate = <48000>; + status = "okay"; }; /* pin conflict with PDM */ @@ -185,6 +239,27 @@ &lpi2c4 { pinctrl-0 = <&pinctrl_lpi2c4>; status = "okay"; + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&scmi_clk IMX952_CLK_SAI3>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + gpio-cfg = < 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + }; + i2c4_pcal6408: gpio@21 { compatible = "nxp,pcal6408"; reg = <0x21>; @@ -312,6 +387,24 @@ &lpspi7 { status = "okay"; }; +&sai3 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <12288000>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-1 = <&pinctrl_sai3_sleep>; + pinctrl-names = "default", "sleep"; + fsl,sai-amix-mode = "bypass"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &scmi_misc { nxp,ctrl-ids = ; }; + pinctrl_hp: hpgrp { + fsl,pins = < + IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x31e + >; + }; + pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e @@ -476,6 +575,26 @@ IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x31e + IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x31e + IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x31e + IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x31e + IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x31e + IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x31e + IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x31e + IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x31e + IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x31e + >; + }; + pinctrl_tpm3: tpm3grp { fsl,pins = < IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e From 27a0f0487b0eaa8eb1d663b61b56b5670cec8112 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 16 Mar 2026 10:14:38 +0800 Subject: [PATCH 103/139] arm64: dts: imx952-evk: Add bt-sco sound card support Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default. Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 59 ++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index ef0058b98573..2615fbb63145 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -43,6 +43,11 @@ aliases { spi6 = &lpspi7; }; + bt_sco_codec: audio-codec-bt-sco { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + chosen { stdout-path = &lpuart1; }; @@ -140,6 +145,25 @@ reg_usb_vbus: regulator-vbus { enable-active-high; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master = <&btcpu>; + simple-audio-card,format = "dsp_a"; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,name = "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + sound-dai = <&sai1>; + }; + }; + sound-wm8962 { compatible = "fsl,imx-audio-wm8962"; audio-asrc = <&asrc1>; @@ -387,6 +411,23 @@ &lpspi7 { status = "okay"; }; +&sai1 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <12288000>; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + pinctrl-names = "default", "sleep"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &sai3 { assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, @@ -575,6 +616,24 @@ IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x31e + IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e + IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e + IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x51e + IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x51e + IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x51e + IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x51e + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x31e From ae96aa9e0a2325db622dcc8f070fde286b5498da Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 16 Mar 2026 10:14:39 +0800 Subject: [PATCH 104/139] arm64: dts: imx952-evk: Add PDM microphone sound card support Add PDM micphone sound card support, configure the pinmux. This sound card supports recording sound from PDM microphone and convert the PDM format data to PCM data. Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 54 ++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 2615fbb63145..62d1c1c7c501 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -52,6 +52,12 @@ chosen { stdout-path = &lpuart1; }; + dmic: dmic { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <2>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; @@ -164,6 +170,24 @@ btcpu: simple-audio-card,cpu { }; }; + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + sound-wm8962 { compatible = "fsl,imx-audio-wm8962"; audio-asrc = <&asrc1>; @@ -411,6 +435,22 @@ &lpspi7 { status = "okay"; }; +&micfil { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-1 = <&pinctrl_pdm_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, @@ -604,6 +644,20 @@ IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x31e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x31e + >; + }; + pinctrl_ptn5110: ptn5110grp { fsl,pins = < IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e From e2bb524f4bff2f9cd8bafc62daba02cb6558fe9e Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 17 Mar 2026 11:04:18 +0800 Subject: [PATCH 105/139] arm64: dts: imx95-15x15-evk: remove regulator-always-on for reg_m2_pwr Now we use vpcie3v3aux-supply to keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle, no need regulator-always-on property. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index d4184fb8b28c..7eb12e7d5014 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -116,7 +116,6 @@ flexcan2_phy: can-phy { reg_m2_pwr: regulator-m2-pwr { compatible = "regulator-fixed"; - regulator-always-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "M.2-power"; From 0083b7be1b3e097209de38c0eb9abd5b3e9dc2f1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 16 Mar 2026 14:58:18 +0100 Subject: [PATCH 106/139] arm64: dts: mba8mx: Add DSI->LVDS bridge IRQ Now that the bindings supports IRQ, add the IRQ line. Add a GPIO label as well. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/mba8mx.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 10d5c211b1c9..c24ae953cbc2 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -209,7 +209,7 @@ expander0: gpio@23 { interrupt-controller; #interrupt-cells = <2>; gpio-line-names = "", "", "", "", - "", "", "LVDS_BRIDGE_EN", "", + "", "", "LVDS_BRIDGE_EN", "LVDS_BRIDGE_IRQ", "", "", "", "", "", "", "", ""; @@ -298,6 +298,8 @@ dsi_lvds_bridge: bridge@2d { reg = <0x2d>; enable-gpios = <&gpio_delays 0 130000 0>; vcc-supply = <®_sn65dsi83_1v8>; + interrupt-parent = <&expander0>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; status = "disabled"; ports { From 18955d59419de7da1bc29247f0c854e4785b94fd Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 16 Mar 2026 14:58:19 +0100 Subject: [PATCH 107/139] arm64: dts: freescale: tqma8mqml/tqma8mxnl-mba8mx: Add dual-channel LVDS overlay Add an overlay for the supported LVDS display AUO G133HAN01. Apply it for both TQMa8MxML and TQMa8MxNL. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 + ...mx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso | 86 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 2da6dc4f8a14..3c01377bba10 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -183,7 +183,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb +imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb @@ -219,8 +221,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \ imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtb \ imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo +imx8mn-tqma8mqnl-mba8mx-lvds-g133han01-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-usbotg.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso new file mode 100644 index 000000000000..ce12bc46553d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&backlight_lvds { + status = "okay"; +}; + +&dsi_lvds_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + lvds_bridge_out0: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + port@3 { + reg = <3>; + + lvds_bridge_out1: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&expander0 { + dsi-mux-oe-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-high; + line-name = "DSI_MUX_OE#"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel { + compatible = "auo,g133han01"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds_bridge_out0>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds_bridge_out1>; + }; + }; + }; +}; From 20288505481c083d76f706319aa58159b779bf41 Mon Sep 17 00:00:00 2001 From: Martin Schmiedel Date: Thu, 19 Mar 2026 13:50:09 +0100 Subject: [PATCH 108/139] arm64: dts: freescale: add initial device tree for TQMa93xx/MBa93xxLA-MINI Add support for TQMa93xx module attached to MBa93xxLA-MINI board. TQMa93xx is a SOM series using i.MX93 SOC. The MBa93xxLA-MINI has a small form factor and is designed with WLAN, Bluetooth and WWAN applications in mind. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Reviewed-by: Andrew Lunn Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx93-tqma9352-mba93xxla-mini.dts | 598 ++++++++++++++++++ 2 files changed, 599 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 3c01377bba10..28b51282fd57 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -485,6 +485,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts new file mode 100644 index 000000000000..4afd6b650d9d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "imx93-tqma9352.dtsi" + +/{ + model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA-MINI SBC"; + compatible = "tq,imx93-tqma9352-mba93xxla-mini", + "tq,imx93-tqma9352", "fsl,imx93"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0_usb: regulator-5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&expander0 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +/* deactivated because pins are used for SDIO */ +&flexspi1 { + status = "disabled"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_m2_key_b>, <&pinctrl_m2_key_e>; + + gpio-line-names = + /* 00 */ "", "", "M2_KEYE_ALERT#", "", + /* 04 */ "", "", "M2_KEYE_UART_WAKE#", "BM1_M2_KEYE_SDIO_WAKE#", + /* 08 */ "", "", "", "BM2_M2_KEYE_SDIO_RST#", + /* 12 */ "M2_KEYB_WOWWAN#", "BM3_M2_KEYB_PEWAKE#", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "LVDS_RESET#", "LVDS_BLT_EN", "", "LVDS_PWR_EN", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "X1_9", "X1_19", "X1_15", "X1_11", + /* 20 */ "X1_13", "X1_7", "", "CAM_TRIGGER", + /* 24 */ "CAM_SYNC", "", "X1_5", "", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "DSI_GPIO", "", ""; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "M2_KEYE_PERST#", "M2_KEYB_PERST#", + "M2_KEYE_W_DISABLE1#", "M2_KEYE_W_DISABLE2#", + "M2_KEYA_W_DISABLE1#", "12V_EN"; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "USB_HUB_PWR", "DSI_RST#", + "CAM_PWR#", "CAMRST#", + "M2_KEYB_FULL_CARD_PWR_OFF#", "M2_KEYB_W_DISABLE2#", + "M2_KEYB_RST#", "M2_KEYB_DPR"; + + /* + * Controls the LTE card FULL_CARD_PWR_OFF pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + full-card-power-off-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_FULL_CARD_PWR_OFF#"; + }; + + /* + * Controls the LTE card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_RST#"; + }; + }; +}; + +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* disabled per default, console for M33 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "disabled"; +}; + +/* disabled per default, used for bluetooth on M.2 slot */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; + status = "disabled"; +}; + +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0_usb>; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + hub_2_0: usb-hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + disable-wp; + no-sdio; + no-mmc; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3v3>; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X5 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X5 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + , + ; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { + fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins = /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + ; + }; + + pinctrl_lpspi6_cs: lpspi6csgrp { + fsl,pins = /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_m2_key_b: m2keybgrp { + fsl,pins = , + ; + }; + + pinctrl_m2_key_e: m2keyegrp { + fsl,pins = , + , + , + ; + }; + + /*CAM_MCLK, DSI_GPIO, CAM_TRIGGER, CAM_SYNC*/ + pinctrl_mipi_csi_dsi: mipi_csi_dsigrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X5 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + /* HYS | PU | FSEL_3 | DSE X3 */ + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X6 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = /* PD | FSEL_3 | DSE X6 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + , + , + , + ; + }; +}; From 9754620110bf352e1c6f7ccd83c5388610157fd2 Mon Sep 17 00:00:00 2001 From: Martin Schmiedel Date: Thu, 19 Mar 2026 13:50:10 +0100 Subject: [PATCH 109/139] arm64: dts: freescale: imx93-tqma9352-mba93xxla-mini: Add WLAN/BT overlay This overlay enables the LWB5+ M.2 wlan module from ezurio. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 +++ ...3-tqma9352-mba93xxla-mini-ezurio-wlan.dtso | 35 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 28b51282fd57..0858471420c3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -492,6 +492,10 @@ imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb im dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb +imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso new file mode 100644 index 000000000000..12a14d871103 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&lpuart7 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4329-bt"; + vbat-supply = <®_3v3>; + vddio-supply = <®_3v3>; + shutdown-gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf_sdio: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; +}; From 70db6463c920e059cc3edfe7dfeb9c33c742da82 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 23 Mar 2026 13:59:50 +0100 Subject: [PATCH 110/139] arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: add vcc supply for BT device Add the vcc power supply for the BT device. Fixes the warning: btnxpuart serial0-0: supply vcc not found, using dummy regulator Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 94e2a7df3556..90d6b5ae215f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -587,6 +587,7 @@ &uart2 { bluetooth { compatible = "nxp,88w8987-bt"; + vcc-supply = <®_vcc_3v3>; }; }; From 676d7ce22f002685ae624d922357fddbd2288cfe Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Wed, 25 Mar 2026 15:46:03 +0100 Subject: [PATCH 111/139] arm64: dts: freescale: Add Verdin iMX95 support Add support for the Toradex Verdin iMX95 and its development carrier board. The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR4x RAM, up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit Ethernet PHY, an I2C EEPROM and Temperature Sensor, an RX8130 RTC, an I3C bus, one Quad lane CSI interface, one Quad lane DSI or CSI interface, one LVDS interface (one or two channels), and some optional addons: TPM 2.0, and a WiFi/BT module. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Co-developed-by: Emanuele Ghidoli Signed-off-by: Emanuele Ghidoli Co-developed-by: Francesco Dolcini Signed-off-by: Francesco Dolcini Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../boot/dts/freescale/imx95-verdin-dev.dtsi | 250 ++++ .../freescale/imx95-verdin-nonwifi-dev.dts | 21 + .../dts/freescale/imx95-verdin-nonwifi.dtsi | 16 + .../dts/freescale/imx95-verdin-wifi-dev.dts | 21 + .../boot/dts/freescale/imx95-verdin-wifi.dtsi | 50 + .../boot/dts/freescale/imx95-verdin.dtsi | 1162 +++++++++++++++++ 7 files changed, 1522 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0858471420c3..97916edf706b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -506,6 +506,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi new file mode 100644 index 000000000000..2848f9adf152 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + clocks = <&scmi_clk IMX95_CLK_SAI3>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3_mclk>; + #sound-dai-cells = <0>; + }; + + carrier_gpio_expander: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&lpuart7 { + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +&netc_emdio { + ethphy2: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&sai3 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..97636ec7c26a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Verdin Development Board"; + compatible = "toradex,verdin-imx95-nonwifi-dev", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..7aba22067de5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM non-WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +/* SDIO on MSP 30, 31, 32, 33, 34, 35 */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts new file mode 100644 index 000000000000..345d37247025 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Verdin Development Board"; + compatible = "toradex,verdin-imx95-wifi-dev", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi new file mode 100644 index 000000000000..256c9ed04605 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + /* PMIC_EN_WIFI */ + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_MAYA-W260"; + startup-delay-us = <2000>; + }; +}; + +/* On-module Bluetooth */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + uart-has-rtscts; + + status = "okay"; + + som_bt: bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_wifi_en>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi new file mode 100644 index 000000000000..d3737956e2f9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi @@ -0,0 +1,1162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +#include +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + i2c0 = &lpi2c2; + i2c1 = &lpi2c4; + i2c2 = &lpi2c3; + i2c3 = &i3c2; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart7; + serial1 = &lpuart8; + serial2 = &lpuart1; + serial3 = &lpuart2; + serial4 = &lpuart6; + usb0 = &usb2; + usb1 = &usb3; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + /* Verdin USB_1_ID (SODIMM 161) */ + id-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb1_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_id>; + }; + }; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + verdin_key_wakeup: key-wakeup { + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_1_EN (SODIMM 155) */ + gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_2_EN (SODIMM 185) */ + gpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_EN"; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_SD2_VSEL"; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + cm7: remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; +}; + +&gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_20", + "SODIMM_22", + "SODIMM_252", /* 10 */ + "", + "SODIMM_189", + "IO_EXP_INT", + "SODIMM_256", + ""; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = + "SODIMM_206", /* 0 */ + "SODIMM_198", + "SODIMM_200", + "SODIMM_196", + "", + "SODIMM_15", + "SODIMM_16", + "", + "SODIMM_131", + "SODIMM_129", + "SODIMM_135", /* 10 */ + "SODIMM_133", + "SODIMM_139", + "SODIMM_137", + "SODIMM_143", + "SODIMM_141", + "SODIMM_30", + "SODIMM_38", + "SODIMM_208", + "SODIMM_19", + "SODIMM_36", /* 20 */ + "SODIMM_34", + "SODIMM_93", + "SODIMM_95", + "SODIMM_210", + "SODIMM_24", + "SODIMM_32", + "SODIMM_26", + "SODIMM_53", + "SODIMM_55", + "SODIMM_12", /* 30 */ + "SODIMM_14"; +}; + +&gpio3 { + gpio-line-names = + "SODIMM_84", /* 0 */ + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72", + "SODIMM_76", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "PMIC_SD2_VSEL", + "", /* 20 */ + "", + "", + "", + "", + "", + "SODIMM_91", + "SODIMM_218", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio4 { + gpio-line-names = + "SODIMM_59", /* 0 */ + "SODIMM_57", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "SODIMM_193", + "SODIMM_191", + "SODIMM_215", + "SODIMM_217", + "SODIMM_219", + "SODIMM_221", + "SODIMM_211", /* 20 */ + "SODIMM_213", + "SODIMM_199", + "SODIMM_197", + "SODIMM_201", + "SODIMM_203", + "SODIMM_205", + "SODIMM_207", + "SODIMM_216", + "SODIMM_202"; +}; + +&gpio5 { + gpio-line-names = + "SODIMM_56", /* 0 */ + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_46", + "SODIMM_44", + "SODIMM_42", + "SODIMM_48", + "SODIMM_66", + "SODIMM_52", + "SODIMM_54", /* 10 */ + "SODIMM_64", + "SODIMM_212", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <400000>; +}; + +/* CTRL_I2C (On-module I2C) */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>; + clock-frequency = <400000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + + status = "okay"; + + som_gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "SODIMM_220", /* 0 */ + "SODIMM_222", + "SODIMM_17", + "SODIMM_21", + "SODIMM_244", + "SODIMM_161", + "SODIMM_157", + "SODIMM_155", + "SODIMM_185", + "SODIMM_187", + "USB_RECOV_CTRL#", /* 10 */ + "ENET1_INT#", + "TPM_INT#", + "TPM_CS#", + "", + ""; + + /* + * Switch USB to default position: + * - SoC USB2 -> Verdin USB_1 + * - SoC USB1 -> Verdin USB_2 + * Reset configuration: + * - SoC USB1 -> Verdin USB_1 (USB recovery) + * - SoC USB2 not connected + */ + usb_recov_ctrl: usb-recov-ctrl-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "USB_RECOV_CTRL#"; + output-high; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi6's per-clock (twice the max speed) is 24 MHz + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Verdin UART_1 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_bus0 { + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>; +}; + +/* Verdin I2S_1 */ +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = ; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Verdin PWM_1 */ +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm4>; +}; + +/* Verdin PWM_2 */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; +}; + +/* Verdin USB_1 */ +&usb2 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; + vbus-supply = <®_usb1_vbus>; + + port { + usb1_id: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "host"; +}; + +&usb3_phy { + vbus-supply = <®_usb2_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* On-module Bluetooth on WB SKUs, module-specific UART otherwise */ + pinctrl_bt_uart: btuartgrp { + fsl,pins = , /* WiFi_UART_SoC_TXD */ + , /* WiFi_UART_SoC_RXD */ + , /* WiFi_UART_SoC_CTS */ + ; /* WiFi_UART_SoC_RTS */ + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_csi1_mclk: csi1mclkgrp { + fsl,pins = ; /* SODIMM 91 */ + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = ; /* SODIMM 256 */ + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = ; /* SODIMM 252 */ + }; + + /* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ + pinctrl_emdio: emdiogrp { + fsl,pins = , /* ENET2_MDC, SODIMM 193 */ + ; /* ENET2_MDIO, SODIMM 191 */ + }; + + /* Verdin ETH_1 (On-module PHY) */ + pinctrl_enetc0: enetc0grp { + fsl,pins = , /* ENET1_TX_CTL */ + , /* ENET1_TXC */ + , /* ENET1_TDO */ + , /* ENET1_TD1 */ + , /* ENET1_TD2 */ + , /* ENET1_TD3 */ + , /* ENET1_RX_CTL */ + , /* ENET1_RXC */ + , /* ENET1_RD0 */ + , /* ENET1_RD1 */ + , /* ENET1_RD2 */ + ; /* ENET1_RD3 */ + }; + + /* Verdin ETH_2_RGMII */ + pinctrl_enetc1: enetc1grp { + fsl,pins = , /* ENET2_TX_CTL */ + , /* ENET2_TXC */ + , /* ENET2_TD0 */ + , /* ENET2_TD1 */ + , /* ENET2_TD2 */ + , /* ENET2_TD3 */ + , /* ENET2_RX_CTL */ + , /* ENET2_RXC */ + , /* ENET2_RD0 */ + , /* ENET2_RD1 */ + , /* ENET2_RD2 */ + ; /* ENET2_RD3 */ + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: eth2rgmiiintgrp { + fsl,pins = ; /* SODIMM 189 */ + }; + + /* Verdin CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , /* SODIMM 20 */ + ; /* SODIMM 22 */ + }; + + /* Verdin CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , /* SODIMM 24 */ + ; /* SODIMM 26 */ + }; + + /* Verdin QSPI_1 */ + pinctrl_flexspi1: flexspi1grp { + fsl,pins = , /* SODIMM 54 */ + , /* SODIMM 64 */ + , /* SODIMM 52 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + , /* SODIMM 62 */ + ; /* SODIMM 66 */ + }; + + /* Verdin GPIO_1 */ + pinctrl_gpio1: gpio1grp { + fsl,pins = ; /* SODIMM 206 */ + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = ; /* SODIMM 208 */ + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = ; /* SODIMM 210 */ + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = ; /* SODIMM 212 */ + }; + + /* Verdin GPIO_5_CSI */ + pinctrl_gpio5: gpio5grp { + fsl,pins = ; /* SODIMM 216 */ + }; + + /* Verdin GPIO_6_CSI */ + pinctrl_gpio6: gpio6grp { + fsl,pins = ; /* SODIMM 218 */ + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp { + fsl,pins = ; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp { + fsl,pins = ; /* SODIMM 48 */ + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp { + fsl,pins = ; /* SODIMM 46 */ + }; + + /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp { + fsl,pins = ; /* SODIMM 44 */ + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = , /* SODIMM 59 */ + ; /* SODIMM 57 */ + }; + + pinctrl_io_exp_int: ioexpintgrp { + fsl,pins = ; /* IO_EXP_INT */ + }; + + /* CTRL_I2C (On-module I2C) */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = , /* CTRL_I2C_SCL */ + ; /* CTRL_I2C_SDA */ + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , /* CTRL_I2C_SCL */ + ; /* CTRL_I2C_SDA */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = , /* SODIMM 53 */ + ; /* SODIMM 55 */ + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , /* SODIMM 53 */ + ; /* SODIMM 55 */ + }; + + /* Verdin I2C_1 */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = , /* SODIMM 93 */ + ; /* SODIMM 95 */ + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = , /* SODIMM 93 */ + ; /* SODIMM 95 */ + }; + + /* Verdin SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = , /* SODIMM 198 */ + , /* SODIMM 200 */ + ; /* SODIMM 196 */ + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: qspi1clkgpiogrp { + fsl,pins = ; /* SODIMM 52 */ + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp { + fsl,pins = ; /* SODIMM 64 */ + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: qspi1csgpiogrp { + fsl,pins = ; /* SODIMM 54 */ + }; + + /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp { + fsl,pins = ; /* SODIMM 66 */ + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: qspi1io0gpiogrp { + fsl,pins = ; /* SODIMM 56 */ + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: qspi1io1gpiogrp { + fsl,pins = ; /* SODIMM 58 */ + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: qspi1io2gpiogrp { + fsl,pins = ; /* SODIMM 60 */ + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: qspi1io3gpiogrp { + fsl,pins = ; /* SODIMM 62 */ + }; + + /* Verdin I2S_1 */ + pinctrl_sai3: sai3grp { + fsl,pins = , /* SODIMM 30 */ + , /* SODIMM 36 */ + , /* SODIMM 34 */ + ; /* SODIMM 32 */ + }; + + /* Verdin I2S_1_MCLK */ + pinctrl_sai3_mclk: sai3mclkgrp { + fsl,pins = ; /* SODIMM 38 */ + }; + + /* Verdin I2S_2 */ + pinctrl_sai5: sai5grp { + fsl,pins = , /* SODIMM 46 */ + , /* SODIMM 44 */ + , /* SODIMM 42 */ + ; /* SODIMM 48 */ + }; + + /* Verdin SPI_1_CS */ + pinctrl_spi1_cs: spi1csgrp { + fsl,pins = ; /* SODIMM 202 */ + }; + + /* Verdin PWM_1 */ + pinctrl_tpm4: tpm4grp { + fsl,pins = ; /* SODIMM 15 */ + }; + + /* Verdin PWM_2 */ + pinctrl_tpm5: tpm5grp { + fsl,pins = ; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_tpm6_gpio: tpm6gpiogrp { + fsl,pins = ; /* SODIMM 19 */ + }; + + /* Verdin PWM_3_DSI */ + pinctrl_tpm6: tpm6grp { + fsl,pins = ; /* SODIMM 19 */ + }; + + /* Verdin UART_3, used as the Linux Console */ + pinctrl_uart1: uart1grp { + fsl,pins = , /* SODIMM 147 */ + ; /* SODIMM 149 */ + }; + + /* Verdin UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + /* Verdin UART_1 */ + pinctrl_uart7: uart7grp { + fsl,pins = , /* SODIMM 131 */ + , /* SODIMM 129 */ + , /* SODIMM 135 */ + ; /* SODIMM 133 */ + }; + + /* Verdin UART_2 */ + pinctrl_uart8: uart8grp { + fsl,pins = , /* SODIMM 139 */ + , /* SODIMM 137 */ + , /* SODIMM 143 */ + ; /* SODIMM 141 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , /* SD1_CLK */ + , /* SD1_CMD */ + , /* SD1_DATA0 */ + , /* SD1_DATA1 */ + , /* SD1_DATA2 */ + , /* SD1_DATA3 */ + , /* SD1_DATA4 */ + , /* SD1_DATA5 */ + , /* SD1_DATA6 */ + , /* SD1_DATA7 */ + ; /* SD1_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , /* SD1_CLK */ + , /* SD1_CMD */ + , /* SD1_DATA0 */ + , /* SD1_DATA1 */ + , /* SD1_DATA2 */ + , /* SD1_DATA3 */ + , /* SD1_DATA4 */ + , /* SD1_DATA5 */ + , /* SD1_DATA6 */ + , /* SD1_DATA7 */ + ; /* SD1_STROBE */ + }; + + /* Verdin SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + /* Verdin SD_1_CD# */ + pinctrl_usdhc2_cd: usdhc2-cdgrp { + fsl,pins = ; /* SODIMM 84 */ + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { + fsl,pins = ; /* SODIMM 76 */ + }; + + pinctrl_usdhc2_vsel: usdhc2-vselgrp { + fsl,pins = ; /* PMIC_SD2_VSEL */ + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , /* SD3_CLK */ + , /* SD3_CMD */ + , /* SD3_DATA0 */ + , /* SD3_DATA1 */ + , /* SD3_DATA2 */ + ; /* SD3_DATA3 */ + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , /* SD3_CLK */ + , /* SD3_CMD */ + , /* SD3_DATA1 */ + , /* SD3_DATA2 */ + , /* SD3_DATA3 */ + ; /* SD3_DATA4 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = ; /* PMIC_EN_WIFI */ + }; +}; From e79c2c016b4389c762678bb4078fb262dccb00b5 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Wed, 25 Mar 2026 15:46:04 +0100 Subject: [PATCH 112/139] arm64: dts: freescale: imx95-verdin: Add Dahlia carrier board Add support for the Verdin i.MX95 mated with the Verdin Dahlia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx95-verdin-dahlia.dtsi | 270 ++++++++++++++++++ .../freescale/imx95-verdin-nonwifi-dahlia.dts | 21 ++ .../freescale/imx95-verdin-wifi-dahlia.dts | 21 ++ 4 files changed, 314 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 97916edf706b..26e508e3d218 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -506,7 +506,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi new file mode 100644 index 000000000000..889b71aa3de0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Dahlia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + reg_1v8_sw: regulator-1v8-sw { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier +V1.8_SW"; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "PCIE_1_PWR_EN"; + }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_1v8_sw>; + CPVDD-supply = <®_1v8_sw>; + DBVDD-supply = <®_1v8_sw>; + DCVDD-supply = <®_1v8_sw>; + MICVDD-supply = <®_1v8_sw>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + vpcie-supply = <®_pcie>; + + status = "okay"; +}; + +/* We support turning off sleep moci on Dahlia */ +®_force_sleep_moci { + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&sai3 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_dwc3 { + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_3_0: usb-hub@1 { + compatible = "usb424,5744"; + reg = <1>; + peer-hub = <&usb_hub_2_0>; + vdd-supply = <®_usb_hub>; + }; + + usb_hub_2_0: usb-hub@2 { + compatible = "usb424,2744"; + reg = <2>; + peer-hub = <&usb_hub_3_0>; + vdd-supply = <®_usb_hub>; + }; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..16975ae12fcb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Dahlia Board"; + compatible = "toradex,verdin-imx95-nonwifi-dahlia", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..bafbe1179ec8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Dahlia Board"; + compatible = "toradex,verdin-imx95-wifi-dahlia", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; From f33a1f9a942cba6c7454c5c2290395961a986f6f Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Wed, 25 Mar 2026 15:46:05 +0100 Subject: [PATCH 113/139] arm64: dts: freescale: imx95-verdin: Add Ivy carrier board Add support for the Verdin i.MX95 SoM mated with the Ivy carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/ivy-carrier-board Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../boot/dts/freescale/imx95-verdin-ivy.dtsi | 515 ++++++++++++++++++ .../freescale/imx95-verdin-nonwifi-ivy.dts | 21 + .../dts/freescale/imx95-verdin-wifi-ivy.dts | 21 + 4 files changed, 559 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 26e508e3d218..72eab6e87146 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -508,8 +508,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi new file mode 100644 index 000000000000..8337c8b25f05 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi @@ -0,0 +1,515 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Ivy carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +#include +#include +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + ain1-current { + compatible = "io-channel-mux"; + channels = "", "ain1_current"; + io-channels = <&ain1_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain1-voltage { + compatible = "io-channel-mux"; + channels = "ain1_voltage", ""; + io-channels = <&ain1_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain2-current { + compatible = "io-channel-mux"; + channels = "", "ain2_current"; + io-channels = <&ain2_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain2-voltage { + compatible = "io-channel-mux"; + channels = "ain2_voltage", ""; + io-channels = <&ain2_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + /* AIN1 Current w/o AIN1_MODE gpio control */ + ain1_current_unmanaged: current-sense-shunt-ain1 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc1 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* AIN2 Current w/o AIN2_MODE gpio control */ + ain2_current_unmanaged: current-sense-shunt-ain2 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc2 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* Ivy Power Supply Input Voltage */ + ivy-1v8-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_4 */ + io-channels = <&adc1 3>; + full-ohms = <39000>; /* 12k + 27k */ + output-ohms = <27000>; + }; + + ivy-3v3-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_3 */ + io-channels = <&adc1 2>; + full-ohms = <54000>; /* 27k + 27k */ + output-ohms = <27000>; + }; + + ivy-5v-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_2 */ + io-channels = <&adc1 1>; + full-ohms = <39000>; /* 27k + 12k */ + output-ohms = <12000>; + }; + + ivy-input-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_1 */ + io-channels = <&adc1 0>; + full-ohms = <204700>; /* 200k + 4.7k */ + output-ohms = <4700>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ivy_leds>; + + /* D7 Blue - SODIMM 30 - LEDs.GPIO1 */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Green - SODIMM 32 - LEDs.GPIO2 */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Red - SODIMM 34 - LEDs.GPIO3 */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Blue - SODIMM 36 - LEDs.GPIO4 */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Green - SODIMM 54 - LEDs.GPIO5 */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Red - SODIMM 44 - LEDs.GPIO6 */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Blue - SODIMM 46 - LEDs.GPIO7 */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Red - SODIMM 48 - LEDs.GPIO8 */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + }; + + /* AIN1_MODE - SODIMM 216 */ + ain1_mode_mux_ctrl: mux-controller-0 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + #mux-control-cells = <0>; + mux-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + /* AIN2_MODE - SODIMM 218 */ + ain2_mode_mux_ctrl: mux-controller-1 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; + #mux-control-cells = <0>; + mux-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + }; + + reg_3v2_ain1: regulator-3v2-ain1 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN1"; + }; + + reg_3v2_ain2: regulator-3v2-ain2 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN2"; + }; + + /* AIN1 Voltage w/o AIN1_MODE gpio control */ + ain1_voltage_unmanaged: voltage-divider-ain1 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc1 0>; + full-ohms = <19>; + output-ohms = <1>; + }; + + /* AIN2 Voltage w/o AIN2_MODE gpio control */ + ain2_voltage_unmanaged: voltage-divider-ain2 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc2 0>; + full-ohms = <19>; + output-ohms = <1>; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + gpio-line-names = ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>, + <&pinctrl_gpio3>; + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "GPIO2", /* Verdin GPIO_2 - SODIMM 208 */ + "", + "", /* 20 */ + "", + "", + "", + "GPIO3", /* Verdin GPIO_3 - SODIMM 210 */ + "", + "", + "", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio3 { + gpio-line-names = ""; +}; + +&gpio4 { + gpio-line-names = ""; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_cs2_gpio>, + <&pinctrl_qspi1_dqs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + gpio-line-names = + "DIGI_1", /* SODIMM 56 */ + "DIGI_2", /* SODIMM 58 */ + "REL1", /* SODIMM 60 */ + "REL2", /* SODIMM 62 */ + "", + "", + "", + "", + "REL4", /* SODIMM 66 */ + "", + "", /* 10 */ + "REL3", /* SODIMM 64 */ + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; + + ivy_adc1: adc@40 { + compatible = "ti,ads1119"; + reg = <0x40>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain1>; + dvdd-supply = <®_3v2_ain1>; + vref-supply = <®_3v2_ain1>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN1 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN1 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; + + ivy_adc2: adc@41 { + compatible = "ti,ads1119"; + reg = <0x41>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain2>; + dvdd-supply = <®_3v2_ain2>; + vref-supply = <®_3v2_ain2>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN2 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN2 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, + <&pinctrl_spi1_cs>, + <&pinctrl_gpio1>, + <&pinctrl_gpio4>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>, + <&gpio2 0 GPIO_ACTIVE_LOW>, + <&gpio5 12 GPIO_ACTIVE_LOW>; + + tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <2>; + spi-max-frequency = <18500000>; + }; + + fram@3 { + compatible = "fujitsu,mb85rs256", "atmel,at25"; + reg = <3>; + address-width = <16>; + size = <32768>; + spi-max-frequency = <33000000>; + pagesize = <1>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2, through RS485 transceiver */ +&lpuart8 { + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +&netc_emdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +&som_gpio_expander { + gpio-line-names = ""; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_ivy_leds: ivyledsgrp { + fsl,pins = , /* SODIMM 30 */ + , /* SODIMM 32 */ + , /* SODIMM 34 */ + , /* SODIMM 36 */ + , /* SODIMM 44 */ + , /* SODIMM 46 */ + , /* SODIMM 48 */ + ; /* SODIMM 54 */ + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts new file mode 100644 index 000000000000..ebe1aec1ffa4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Ivy Board"; + compatible = "toradex,verdin-imx95-nonwifi-ivy", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts new file mode 100644 index 000000000000..7ff2d03a254d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Ivy Board"; + compatible = "toradex,verdin-imx95-wifi-ivy", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; From 2f71fba0a082df525037473568743f1e5454107b Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Wed, 25 Mar 2026 15:46:06 +0100 Subject: [PATCH 114/139] arm64: dts: freescale: imx95-verdin: Add Mallow carrier board Add support for the Verdin i.MX95 SoM mated with the Mallow carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/mallow-carrier-board Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx95-verdin-mallow.dtsi | 223 ++++++++++++++++++ .../freescale/imx95-verdin-nonwifi-mallow.dts | 21 ++ .../freescale/imx95-verdin-wifi-mallow.dts | 21 ++ 4 files changed, 267 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 72eab6e87146..89846d3ea53f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -509,9 +509,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi new file mode 100644 index 000000000000..53506b7550f5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Mallow carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>; + + /* SODIMM 52 - USER_LED_1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 54 - USER_LED_1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 56 - USER_LED_2_RED */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 58 - USER_LED_2_GREEN */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, + <&pinctrl_spi1_cs>, + <&pinctrl_qspi1_cs2_gpio>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>, + <&gpio5 11 GPIO_ACTIVE_LOW>; + + tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts new file mode 100644 index 000000000000..5a9c0e4a79c9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Mallow Board"; + compatible = "toradex,verdin-imx95-nonwifi-mallow", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts new file mode 100644 index 000000000000..eaa67a39be1c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Mallow Board"; + compatible = "toradex,verdin-imx95-wifi-mallow", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; From e77f8e6bba733392896b978548cc771c143280d8 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Wed, 25 Mar 2026 15:46:07 +0100 Subject: [PATCH 115/139] arm64: dts: freescale: imx95-verdin: Add Yavia carrier board Add support for the Verdin i.MX95 SoM mated with the Yavia carrier board. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/yavia Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../freescale/imx95-verdin-nonwifi-yavia.dts | 21 ++ .../dts/freescale/imx95-verdin-wifi-yavia.dts | 21 ++ .../dts/freescale/imx95-verdin-yavia.dtsi | 217 ++++++++++++++++++ 4 files changed, 261 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 89846d3ea53f..c7ccf529ee1a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -510,10 +510,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts new file mode 100644 index 000000000000..4f7b4e3a518b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Yavia Board"; + compatible = "toradex,verdin-imx95-nonwifi-yavia", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts new file mode 100644 index 000000000000..43d35b770db2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Yavia Board"; + compatible = "toradex,verdin-imx95-wifi-yavia", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi new file mode 100644 index 000000000000..6403ae584e70 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Yavia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/yavia + */ + +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + + /* SODIMM 52 - LD1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 54 - LD1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 56 - LD1_BLUE */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 58 - LD2_RED */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 60 - LD2_GREEN */ + led-4 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 62 - LD2_BLUE */ + led-5 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>, + <&pinctrl_qspi1_cs2_gpio>, + <&pinctrl_qspi1_dqs_gpio>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; From 95d7d7d2ad27d2c1246fbb486628567b47109a21 Mon Sep 17 00:00:00 2001 From: Fabian Pfitzner Date: Wed, 25 Mar 2026 17:01:49 +0100 Subject: [PATCH 116/139] arm64: dts: imx8mp-frdm: add sd, ethernet, wifi, usb and hdmi support Add support for the following new features: - SD Card - Ethernet (FEC + EQOS) - Wifi - USB - HDMI Signed-off-by: Fabian Pfitzner Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 406 ++++++++++++++++++ 1 file changed, 406 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts index d69d78fed4e1..5fb9714215bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -42,6 +42,67 @@ memory@40000000 { reg = <0x0 0x40000000 0 0xc0000000>, <0x1 0x00000000 0 0x40000000>; }; + + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_usdhc2_vmmc: regulator-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc1_vmmc: regulator-wifi-vmmc { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + enable-active-high; + startup-delay-us = <20000>; + }; + + reg_usdhc1_vqmmc: regulator-wifi-vqmmc { + compatible = "regulator-fixed"; + regulator-name = "regulator-wifi-vqmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; + + sdio_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; }; &A53_0 { @@ -60,6 +121,146 @@ &A53_3 { cpu-supply = <®_arm>; }; +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + eee-broken-1000t; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,aldps-enable; + realtek,clkout-disable; + }; + }; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -218,6 +419,10 @@ &i2c3 { status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -237,6 +442,58 @@ &uart3 { status = "okay"; }; +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <®_usdhc1_vmmc>; + vqmmc-supply = <®_usdhc1_vqmmc>; + bus-width = <4>; + non-removable; + no-sd; + no-mmc; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + &usdhc3 { assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; assigned-clock-rates = <400000000>; @@ -250,6 +507,74 @@ &usdhc3 { }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Pin might be required by multiple drivers + * (e. g. HDMI Audio and HDMI TX) + */ + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) @@ -293,6 +618,12 @@ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 >; }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) @@ -310,6 +641,81 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK From c045ff8d3d915b76091cb9e37a4f463b1e2e9a98 Mon Sep 17 00:00:00 2001 From: Ranjani Vaidyanathan Date: Tue, 24 Mar 2026 13:44:07 +0800 Subject: [PATCH 117/139] arm64: dts: imx94: Update pin headers Update the pin headers to include pins that has special mux options: The MUX value field in the IOMUX table is extended to 16 bits where the lower 8 bits represent the current IOMUX value and the upper 8 bits represent the new extended mux. Signed-off-by: Ranjani Vaidyanathan Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h index 00255db89185..d5056e917140 100644 --- a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h @@ -233,6 +233,7 @@ #define IMX94_PAD_GPIO_IO17__GPT_MUX_INOUT3 0x0054 0x0358 0x0704 0x05 0x01 #define IMX94_PAD_GPIO_IO17__FLEXPWM4_PWMB0 0x0054 0x0358 0x06e4 0x06 0x00 #define IMX94_PAD_GPIO_IO17__XBAR1_XBAR_INOUT31 0x0054 0x0358 0x08b4 0x07 0x00 +#define IMX94_PAD_GPIO_IO17__XSPI1_IPP_IND_INTFA_B 0x0054 0x0358 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x035c 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO18__LPI2C4_SDA 0x0058 0x035c 0x0738 0x01 0x00 @@ -242,6 +243,7 @@ #define IMX94_PAD_GPIO_IO18__GPT_MUX_INOUT6 0x0058 0x035c 0x0710 0x05 0x01 #define IMX94_PAD_GPIO_IO18__FLEXPWM4_PWMA1 0x0058 0x035c 0x06d8 0x06 0x00 #define IMX94_PAD_GPIO_IO18__XBAR1_XBAR_INOUT32 0x0058 0x035c 0x08b8 0x07 0x00 +#define IMX94_PAD_GPIO_IO18__USB1_OTG_OC 0x0058 0x035c 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x0360 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO19__LPI2C4_SCL 0x005c 0x0360 0x0734 0x01 0x00 @@ -251,6 +253,7 @@ #define IMX94_PAD_GPIO_IO19__GPT_MUX_INOUT9 0x005c 0x0360 0x071c 0x05 0x01 #define IMX94_PAD_GPIO_IO19__FLEXPWM4_PWMB1 0x005c 0x0360 0x06e8 0x06 0x00 #define IMX94_PAD_GPIO_IO19__XBAR1_XBAR_INOUT33 0x005c 0x0360 0x08bc 0x07 0x00 +#define IMX94_PAD_GPIO_IO19__USB2_OTG_OC 0x005c 0x0360 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0364 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x0060 0x0364 0x0000 0x01 0x00 @@ -413,6 +416,7 @@ #define IMX94_PAD_GPIO_IO37__FLEXPWM3_PWMB2 0x00a4 0x03a8 0x06c0 0x05 0x00 #define IMX94_PAD_GPIO_IO37__FLEXPWM2_PWMX1 0x00a4 0x03a8 0x06a4 0x06 0x00 #define IMX94_PAD_GPIO_IO37__XBAR1_XBAR_INOUT13 0x00a4 0x03a8 0x0890 0x07 0x00 +#define IMX94_PAD_GPIO_IO37__XSPI1_IPP_IND_INTFA_B 0x00a4 0x03a8 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO38__GPIO3_IO6 0x00a8 0x03ac 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO38__NETC_1588MUX_INOUT0 0x00a8 0x03ac 0x064c 0x01 0x00 @@ -574,6 +578,7 @@ #define IMX94_PAD_GPIO_IO55__TPM4_CH3 0x00ec 0x03f0 0x083c 0x05 0x01 #define IMX94_PAD_GPIO_IO55__SINC3_EMBIT0 0x00ec 0x03f0 0x0000 0x06 0x00 #define IMX94_PAD_GPIO_IO55__XBAR1_XBAR_INOUT19 0x00ec 0x03f0 0x08a8 0x07 0x00 +#define IMX94_PAD_GPIO_IO55__XSPI1_IPP_IND_INTFA_B 0x00ec 0x03f0 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO56__GPIO3_IO24 0x00f0 0x03f4 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO56__NETC_1588MUX_INOUT6 0x00f0 0x03f4 0x0664 0x01 0x00 @@ -592,6 +597,8 @@ #define IMX94_PAD_GPIO_IO57__TPM6_CH3 0x00f4 0x03f8 0x084c 0x05 0x01 #define IMX94_PAD_GPIO_IO57__SINC3_EMBIT1 0x00f4 0x03f8 0x0000 0x06 0x00 #define IMX94_PAD_GPIO_IO57__ENET_REF_CLK_ROOT 0x00f4 0x03f8 0x0000 0x07 0x00 +#define IMX94_PAD_GPIO_IO57__XBAR1_XBAR_INOUT21 0x00f4 0x03f8 0x0000 0x0100 0x00 +#define IMX94_PAD_GPIO_IO57__SAI3_RX_SYNC 0x00f4 0x03f8 0x0000 0x0200 0x00 #define IMX94_PAD_CCM_CLKO1__CLKO_1 0x00f8 0x03fc 0x0000 0x00 0x00 #define IMX94_PAD_CCM_CLKO1__NETC_1588MUX_INOUT8 0x00f8 0x03fc 0x066c 0x01 0x00 @@ -619,6 +626,7 @@ #define IMX94_PAD_CCM_CLKO3__GPIO4_IO2 0x0100 0x0404 0x0000 0x05 0x00 #define IMX94_PAD_CCM_CLKO3__SINC3_EMCLK3 0x0100 0x0404 0x0000 0x06 0x00 #define IMX94_PAD_CCM_CLKO3__ENET_REF_CLK_ROOT 0x0100 0x0404 0x0000 0x07 0x00 +#define IMX94_PAD_CCM_CLKO3__XBAR1_XBAR_INOUT24 0x0100 0x0404 0x0000 0x0105 0x00 #define IMX94_PAD_CCM_CLKO4__CLKO_4 0x0104 0x0408 0x0000 0x00 0x00 #define IMX94_PAD_CCM_CLKO4__NETC_1588MUX_INOUT11 0x0104 0x0408 0x0000 0x01 0x00 @@ -872,6 +880,7 @@ #define IMX94_PAD_ETH4_MDIO_GPIO2__GPIO6_IO29 0x017c 0x0480 0x0000 0x05 0x00 #define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXPWM4_PWMX1 0x017c 0x0480 0x06f8 0x06 0x02 #define IMX94_PAD_ETH4_MDIO_GPIO2__SINC_FILTER_GLUE4_BREAK 0x017c 0x0480 0x0000 0x07 0x00 +#define IMX94_PAD_ETH4_MDIO_GPIO2__XSPI2_IPP_IND_INTFA_B 0x017c 0x0480 0x0000 0x0105 0x00 #define IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x0180 0x0484 0x0648 0x00 0x00 #define IMX94_PAD_ETH4_TX_CLK__USDHC3_CLK 0x0180 0x0484 0x0000 0x01 0x00 @@ -917,6 +926,7 @@ #define IMX94_PAD_ETH4_TXD2__GPIO7_IO2 0x0190 0x0494 0x0000 0x05 0x00 #define IMX94_PAD_ETH4_TXD2__FLEXPWM4_PWMA2 0x0190 0x0494 0x06dc 0x06 0x01 #define IMX94_PAD_ETH4_TXD2__ETH4_RMII_REF50_CLK 0x0190 0x0494 0x0000 0x07 0x00 +#define IMX94_PAD_ETH4_TXD2__XBAR1_XBAR_INOUT34 0x0190 0x0494 0x0000 0x0105 0x00 #define IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x0194 0x0498 0x0000 0x00 0x00 #define IMX94_PAD_ETH4_TXD3__USDHC3_DATA3 0x0194 0x0498 0x0868 0x01 0x01 @@ -965,6 +975,7 @@ #define IMX94_PAD_ETH4_RX_CTL__GPIO7_IO8 0x01a8 0x04ac 0x0000 0x05 0x00 #define IMX94_PAD_ETH4_RX_CTL__DIG_ENCODER2_DATA_OUT 0x01a8 0x04ac 0x0000 0x06 0x00 #define IMX94_PAD_ETH4_RX_CTL__XBAR1_XBAR_INOUT6 0x01a8 0x04ac 0x0874 0x07 0x01 +#define IMX94_PAD_ETH4_RX_CTL__XSPI2_IPP_IND_INTFA_B 0x01a8 0x04ac 0x0000 0x0105 0x00 #define IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x01ac 0x04b0 0x0630 0x00 0x00 #define IMX94_PAD_ETH4_RX_CLK__XSPI2_A_DQS 0x01ac 0x04b0 0x0000 0x02 0x00 @@ -1344,6 +1355,7 @@ #define IMX94_PAD_XSPI1_SS1_B__GPIO7_IO27 0x028c 0x0590 0x0000 0x05 0x00 #define IMX94_PAD_XSPI1_SS1_B__SINC1_MOD_CLK0 0x028c 0x0590 0x0000 0x06 0x00 #define IMX94_PAD_XSPI1_SS1_B__SINC_FILTER_GLUE1_BREAK 0x028c 0x0590 0x0000 0x07 0x00 +#define IMX94_PAD_XSPI1_SS1_B__XSPI1_IPP_IND_INTFA_B 0x028c 0x0590 0x0000 0x0105 0x00 #define IMX94_PAD_SD2_CD_B__USDHC2_CD_B 0x0290 0x0594 0x0000 0x00 0x00 #define IMX94_PAD_SD2_CD_B__NETC_PINMUX_ETH4_RX_CTL 0x0290 0x0594 0x0634 0x01 0x01 From c07b414ff2538daee6b055106020cb596e9820cb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 24 Mar 2026 13:44:08 +0800 Subject: [PATCH 118/139] arm64: dts: imx94: Add V2X/ELE mailbox nodes Add V2X and ELE Message Unit nodes for i.MX94. One extra V2X MU which is dedicated for V2X fast crypto engine is not included, because it requires a new compatible string. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 04c562eddc3b..5622c3f3af70 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1212,6 +1212,48 @@ a55_irqsteer: interrupt-controller@446a0000 { }; }; + mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47310000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47310000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + aips4: bus@49000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x0 0x49000000 0x0 0x800000>; From 531d1c767d7f913c58ed6b46bb313dac0719250b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 24 Mar 2026 13:44:09 +0800 Subject: [PATCH 119/139] arm64: dts: imx94: Add SCMI sensor/lmm/cpu nodes Add SCMI sensor/lmm/cpu nodes to allow Linux use thermal, i.MX System Manager Logical Machine API and CPU API Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 5622c3f3af70..3a05941da1de 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -94,14 +94,27 @@ scmi_clk: protocol@14 { #clock-cells = <1>; }; + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + scmi_iomuxc: protocol@19 { reg = <0x19>; }; + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + scmi_bbm: protocol@81 { reg = <0x81>; }; + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + scmi_misc: protocol@84 { reg = <0x84>; }; From 5b1f0603b56371899d8a6cb77a89fd44c2962b92 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Tue, 24 Mar 2026 13:44:10 +0800 Subject: [PATCH 120/139] arm64: dts: imx943: Add thermal support Add A55 and ANA thermal including cooling-maps. Signed-off-by: Joy Zou Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 1 + arch/arm64/boot/dts/freescale/imx943.dtsi | 64 +++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 3a05941da1de..c460ece6070f 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "imx94-clock.h" #include "imx94-pinfunc.h" diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi index 45b8da758e87..dfd956ece2e3 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -145,4 +145,68 @@ l3_cache: l3-cache { cache-unified; }; }; + + thermal_zones: thermal-zones { + a55-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 1>; + + trips { + cpu_alert0: trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + ana-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 0>; + + trips { + ana_alert: trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + ana_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&ana_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; From 44b580a74fcd39d0c53b8c9d6b865cfbd05a947e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 24 Mar 2026 13:44:11 +0800 Subject: [PATCH 121/139] arm64: dts: imx943-evk: Add nxp,ctrl-ids for scmi_misc Add nxp,ctrl-ids for scmi_misc to support wakeup from the peripherals. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 1d834379f602..ec728efbe15c 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -8,6 +8,12 @@ #include "imx943.dtsi" #include +#define BRD_SM_CTRL_BT_WAKE 0x8000 /*!< PCAL6416A-3 */ +#define BRD_SM_CTRL_SD3_WAKE 0x8001 /*!< PCAL6416A-4 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8002 /*!< PCAL6416A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6416A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6416A-7 */ + / { compatible = "fsl,imx943-evk", "fsl,imx94"; model = "NXP i.MX943 EVK board"; @@ -878,6 +884,14 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe }; }; +&scmi_misc { + nxp,ctrl-ids = ; +}; + &usb2 { dr_mode = "otg"; disable-over-current; From 6bc554ff0d951103d286a12d4c2d7b9105ac35e3 Mon Sep 17 00:00:00 2001 From: Florin Leotescu Date: Tue, 24 Mar 2026 13:44:12 +0800 Subject: [PATCH 122/139] arm64: dts: imx943-evk: Add fan node and enable active cooling on A55 Add pwm fan node and use it for A55 cooling. Signed-off-by: Florin Leotescu Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index ec728efbe15c..4373ca117dac 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -7,6 +7,7 @@ #include "imx943.dtsi" #include +#include #define BRD_SM_CTRL_BT_WAKE 0x8000 /*!< PCAL6416A-3 */ #define BRD_SM_CTRL_SD3_WAKE 0x8001 /*!< PCAL6416A-4 */ @@ -336,6 +337,20 @@ wm8962: codec@1a { SPKVDD2-supply = <®_audio_pwr>; }; + fan_controller: pwm@2f { + compatible = "microchip,emc2301", "microchip,emc2305"; + reg = <0x2f>; + #pwm-cells = <3>; + #address-cells = <1>; + #size-cells = <0>; + + fan0: fan@0 { + reg = <0x0>; + pwms = <&fan_controller 26000 1 PWM_POLARITY_INVERTED>; + #cooling-cells = <2>; + }; + }; + ptn5150: tcpc@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; @@ -892,6 +907,47 @@ BRD_SM_CTRL_PCIE2_WAKE 1 BRD_SM_CTRL_BUTTON 1>; }; +&thermal_zones { + a55-thermal { + trips { + atrip2: trip2 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + atrip3: trip3 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + + atrip4: trip4 { + temperature = <75000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&atrip2>; + cooling-device = <&fan0 4 6>; + }; + + map2 { + trip = <&atrip3>; + cooling-device = <&fan0 6 8>; + }; + + map3 { + trip = <&atrip4>; + cooling-device = <&fan0 8 10>; + }; + }; + }; +}; + &usb2 { dr_mode = "otg"; disable-over-current; From 9af6eed8eeb01bf501b4d82155b221b37b0141ec Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 24 Mar 2026 13:44:13 +0800 Subject: [PATCH 123/139] arm64: dts: imx943-evk: Add pf09/53 thermal zone Add PF09 and PF53 thermal nodes. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 4373ca117dac..52f7ef7dbf27 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -946,6 +946,46 @@ map3 { }; }; }; + + pf09-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + temperature = <140000>; + hysteresis = <2000>; + type = "passive"; + }; + + pf09_crit: trip1 { + temperature = <155000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + temperature = <140000>; + hysteresis = <2000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + temperature = <155000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; &usb2 { From e8341b0245736619f8d6a2cc311c9e8ad8e82390 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 17 Mar 2026 13:37:38 +0800 Subject: [PATCH 124/139] arm64: dts: imx8dxl-evk: Use audio-graph-card2 for wm8960-2 and wm8960-3 The sound card wm8960-2 and wm8960-3 only support capture mode for the reason of connection on the EVK board. But fsl-asoc-card don't support capture_only setting, the sound card creation will fail. fsl-sai 59060000.sai: Missing dma channel for stream: 0 fsl-sai 59060000.sai: ASoC error (-22): at snd_soc_pcm_component_new() on 59060000.sai fsl-sai 59070000.sai: Missing dma channel for stream: 0 fsl-sai 59070000.sai: ASoC error (-22): at snd_soc_pcm_component_new() on 59070000.sai so switch to use audio-graph-card2 which supports 'capture_only' property for wm8960-2 and wm8960-3 cards. Fixes: b41c45eb990a ("arm64: dts: imx8dxl-evk: add audio nodes") Signed-off-by: Shengjiu Wang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 114 ++++++++++++++---- 1 file changed, 90 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 5c68d33e19f2..bc62ae5ca812 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -259,33 +259,37 @@ sound-wm8960-1 { }; sound-wm8960-2 { - compatible = "fsl,imx-audio-wm8960"; - model = "wm8960-audio-2"; - audio-cpu = <&sai2>; - audio-codec = <&wm8960_2>; - audio-routing = "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT1", "Mic Jack", - "Mic Jack", "MICB"; + compatible = "audio-graph-card2"; + label = "wm8960-audio-2"; + links = <&sai2_port2>; + routing = "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + widgets = "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; }; sound-wm8960-3 { - compatible = "fsl,imx-audio-wm8960"; - model = "wm8960-audio-3"; - audio-cpu = <&sai3>; - audio-codec = <&wm8960_3>; - audio-routing = "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT1", "Mic Jack", - "Mic Jack", "MICB"; + compatible = "audio-graph-card2"; + label = "wm8960-audio-3"; + links = <&sai3_port2>; + routing = "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + widgets = "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; }; }; @@ -481,6 +485,16 @@ wm8960_2: audio-codec@1a { DCVDD-supply = <®_audio_1v8>; SPKVDD1-supply = <®_audio_5v>; SPKVDD2-supply = <®_audio_5v>; + + port { + capture-only; + + wm8960_2_ep: endpoint { + bitclock-master; + frame-master; + remote-endpoint = <&sai2_endpoint2>; + }; + }; }; }; @@ -510,6 +524,16 @@ wm8960_3: audio-codec@1a { DCVDD-supply = <®_audio_1v8>; SPKVDD1-supply = <®_audio_5v>; SPKVDD2-supply = <®_audio_5v>; + + port { + capture-only; + + wm8960_3_ep: endpoint { + bitclock-master; + frame-master; + remote-endpoint = <&sai3_endpoint2>; + }; + }; }; }; @@ -700,6 +724,27 @@ &sai2 { pinctrl-0 = <&pinctrl_sai2>; fsl,sai-asynchronous; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sai2_port1: port@1 { + reg = <1>; + endpoint { /* not used */ }; + }; + + sai2_port2: port@2 { + reg = <2>; + capture-only; + + sai2_endpoint2: endpoint { + dai-format = "i2s"; + remote-endpoint = <&wm8960_2_ep>; + system-clock-direction-out; + }; + }; + }; }; &sai3 { @@ -712,6 +757,27 @@ &sai3 { pinctrl-0 = <&pinctrl_sai3>; fsl,sai-asynchronous; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sai3_port1: port@1 { + reg = <1>; + endpoint { /* not used */ }; + }; + + sai3_port2: port@2 { + reg = <2>; + capture-only; + + sai3_endpoint2: endpoint { + dai-format = "i2s"; + remote-endpoint = <&wm8960_3_ep>; + system-clock-direction-out; + }; + }; + }; }; &thermal_zones { From bfb91be0eba426913f2950ed8b3d963f0de53fcc Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Tue, 24 Mar 2026 13:52:03 +0800 Subject: [PATCH 125/139] arm64: dts: imx8mp-evk: Specify ADV7535 register addresses MIPI DSI to HDMI bridge ADV7535 CEC default register address is 0x3c on an I2C bus. And, OV5640 camera uses the same address on the same I2C bus. To resolve this conflict, use 0x3b as ADV7535 CEC register address by specifying all ADV7535 register addresses. Fixes: 6f6c18cba16f ("arm64: dts: imx8mp-evk: add camera ov5640 and related nodes") Signed-off-by: Liu Ying Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index aedc09937716..d0a2bd975a18 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -602,7 +602,8 @@ ov5640_mipi_0_ep: endpoint { hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>; + reg = <0x3d>, <0x3f>, <0x3b>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; From f15bfdc18a010a8f5433ef43f1c942793f8f4671 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 24 Mar 2026 08:58:41 +0100 Subject: [PATCH 126/139] arm64: dts: imx8mp-tqma8mpql: Add DT overlays to explicit list Armbian installs DT overlays using dtbs_install. For it to work all the overlays have to be added to dtb-y explicitly. Add the overlays for platforms supported by Armbian. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c7ccf529ee1a..711e36cc2c99 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -370,8 +370,11 @@ imx8mp-tqma8mpql-mba8mp-ras314-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb From 4074753df3952c2af5373b46337ad93ccb86ef73 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Thu, 12 Mar 2026 15:16:09 +0800 Subject: [PATCH 127/139] arm64: dts: freescale: imx8mp-moduline-display-106: add typec-power-opmode property Add typec-power-opmode property to avoid dtbs_check warning. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- .../imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso index e3965caca6be..c6fc5d5b1e5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso @@ -77,6 +77,7 @@ connector { compatible = "usb-c-connector"; data-role = "host"; pd-disable; + typec-power-opmode = "default"; vbus-supply = <®_vbus>; port { From 70008aee892bbb5c2969bbe9e5778fc081b14bd2 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:40:55 +0100 Subject: [PATCH 128/139] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") introduced pinmux nodes for lx2160 i2c interfaces, allowing runtime change between i2c and gpio functions implementing bus recovery. However, the dynamic configuration area (overwrite MUX) used by the pinctrl-single driver initially reads as zero and does not reflect the actual hardware state set by the Reset Configuration Word (RCW) at power-on. Because multiple groups of pins are configured from a single 32-bit register, the first write from the pinctrl driver unintentionally clears all other bits to zero. For example, on the LX2162A Clearfog, RCWSR12 is initialized to 0x08000006. When any i2c pinmux is applied, it clears all other fields. This inadvertently disables SD card-detect (IIC2_PMUX) and some GPIOs (SDHC1_DIR_PMUX): LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110 IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI Reverting the commit in question was considered but bus recovery is an important feature. Instead add pinmux nodes for those pins that were unintentionally reconfigured on SolidRun LX2160A Clearfog-CX and LX2162A Clearfog boards. Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") Cc: stable@vger.kernel.org Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 7 ++++++ .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 +++++++++++++++++++ .../dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++ .../dts/freescale/fsl-lx2162a-sr-som.dtsi | 7 ++++++ 5 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index eec2cd6c6d32..7f6e39e27ce5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -162,6 +162,8 @@ rtc@51 { }; &fspi { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>; status = "okay"; flash@0 { @@ -177,6 +179,11 @@ flash@0 { }; }; +&pinmux_i2crv { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_14_12_pins>; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index af6258b2fe82..580ee9b3026e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -89,6 +89,8 @@ &emdio2 { }; &esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>; sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 853b01452813..af74e77efabc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1721,6 +1721,10 @@ i2c1_scl_gpio: i2c1-scl-gpio-pins { pinctrl-single,bits = <0x0 0x1 0x7>; }; + esdhc0_cd_wp_pins: iic2-sdhc-pins { + pinctrl-single,bits = <0x0 0x6 0x7>; + }; + i2c2_scl: i2c2-scl-pins { pinctrl-single,bits = <0x0 0 (0x7 << 3)>; }; @@ -1753,6 +1757,26 @@ i2c5_scl_gpio: i2c5-scl-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; }; + fspi_data74_pins: xspi1-data74-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>; + }; + + fspi_data30_pins: xspi1-data30-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>; + }; + + fspi_dqs_sck_cs10_pins: xspi1-base-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>; + }; + + esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>; + }; + + gpio0_14_12_pins: sdhc1-dir-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>; + }; + i2c6_scl: i2c6-scl-pins { pinctrl-single,bits = <0x4 0x2 0x7>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index eafef8718a0f..8920326a0673 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -223,6 +223,8 @@ ethernet_phy8: ethernet-phy@15 { }; &esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>; sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi index e914291e63a1..e1344942eaae 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -30,6 +30,8 @@ &esdhc1 { }; &fspi { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>; status = "okay"; flash@0 { @@ -80,3 +82,8 @@ rtc@6f { reg = <0x6f>; }; }; + +&pinmux_i2crv { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_14_12_pins>; +}; From 7a3cc49ad1fc8d063abb7f5de8f1b981b99d2978 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:40:56 +0100 Subject: [PATCH 129/139] arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit LX2160A pinmux is done in groups by various length bitfields within configuration registers. The first i2c bus (called IIC1 in reference manual) is configured through field IIC1_PMUX in register RCWSR14 bit 10 which is described in the reference manual as a single bit, unlike the other i2c buses. Change the bitmask for the pinmux nodes from 0x7 to 0x1 to ensure only single bit is modified. Further change the zero in the same line to hexadecimal format for consistency. Align with documentation by avoiding writes to reserved bits. No functional change, as writing the extra two reserved bits is not known to cause issues. Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index af74e77efabc..d5bb55df0321 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1794,11 +1794,11 @@ i2c7_scl_gpio: i2c7-scl-gpio-pins { }; i2c0_scl: i2c0-scl-pins { - pinctrl-single,bits = <0x8 0 (0x7 << 10)>; + pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>; }; i2c0_scl_gpio: i2c0-scl-gpio-pins { - pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>; + pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>; }; }; From 325ca511ca3dda936207ce737e0afe837d45a674 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:40:57 +0100 Subject: [PATCH 130/139] arm64: dts: lx2160a: remove duplicate pinmux nodes LX2160A pinmux is done in groups by various length bitfields within configuration registers. The pinmux nodes i2c7-scl-pins and i2c7-scl-gpio-pins are duplicates of i2c6-scl-gpio and i2c6-scl-gpio-pins, writing to the same register and bits. These two i2c buses i2c6/i2c7 (IIC7/IIC8) are configured together in register RCWSR13 bits 3-0. Drop the duplicate node name and change references to the i2c6 node. Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index d5bb55df0321..41c9b4253f4a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -862,8 +862,8 @@ i2c7: i2c@2070000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c7_scl>; - pinctrl-1 = <&i2c7_scl_gpio>; + pinctrl-0 = <&i2c6_scl>; + pinctrl-1 = <&i2c6_scl_gpio>; scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -1785,14 +1785,6 @@ i2c6_scl_gpio: i2c6-scl-gpio-pins { pinctrl-single,bits = <0x4 0x1 0x7>; }; - i2c7_scl: i2c7-scl-pins { - pinctrl-single,bits = <0x4 0x2 0x7>; - }; - - i2c7_scl_gpio: i2c7-scl-gpio-pins { - pinctrl-single,bits = <0x4 0x1 0x7>; - }; - i2c0_scl: i2c0-scl-pins { pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>; }; From 456eb494746afd56d3a9dc30271300136e55b96e Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:40:58 +0100 Subject: [PATCH 131/139] arm64: dts: lx2160a: rename pinmux nodes for readability LX2160A pinmux is done in groups by various length bitfields within configuration registers. Each group of pins is named in the reference manual after a primary function using soc-specific naming, e.g. IIC1 (for i2c0). Hardware block numbering starts from zero in device-tree but one in the reference manual. Rename the already defined pinmux nodes originally added for changing i2c pins between i2c and gpio functions reflecting the reference manual name (IIC) in the node name, and the device-tree name (i2c, gpio) in the label. Specifically, drop the "_scl" suffix from the I2C labels because the nodes actually configure both SDA and SCL pins together. Instead add "_pins" suffix to avoid conflicts with I2C controller labels. For GPIO functions, include the specific controller and pin numbers in the label to clarify they are generic GPIOs and help spot mistakes. No functional change intended. Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 66 +++++++++---------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 41c9b4253f4a..28500e887390 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -750,8 +750,8 @@ i2c0: i2c@2000000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c0_scl>; - pinctrl-1 = <&i2c0_scl_gpio>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&gpio0_3_2_pins>; scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -766,8 +766,8 @@ i2c1: i2c@2010000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c1_scl>; - pinctrl-1 = <&i2c1_scl_gpio>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&gpio0_31_30_pins>; scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -782,8 +782,8 @@ i2c2: i2c@2020000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c2_scl>; - pinctrl-1 = <&i2c2_scl_gpio>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&gpio0_29_28_pins>; scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -798,8 +798,8 @@ i2c3: i2c@2030000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c3_scl>; - pinctrl-1 = <&i2c3_scl_gpio>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&gpio0_27_26_pins>; scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -814,8 +814,8 @@ i2c4: i2c@2040000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c4_scl>; - pinctrl-1 = <&i2c4_scl_gpio>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&gpio0_25_24_pins>; scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -830,8 +830,8 @@ i2c5: i2c@2050000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c5_scl>; - pinctrl-1 = <&i2c5_scl_gpio>; + pinctrl-0 = <&i2c5_pins>; + pinctrl-1 = <&gpio0_23_22_pins>; scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -846,8 +846,8 @@ i2c6: i2c@2060000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c6_scl>; - pinctrl-1 = <&i2c6_scl_gpio>; + pinctrl-0 = <&i2c6_i2c7_pins>; + pinctrl-1 = <&gpio1_18_15_pins>; scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -862,8 +862,8 @@ i2c7: i2c@2070000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c6_scl>; - pinctrl-1 = <&i2c6_scl_gpio>; + pinctrl-0 = <&i2c6_i2c7_pins>; + pinctrl-1 = <&gpio1_18_15_pins>; scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -1713,11 +1713,11 @@ pinmux_i2crv: pinmux@70010012c { pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; - i2c1_scl: i2c1-scl-pins { + i2c1_pins: iic2-i2c-pins { pinctrl-single,bits = <0x0 0 0x7>; }; - i2c1_scl_gpio: i2c1-scl-gpio-pins { + gpio0_31_30_pins: iic2-gpio-pins { pinctrl-single,bits = <0x0 0x1 0x7>; }; @@ -1725,35 +1725,35 @@ esdhc0_cd_wp_pins: iic2-sdhc-pins { pinctrl-single,bits = <0x0 0x6 0x7>; }; - i2c2_scl: i2c2-scl-pins { + i2c2_pins: iic3-i2c-pins { pinctrl-single,bits = <0x0 0 (0x7 << 3)>; }; - i2c2_scl_gpio: i2c2-scl-gpio-pins { + gpio0_29_28_pins: iic3-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; }; - i2c3_scl: i2c3-scl-pins { + i2c3_pins: iic4-i2c-pins { pinctrl-single,bits = <0x0 0 (0x7 << 6)>; }; - i2c3_scl_gpio: i2c3-scl-gpio-pins { + gpio0_27_26_pins: iic4-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; }; - i2c4_scl: i2c4-scl-pins { + i2c4_pins: iic5-i2c-pins { pinctrl-single,bits = <0x0 0 (0x7 << 9)>; }; - i2c4_scl_gpio: i2c4-scl-gpio-pins { + gpio0_25_24_pins: iic5-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; }; - i2c5_scl: i2c5-scl-pins { + i2c5_pins: iic6-i2c-pins { pinctrl-single,bits = <0x0 0 (0x7 << 12)>; }; - i2c5_scl_gpio: i2c5-scl-gpio-pins { + gpio0_23_22_pins: iic6-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; }; @@ -1777,19 +1777,19 @@ gpio0_14_12_pins: sdhc1-dir-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>; }; - i2c6_scl: i2c6-scl-pins { - pinctrl-single,bits = <0x4 0x2 0x7>; - }; - - i2c6_scl_gpio: i2c6-scl-gpio-pins { + gpio1_18_15_pins: iic8-iic7-gpio-pins { pinctrl-single,bits = <0x4 0x1 0x7>; }; - i2c0_scl: i2c0-scl-pins { + i2c6_i2c7_pins: iic8-iic7-i2c-pins { + pinctrl-single,bits = <0x4 0x2 0x7>; + }; + + i2c0_pins: iic1-i2c-pins { pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>; }; - i2c0_scl_gpio: i2c0-scl-gpio-pins { + gpio0_3_2_pins: iic1-gpio-pins { pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>; }; }; From 89ea0dbd701f89805499d26bd90657468c789545 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:40:59 +0100 Subject: [PATCH 132/139] arm64: dts: lx2160a: add sda gpio references for i2c bus recovery LX2160A pinmux is done in groups by various length bitfields within configuration registers. In particular i2c sda/scl pins are always configured together. Therefore bus recovery may control both sda and scl. When pinmux nodes and bus recovery was enabled originally for LX2160, only the scl-gpios were added to the i2c controller nodes. Add references to sda-gpios for each i2c controller. Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 28500e887390..53b9c5f1f193 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -753,6 +753,7 @@ i2c0: i2c@2000000 { pinctrl-0 = <&i2c0_pins>; pinctrl-1 = <&gpio0_3_2_pins>; scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -769,6 +770,7 @@ i2c1: i2c@2010000 { pinctrl-0 = <&i2c1_pins>; pinctrl-1 = <&gpio0_31_30_pins>; scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -785,6 +787,7 @@ i2c2: i2c@2020000 { pinctrl-0 = <&i2c2_pins>; pinctrl-1 = <&gpio0_29_28_pins>; scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -801,6 +804,7 @@ i2c3: i2c@2030000 { pinctrl-0 = <&i2c3_pins>; pinctrl-1 = <&gpio0_27_26_pins>; scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -817,6 +821,7 @@ i2c4: i2c@2040000 { pinctrl-0 = <&i2c4_pins>; pinctrl-1 = <&gpio0_25_24_pins>; scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -833,6 +838,7 @@ i2c5: i2c@2050000 { pinctrl-0 = <&i2c5_pins>; pinctrl-1 = <&gpio0_23_22_pins>; scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -849,6 +855,7 @@ i2c6: i2c@2060000 { pinctrl-0 = <&i2c6_i2c7_pins>; pinctrl-1 = <&gpio1_18_15_pins>; scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -865,6 +872,7 @@ i2c7: i2c@2070000 { pinctrl-0 = <&i2c6_i2c7_pins>; pinctrl-1 = <&gpio1_18_15_pins>; scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; From 03241620d2b9915c9e3463dbc56e9eb95ad43c08 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:41:00 +0100 Subject: [PATCH 133/139] arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes Replace some stray zeros from decimal to hexadecimal format within pinmux nodes. No functional change intended. Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 53b9c5f1f193..d266bf96e2c6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1722,7 +1722,7 @@ pinmux_i2crv: pinmux@70010012c { pinctrl-single,function-mask = <0x7>; i2c1_pins: iic2-i2c-pins { - pinctrl-single,bits = <0x0 0 0x7>; + pinctrl-single,bits = <0x0 0x0 0x7>; }; gpio0_31_30_pins: iic2-gpio-pins { @@ -1734,7 +1734,7 @@ esdhc0_cd_wp_pins: iic2-sdhc-pins { }; i2c2_pins: iic3-i2c-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 3)>; + pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>; }; gpio0_29_28_pins: iic3-gpio-pins { @@ -1742,7 +1742,7 @@ gpio0_29_28_pins: iic3-gpio-pins { }; i2c3_pins: iic4-i2c-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 6)>; + pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>; }; gpio0_27_26_pins: iic4-gpio-pins { @@ -1750,7 +1750,7 @@ gpio0_27_26_pins: iic4-gpio-pins { }; i2c4_pins: iic5-i2c-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 9)>; + pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>; }; gpio0_25_24_pins: iic5-gpio-pins { @@ -1758,7 +1758,7 @@ gpio0_25_24_pins: iic5-gpio-pins { }; i2c5_pins: iic6-i2c-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 12)>; + pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>; }; gpio0_23_22_pins: iic6-gpio-pins { From 284ad7064aaa1badde022785cd925af29c696b21 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:41:01 +0100 Subject: [PATCH 134/139] arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") introduced pinmux nodes for lx2160 i2c interfaces, allowing runtime change between i2c and gpio functions implementing bus recovery. However, the dynamic configuration area (overwrite MUX) used by the pinctrl-single driver initially reads as zero and does not reflect the actual hardware state set by the Reset Configuration Word (RCW) at power-on. Because multiple groups of pins are configured from a single 32-bit register, the first write from the pinctrl driver unintentionally clears all other bits to zero. Add description for all bits of RCWSR12 register, allowing boards to explicitly define and restore their intended hardware state. This includes i2c, gpio, flextimer, spi, can and sdhc functions. Other configuration words, i.e. RCWSR13 & RCWSR14 may be added in the future for boards setting non-zero values there. Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery") Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index d266bf96e2c6..479982948ee5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1721,6 +1721,7 @@ pinmux_i2crv: pinmux@70010012c { pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; + /* RCWSR12 */ i2c1_pins: iic2-i2c-pins { pinctrl-single,bits = <0x0 0x0 0x7>; }; @@ -1729,6 +1730,10 @@ gpio0_31_30_pins: iic2-gpio-pins { pinctrl-single,bits = <0x0 0x1 0x7>; }; + ftm0_ch10_pins: iic2-ftm-pins { + pinctrl-single,bits = <0x0 0x2 0x7>; + }; + esdhc0_cd_wp_pins: iic2-sdhc-pins { pinctrl-single,bits = <0x0 0x6 0x7>; }; @@ -1741,6 +1746,14 @@ gpio0_29_28_pins: iic3-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; }; + can0_pins: iic3-can-pins { + pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>; + }; + + event65_pins: iic3-event-pins { + pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>; + }; + i2c3_pins: iic4-i2c-pins { pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>; }; @@ -1749,6 +1762,14 @@ gpio0_27_26_pins: iic4-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; }; + can1_pins: iic4-can-pins { + pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>; + }; + + event87_pins: iic4-event-pins { + pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>; + }; + i2c4_pins: iic5-i2c-pins { pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>; }; @@ -1757,6 +1778,14 @@ gpio0_25_24_pins: iic5-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; }; + esdhc0_clksync_pins: iic5-sdhc-clk-pins { + pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>; + }; + + dspi2_miso_mosi_pins: iic5-spi3-pins { + pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>; + }; + i2c5_pins: iic6-i2c-pins { pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>; }; @@ -1765,26 +1794,71 @@ gpio0_23_22_pins: iic6-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; }; + esdhc1_clksync_pins: iic6-sdhc-clk-pins { + pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>; + }; + fspi_data74_pins: xspi1-data74-pins { pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>; }; + gpio1_31_28_pins: xspi1-data74-gpio-pins { + pinctrl-single,bits = <0x0 0x1 (0x7 << 15)>; + }; + fspi_data30_pins: xspi1-data30-pins { pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>; }; + gpio1_27_24_pins: xspi1-data30-gpio-pins { + pinctrl-single,bits = <0x0 0x1 (0x7 << 18)>; + }; + fspi_dqs_sck_cs10_pins: xspi1-base-pins { pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>; }; + gpio1_23_20_pins: xspi1-base-gpio-pins { + pinctrl-single,bits = <0x0 0x1 (0x7 << 21)>; + }; + esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins { pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>; }; + gpio0_21_15_pins: sdhc1-base-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>; + }; + + dspi0_pins: sdhc1-base-spi1-pins { + pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>; + }; + + esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins { + pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>; + }; + + esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins { + pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>; + }; + + esdhc0_dir_pins: sdhc1-dir-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>; + }; + gpio0_14_12_pins: sdhc1-dir-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>; }; + dspi2_cs31_pins: sdhc1-dir-spi3-pins { + pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>; + }; + + esdhc0_data75_pins: sdhc1-dir-sdhc-pins { + pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>; + }; + + /* RCWSR13 */ gpio1_18_15_pins: iic8-iic7-gpio-pins { pinctrl-single,bits = <0x4 0x1 0x7>; }; @@ -1793,6 +1867,7 @@ i2c6_i2c7_pins: iic8-iic7-i2c-pins { pinctrl-single,bits = <0x4 0x2 0x7>; }; + /* RCWSR14 */ i2c0_pins: iic1-i2c-pins { pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>; }; From e2f31bffa1f5fa1f6628abc59020a0c30b0a3ce9 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:41:02 +0100 Subject: [PATCH 135/139] arm64: dts: lx2160a-cex7: add rtc alias Add alias for rtc0 ensuring that on-COM RTC is assigned first index. Note that fsl-lx2160a.dtsi already defines an alias for rtc1 which implicitly achieved the same result. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index 7f6e39e27ce5..90956ffb8ea9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -14,6 +14,7 @@ / { aliases { crypto = &crypto; + rtc0 = &com_rtc; }; sb_3v3: regulator-sb3v3 { @@ -154,7 +155,7 @@ &i2c2 { &i2c4 { status = "okay"; - rtc@51 { + com_rtc: rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>; From fcf67ca2b23cda0ea4711f6b87ffb9c9c5e54a5e Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:41:03 +0100 Subject: [PATCH 136/139] arm64: dts: lx2162a-sr-som: add crypto & rtc aliases, model Add aliases for crypto accelerator and rtc0 ensuring that on-SoM RTC and the SoC A72 domain crypto accelerator are assigned first index. Further set model and compatible strings which are informative but overridden by actual boards. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi index e1344942eaae..3ad908d52a18 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -5,6 +5,16 @@ // Copyright 2021 Rabeeh Khoury // Copyright 2023 Josua Mayer +/ { + model = "SolidRun LX2162A System on Module"; + compatible = "solidrun,lx2162a-som", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + rtc0 = &som_rtc; + }; +}; + &crypto { status = "okay"; }; @@ -77,7 +87,7 @@ variable_eeprom: eeprom@54 { &i2c5 { status = "okay"; - rtc@6f { + som_rtc: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; From a43212e427b540b39e22511a0a993e7d3e578d56 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 24 Mar 2026 13:41:04 +0100 Subject: [PATCH 137/139] arm64: dts: lx2162a-clearfog: set sfp connector leds function and source LX2162A Clearfog has four LEDs attached physically to the 4-port SFP connector. They are intended to show information relating to network interface status. Select "netdev" as default trigger for each LED, and link each one to the respective dpmac instance as trigger-source. Signed-off-by: Josua Mayer Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index 8920326a0673..9d50d3e2761d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -41,21 +41,29 @@ leds { led_sfp_at: led-sfp-at { gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac3>; }; led_sfp_ab: led-sfp-ab { gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac4>; }; led_sfp_bt: led-sfp-bt { gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac5>; }; led_sfp_bb: led-sfp-bb { gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac6>; }; }; From e3d3d19d1c0050789a4813ce836a641a3387d916 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 24 Mar 2026 19:04:58 +0800 Subject: [PATCH 138/139] arm64: dts: imx8qm-mek: switch Type-C connector power-role to dual When attach to PC Type-A port, the USB device controller does not function at all. Because it is configured as source-only and a Type-A port doesn't support PD capability, a data role swap is impossible. Actually, PTN5110THQ is configured for Source role only at POR, but after POR it can operate as a DRP (Dual-Role Power). By switching the power-role to dual, the port can operate as a sink and enter device mode when attach to Type-A port. Since the board design uses EN_SRC to control the 5V VBUS path and EN_SNK to control the 12V VBUS output, to avoid outputting a higher VBUS when in sink role, we set the operation current limit to 0mA so that SW will not control EN_SNK at all. Fixes: b237975b2cd58 ("arm64: dts: imx8qm-mek: add usb 3.0 and related type C nodes") Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index dadc136aec6e..011a89d85961 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -611,9 +611,17 @@ ptn5110: tcpc@51 { usb_con1: connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "source"; + power-role = "dual"; data-role = "dual"; + try-power-role = "sink"; source-pdos = ; + /* + * Set operational current to 0mA as we don't want EN_SNK + * enable 12V VBUS switch when it work as a sink. + */ + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; ports { #address-cells = <1>; From 825b8c7e1d2918d89eb378b761530d1e51dba82e Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 24 Mar 2026 19:04:59 +0800 Subject: [PATCH 139/139] arm64: dts: imx8qxp-mek: switch Type-C connector power-role to dual When attach to PC Type-A port, the USB device controller does not function at all. Because it is configured as source-only and a Type-A port doesn't support PD capability, a data role swap is impossible. Actually, PTN5110THQ is configured for Source role only at POR, but after POR it can operate as a DRP (Dual-Role Power). By switching the power-role to dual, the port can operate as a sink and enter device mode when attach to Type-A port. Since the board design uses EN_SRC to control the 5V VBUS path and EN_SNK to control the 12V VBUS output, to avoid outputting a higher VBUS when in sink role, we set the operation current limit to 0mA so that SW will not control EN_SNK at all. Fixes: 2faf4ebcee2e5 ("arm64: dts: freescale: imx8qxp-mek: enable cadence usb3") Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 40a0bc9f4e84..623169f7ddb5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -566,9 +566,17 @@ ptn5110: tcpc@50 { usb_con1: connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "source"; + power-role = "dual"; data-role = "dual"; + try-power-role = "sink"; source-pdos = ; + /* + * Set operational current to 0mA as we don't want EN_SNK + * enable 12V VBUS switch when it work as a sink. + */ + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; ports { #address-cells = <1>;