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Samsung DTS ARM64 changes for v6.18

Browse Source 
1. Exynos850 e850 board: Enable Ethernet.
 
 2. Exynos990: Enable watchdog and USB, add more clock controllers.
 
 3. Exynos2200: Switch to 32-bit address space for blocks, because all
    peripherals fit there.  Add remaining serial engine (USI) nodes
    (serial, I2C).
 
 4. New Artpec ARTPEC-8 SoC with board. That's a design from Samsung,
    sharing all basic blocks with other Samsung SoCs (busses, clock
    controllers, pin controllers, PCIe, USB) and having media/video
    related blocks from Axis.
 
    Only basic support is added here: few clock controllers, pin
    controller and UART.
 
 5. Several cleanups.
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Merge tag 'samsung-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt

Samsung DTS ARM64 changes for v6.18

1. Exynos850 e850 board: Enable Ethernet.

2. Exynos990: Enable watchdog and USB, add more clock controllers.

3. Exynos2200: Switch to 32-bit address space for blocks, because all
   peripherals fit there.  Add remaining serial engine (USI) nodes
   (serial, I2C).

4. New Artpec ARTPEC-8 SoC with board. That's a design from Samsung,
   sharing all basic blocks with other Samsung SoCs (busses, clock
   controllers, pin controllers, PCIe, USB) and having media/video
   related blocks from Axis.

   Only basic support is added here: few clock controllers, pin
   controller and UART.

5. Several cleanups.

* tag 'samsung-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllers
  arm64: dts: axis: Add ARTPEC-8 Grizzly dts support
  arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
  dt-bindings: arm: axis: Add ARTPEC-8 grizzly board
  arm64: dts: exynos8895: Minor whitespace cleanup
  dt-bindings: arm: Convert Axis board/soc bindings to json-schema
  arm64: dts: exynos2200: Add default GIC address cells
  arm64: dts: fsd: Add default GIC address cells
  arm64: dts: google: gs101: Add default GIC address cells
  arm64: dts: exynos5433: Add default GIC address cells
  arm64: dts: exynos2200: define all usi nodes
  arm64: dts: exynos2200: increase the size of all syscons
  arm64: dts: exynos2200: use 32-bit address space for /soc
  arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label
  arm64: dts: exynos990-r8s: Enable USB
  arm64: dts: exynos990-c1s: Enable USB
  arm64: dts: exynos990-x1s-common: Enable USB
  arm64: dts: exynos990: Add USB nodes
  arm64: dts: exynos990: Enable watchdog timer
  arm64: dts: exynos: Add Ethernet node for E850-96 board

Link: https://lore.kernel.org/r/20250909180127.99783-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-15 15:04:43 +02:00
commit 54a5a6041b
21 changed files with 2038 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
Documentation/devicetree/bindings/arm/axis.txt
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@ -1,13 +0,0 @@
Axis Communications AB
ARTPEC series SoC Device Tree Bindings
ARTPEC-6 ARM SoC
================
Required root node properties:
- compatible = "axis,artpec6";
ARTPEC-6 Development board:
---------------------------
Required root node properties:
- compatible = "axis,artpec6-dev-board", "axis,artpec6";

36
Documentation/devicetree/bindings/arm/axis.yaml Normal file
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@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/axis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axis ARTPEC platforms
maintainers:
- Jesper Nilsson <jesper.nilsson@axis.com>
- Lars Persson <lars.persson@axis.com>
- linux-arm-kernel@axis.com
description: |
ARM platforms using SoCs designed by Axis branded as "ARTPEC".
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Axis ARTPEC-6 SoC board
items:
- enum:
- axis,artpec6-dev-board
- const: axis,artpec6
- description: Axis ARTPEC-8 SoC board
items:
- enum:
- axis,artpec8-grizzly
- const: axis,artpec8
additionalProperties: true
...

12
MAINTAINERS
View File

@ -4102,6 +4102,18 @@ S: Maintained
F: Documentation/devicetree/bindings/sound/axentia,*
F: sound/soc/atmel/tse850-pcm5142.c
AXIS ARTPEC ARM64 SoC SUPPORT
M: Jesper Nilsson <jesper.nilsson@axis.com>
M: Lars Persson <lars.persson@axis.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org
L: linux-arm-kernel@axis.com
S: Maintained
F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
F: arch/arm64/boot/dts/exynos/axis/
F: drivers/clk/samsung/clk-artpec*.c
F: include/dt-bindings/clock/axis,artpec*-clk.h
AXI-FAN-CONTROL HARDWARE MONITOR DRIVER
M: Nuno Sá <nuno.sa@analog.com>
L: linux-hwmon@vger.kernel.org

7
arch/arm64/Kconfig.platforms
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@ -40,6 +40,13 @@ config ARCH_APPLE
This enables support for Apple's in-house ARM SoC family, such
as the Apple M1.
config ARCH_ARTPEC
bool "Axis Communications ARTPEC SoC Family"
depends on ARCH_EXYNOS
select ARM_GIC
help
This enables support for the ARMv8 based ARTPEC SoC Family.
config ARCH_AXIADO
bool "Axiado SoC Family"
select GPIOLIB

1
arch/arm64/boot/dts/exynos/Makefile
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@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += axis
subdir-y += google
dtb-$(CONFIG_ARCH_EXYNOS) += \

4
arch/arm64/boot/dts/exynos/axis/Makefile Normal file
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@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ARTPEC) += \
artpec8-grizzly.dtb

36
arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h Normal file
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@ -0,0 +1,36 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Axis ARTPEC-8 SoC device tree pinctrl constants
*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*/
#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
#define ARTPEC_PIN_PULL_NONE 0
#define ARTPEC_PIN_PULL_DOWN 1
#define ARTPEC_PIN_PULL_UP 3
#define ARTPEC_PIN_FUNC_INPUT 0
#define ARTPEC_PIN_FUNC_OUTPUT 1
#define ARTPEC_PIN_FUNC_2 2
#define ARTPEC_PIN_FUNC_3 3
#define ARTPEC_PIN_FUNC_4 4
#define ARTPEC_PIN_FUNC_5 5
#define ARTPEC_PIN_FUNC_6 6
#define ARTPEC_PIN_FUNC_EINT 0xf
#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT
/* Drive strength for ARTPEC */
#define ARTPEC_PIN_DRV_SR1 0x8
#define ARTPEC_PIN_DRV_SR2 0x9
#define ARTPEC_PIN_DRV_SR3 0xa
#define ARTPEC_PIN_DRV_SR4 0xb
#define ARTPEC_PIN_DRV_SR5 0xc
#define ARTPEC_PIN_DRV_SR6 0xd
#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */

35
arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts Normal file
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@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Axis ARTPEC-8 Grizzly board device tree source
*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*/
/dts-v1/;
#include "artpec8.dtsi"
#include "artpec8-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "ARTPEC-8 grizzly board";
compatible = "axis,artpec8-grizzly", "axis,artpec8";
aliases {
serial0 = &serial_0;
};
chosen {
stdout-path = &serial_0;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
};
&osc_clk {
clock-frequency = <50000000>;
};

120
arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi Normal file
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@ -0,0 +1,120 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Axis ARTPEC-8 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*/
#include "artpec-pinctrl.h"
&pinctrl_fsys {
gpe0: gpe0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe1: gpe1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe2: gpe2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf2: gpf2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf3: gpf3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf4: gpf4-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gps0: gps0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gps1: gps1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
serial0_bus: serial0-bus-pins {
samsung,pins = "gpf4-4", "gpf4-5";
samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
};
};
&pinctrl_peric {
gpa0: gpa0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa2: gpa2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk0: gpk0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

244
arch/arm64/boot/dts/exynos/axis/artpec8.dtsi Normal file
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@ -0,0 +1,244 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Axis ARTPEC-8 SoC device tree source
*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axis,artpec8-clk.h>
/ {
compatible = "axis,artpec8";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
pinctrl0 = &pinctrl_fsys;
pinctrl1 = &pinctrl_peric;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>;
clock-names = "cpu";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
idle-states {
entry-method = "psci";
cpu_sleep: cpu-sleep {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
};
};
fin_pll: clock-finpll {
compatible = "fixed-factor-clock";
clocks = <&osc_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "fin_pll";
};
osc_clk: clock-osc {
/* XXTI */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "osc_clk";
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
soc: soc@0 {
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x17000000>;
#address-cells = <1>;
#size-cells = <1>;
cmu_imem: clock-controller@10010000 {
compatible = "axis,artpec8-cmu-imem";
reg = <0x10010000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>,
<&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>;
clock-names = "fin_pll", "aclk", "jpeg";
};
timer@10040000 {
compatible = "axis,artpec8-mct", "samsung,exynos4210-mct";
reg = <0x10040000 0x1000>;
clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>;
clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@10201000 {
compatible = "arm,gic-400";
reg = <0x10201000 0x1000>,
<0x10202000 0x2000>,
<0x10204000 0x2000>,
<0x10206000 0x2000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
cmu_cpucl: clock-controller@11410000 {
compatible = "axis,artpec8-cmu-cpucl";
reg = <0x11410000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>;
clock-names = "fin_pll", "switch";
};
cmu_cmu: clock-controller@12400000 {
compatible = "axis,artpec8-cmu-cmu";
reg = <0x12400000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
};
cmu_core: clock-controller@12410000 {
compatible = "axis,artpec8-cmu-core";
reg = <0x12410000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>,
<&cmu_cmu CLK_DOUT_CMU_CORE_DLP>;
clock-names = "fin_pll", "main", "dlp";
};
cmu_bus: clock-controller@12c10000 {
compatible = "axis,artpec8-cmu-bus";
reg = <0x12c10000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_BUS>,
<&cmu_cmu CLK_DOUT_CMU_BUS_DLP>;
clock-names = "fin_pll", "bus", "dlp";
};
cmu_peri: clock-controller@16410000 {
compatible = "axis,artpec8-cmu-peri";
reg = <0x16410000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_PERI_IP>,
<&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>,
<&cmu_cmu CLK_DOUT_CMU_PERI_DISP>;
clock-names = "fin_pll", "ip", "audio", "disp";
};
pinctrl_peric: pinctrl@165f0000 {
compatible = "axis,artpec8-pinctrl";
reg = <0x165f0000 0x1000>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
};
cmu_fsys: clock-controller@16c10000 {
compatible = "axis,artpec8-cmu-fsys";
reg = <0x16c10000 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
<&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
};
pinctrl_fsys: pinctrl@16c30000 {
compatible = "axis,artpec8-pinctrl";
reg = <0x16c30000 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
};
serial_0: serial@16cc0000 {
compatible = "axis,artpec8-uart";
reg = <0x16cc0000 0x100>;
clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>,
<&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>;
clock-names = "uart", "clk_uart_baud0";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&serial0_bus>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

2
arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi
View File

@ -1438,7 +1438,7 @@ i3c11_bus: i3c11-bus-pins {
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
};
hsi223_bus: hsi2c23-bus-pins {
hsi2c23_bus: hsi2c23-bus-pins {
samsung,pins = "gpp11-2", "gpp11-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;

1434
arch/arm64/boot/dts/exynos/exynos2200.dtsi
View File

File diff suppressed because it is too large Load Diff

1
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View File

@ -937,6 +937,7 @@ reboot: syscon-reboot {
gic: interrupt-controller@11001000 {
compatible = "arm,gic-400";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x11001000 0x1000>,

15
arch/arm64/boot/dts/exynos/exynos850-e850-96.dts
View File

@ -21,6 +21,7 @@ / {
compatible = "winlink,e850-96", "samsung,exynos850";
aliases {
ethernet0 = &ethernet;
mmc0 = &mmc_0;
serial0 = &serial_0;
};
@ -241,10 +242,24 @@ &usbdrd {
};
&usbdrd_dwc3 {
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "otg";
usb-role-switch;
role-switch-default-mode = "host";
hub@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethernet: ethernet@1 {
compatible = "usb424,ec00";
reg = <1>;
};
};
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&usb_dr_connector>;

2
arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi
View File

@ -202,7 +202,7 @@ bt_btwake: bt-btwake-pins {
};
bt_en: bt-en-pins {
samsung,pins ="gpj1-7";
samsung,pins = "gpj1-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;

16
arch/arm64/boot/dts/exynos/exynos990-c1s.dts
View File

@ -44,6 +44,12 @@ memory@80000000 {
<0x8 0x80000000 0x1 0x7ec00000>;
};
/* TODO: Remove this once PMIC is implemented */
reg_dummy: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "dummy_reg";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -113,3 +119,13 @@ key_volup: key-volup-pins {
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
};
&usbdrd {
status = "okay";
vdd10-supply = <&reg_dummy>;
vdd33-supply = <&reg_dummy>;
};
&usbdrd_phy {
status = "okay";
};

16
arch/arm64/boot/dts/exynos/exynos990-r8s.dts
View File

@ -44,6 +44,12 @@ memory@80000000 {
<0x8 0x80000000 0x0 0xc0000000>;
};
/* TODO: Remove this once PMIC is implemented */
reg_dummy: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "dummy_reg";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -113,3 +119,13 @@ key_volup: key-volup-pins {
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
};
&usbdrd {
status = "okay";
vdd10-supply = <&reg_dummy>;
vdd33-supply = <&reg_dummy>;
};
&usbdrd_phy {
status = "okay";
};

16
arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi
View File

@ -27,6 +27,12 @@ framebuffer0: framebuffer@f1000000 {
};
};
/* TODO: Remove this once PMIC is implemented */
reg_dummy: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "dummy_reg";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -96,3 +102,13 @@ key_volup: key-volup-pins {
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
};
};
&usbdrd {
status = "okay";
vdd10-supply = <&reg_dummy>;
vdd33-supply = <&reg_dummy>;
};
&usbdrd_phy {
status = "okay";
};

77
arch/arm64/boot/dts/exynos/exynos990.dtsi
View File

@ -211,6 +211,30 @@ timer@10040000 {
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog_cl0: watchdog@10050000 {
compatible = "samsung,exynos990-wdt";
reg = <0x10050000 0x100>;
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK>,
<&oscclk>;
clock-names = "watchdog",
"watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <0>;
};
watchdog_cl2: watchdog@10060000 {
compatible = "samsung,exynos990-wdt";
reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK>,
<&oscclk>;
clock-names = "watchdog",
"watchdog_src";
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <2>;
};
gic: interrupt-controller@10101000 {
compatible = "arm,gic-400";
reg = <0x10101000 0x1000>,
@ -225,12 +249,34 @@ gic: interrupt-controller@10101000 {
#size-cells = <1>;
};
cmu_peric0: clock-controller@10400000 {
compatible = "samsung,exynos990-cmu-peric0";
reg = <0x10400000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
clock-names = "oscclk", "bus", "ip";
};
pinctrl_peric0: pinctrl@10430000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x10430000 0x1000>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
};
cmu_peric1: clock-controller@10700000 {
compatible = "samsung,exynos990-cmu-peric1";
reg = <0x10700000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
clock-names = "oscclk", "bus", "ip";
};
pinctrl_peric1: pinctrl@10730000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x10730000 0x1000>;
@ -254,6 +300,37 @@ cmu_hsi0: clock-controller@10a00000 {
"dpgtc";
};
usbdrd_phy: phy@10c00000 {
compatible = "samsung,exynos990-usbdrd-phy";
reg = <0x10c00000 0x100>;
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>,
<&oscclk>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
status = "disabled";
};
usbdrd: usb@10e00000 {
compatible = "samsung,exynos990-dwusb3",
"samsung,exynos850-dwusb3";
ranges = <0x0 0x10e00000 0x10000>;
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>,
<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40>;
clock-names = "bus_early", "ref";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
usbdrd_dwc3: usb@0 {
compatible = "snps,dwc3";
reg = <0x0 0x10000>;
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>;
phy-names = "usb2-phy";
};
};
pinctrl_hsi1: pinctrl@13040000 {
compatible = "samsung,exynos990-pinctrl";
reg = <0x13040000 0x1000>;

1
arch/arm64/boot/dts/exynos/google/gs101.dtsi
View File

@ -341,6 +341,7 @@ watchdog_cl1: watchdog@10070000 {
gic: interrupt-controller@10400000 {
compatible = "arm,gic-v3";
#address-cells = <0>;
#interrupt-cells = <4>;
interrupt-controller;
reg = <0x10400000 0x10000>, /* GICD */

1
arch/arm64/boot/dts/tesla/fsd.dtsi
View File

@ -363,6 +363,7 @@ soc: soc@0 {
gic: interrupt-controller@10400000 {
compatible = "arm,gic-v3";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */