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clk: rockchip: px30: Add clock id for pclk_otp_phy

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Change-Id: If9c368c6ff93d31f306ab16dbf49dd698f320f72
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2018-01-26 11:51:39 +08:00 committed by Tao Huang
parent 05365c87be
commit 545c52479c
2 changed files with 3 additions and 2 deletions
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2
drivers/clk/rockchip/clk-px30.c
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@ -819,7 +819,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
/* PD_BUS_TOP */
GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
GATE(0, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),

3
include/dt-bindings/clock/px30-cru.h
View File

@ -180,8 +180,9 @@
#define PCLK_GPIO3 350
#define PCLK_ISP 351
#define PCLK_CIF 352
#define PCLK_OTP_PHY 353
#define CLK_NR_CLKS (PCLK_CIF + 1)
#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
/* pmu-clocks indices */