From 545c52479c788470052c8c458bc0ec69ad049119 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 26 Jan 2018 11:51:39 +0800 Subject: [PATCH] clk: rockchip: px30: Add clock id for pclk_otp_phy Change-Id: If9c368c6ff93d31f306ab16dbf49dd698f320f72 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-px30.c | 2 +- include/dt-bindings/clock/px30-cru.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 2f645f3a7f26..733018ecd213 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -819,7 +819,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { /* PD_BUS_TOP */ GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS), GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS), - GATE(0, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS), + GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS), GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS), GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS), GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS), diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h index 80f1be61ff0d..b508d638b00a 100644 --- a/include/dt-bindings/clock/px30-cru.h +++ b/include/dt-bindings/clock/px30-cru.h @@ -180,8 +180,9 @@ #define PCLK_GPIO3 350 #define PCLK_ISP 351 #define PCLK_CIF 352 +#define PCLK_OTP_PHY 353 -#define CLK_NR_CLKS (PCLK_CIF + 1) +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) /* pmu-clocks indices */