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EDAC/igen6: Fix channel selection hash

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In channel selection hash mode, the hardware decoding logic always
includes the channel interleave bit in XOR operations. However, the
hash mask may or may not include this channel interleave bit. When
the mask does include this bit, the current igen6_edac code performs
XOR on the interleave bit twice, effectively ignoring it - which is
incorrect.

Fix this issue by ensuring the hash mask always includes the interleave
bit, so XOR is performed on the interleave bit exactly once.

Fixes: 10590a9d4f ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC")
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20260730024238.4096623-4-qiuxu.zhuo@intel.com
This commit is contained in:
Qiuxu Zhuo 2026-07-30 10:42:31 +08:00 committed by Tony Luck
parent f4008169bd
commit 540b79536f
1 changed files with 11 additions and 3 deletions
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14
drivers/edac/igen6_edac.c
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@ -1009,14 +1009,22 @@ static void set_dimm_params(struct igen6_imc *imc, int chan)
static int decode_chan_idx(u64 addr, u64 mask, int intlv_bit)
{
u64 hash_addr = addr & mask, hash = 0;
u64 intlv = (addr >> intlv_bit) & 1;
u64 hash_addr, hash = 0;
int i;
/*
* In hash mode, the @intlv_bit is the lowest selected bit of @addr
* to be XORed. While @mask may or may not include this @intlv_bit,
* we enforce that @mask includes @intlv_bit to ensure @intlv_bit is
* XORed exactly once.
*/
mask |= 1 << intlv_bit;
hash_addr = addr & mask;
for (i = 6; i < 20; i++)
hash ^= (hash_addr >> i) & 1;
return (int)hash ^ intlv;
return (int)hash;
}
static u64 decode_channel_addr(u64 addr, int intlv_bit)