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pinctrl: qcom: eliza: Split QUP1_SE4 lanes

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QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
function name cannot be the same or the alternate function cannot
be selected.

Split them up into individual lane functions so boards can specify.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Alexander Koskovich 2026-04-23 04:43:46 +00:00 committed by Linus Walleij
parent cef1554c4f
commit 4f5b1f4e77
1 changed files with 24 additions and 6 deletions
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30
drivers/pinctrl/qcom/pinctrl-eliza.c
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@ -568,7 +568,10 @@ enum eliza_functions {
msm_mux_qup1_se2_l3_mira, msm_mux_qup1_se2_l3_mira,
msm_mux_qup1_se2_l3_mirb, msm_mux_qup1_se2_l3_mirb,
msm_mux_qup1_se3, msm_mux_qup1_se3,
msm_mux_qup1_se4, msm_mux_qup1_se4_l0,
msm_mux_qup1_se4_l1,
msm_mux_qup1_se4_l2,
msm_mux_qup1_se4_l3,
msm_mux_qup1_se5, msm_mux_qup1_se5,
msm_mux_qup1_se6, msm_mux_qup1_se6,
msm_mux_qup1_se6_l1_mira, msm_mux_qup1_se6_l1_mira,
@ -1017,8 +1020,20 @@ static const char *const qup1_se3_groups[] = {
"gpio44", "gpio45", "gpio46", "gpio47", "gpio44", "gpio45", "gpio46", "gpio47",
}; };
static const char *const qup1_se4_groups[] = { static const char *const qup1_se4_l0_groups[] = {
"gpio36", "gpio37", "gpio37", "gpio36", "gpio36",
};
static const char *const qup1_se4_l1_groups[] = {
"gpio37",
};
static const char *const qup1_se4_l2_groups[] = {
"gpio37",
};
static const char *const qup1_se4_l3_groups[] = {
"gpio36",
}; };
static const char *const qup1_se5_groups[] = { static const char *const qup1_se5_groups[] = {
@ -1321,7 +1336,10 @@ static const struct pinfunction eliza_functions[] = {
MSM_PIN_FUNCTION(qup1_se2_l3_mira), MSM_PIN_FUNCTION(qup1_se2_l3_mira),
MSM_PIN_FUNCTION(qup1_se2_l3_mirb), MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
MSM_PIN_FUNCTION(qup1_se3), MSM_PIN_FUNCTION(qup1_se3),
MSM_PIN_FUNCTION(qup1_se4), MSM_PIN_FUNCTION(qup1_se4_l0),
MSM_PIN_FUNCTION(qup1_se4_l1),
MSM_PIN_FUNCTION(qup1_se4_l2),
MSM_PIN_FUNCTION(qup1_se4_l3),
MSM_PIN_FUNCTION(qup1_se5), MSM_PIN_FUNCTION(qup1_se5),
MSM_PIN_FUNCTION(qup1_se6), MSM_PIN_FUNCTION(qup1_se6),
MSM_PIN_FUNCTION(qup1_se6_l1_mira), MSM_PIN_FUNCTION(qup1_se6_l1_mira),
@ -1418,8 +1436,8 @@ static const struct msm_pingroup eliza_groups[] = {
[33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _), [33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),
[34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _), [34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),
[35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _), [35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),
[36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), [36] = PINGROUP(36, qup1_se4_l0, qup1_se4_l3, ibi_i3c, _, _, _, _, _, _, _, _),
[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _), [37] = PINGROUP(37, qup1_se4_l1, qup1_se4_l2, ibi_i3c, _, _, _, _, _, _, _, _),
[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), [38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), [40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),