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pinctrl: qcom: eliza: Split QUP lane mirror alternates
Several QUP lanes have MIRA/MIRB mirror routings which are collapsed under a single function name (e.g. qup1_se6). This is an issue because it means there are multiple functions defined for a given pin that share the same name: [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6... So when you select pin 42 and request function qup1_se6, it will select the first instance of it in this group, which just happens to be QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively unreachable. Split each of these lanes that has an alternative GPIO into their own function so they can actually be selected, following the pattern seen in pinctrl-sm8550.c. Signed-off-by: Alexander Koskovich <akoskovich@pm.me> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Alexander Koskovich
Linus Walleij
parent
1bd5c56253
commit
cef1554c4f
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@ -563,15 +563,31 @@ enum eliza_functions {
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msm_mux_qup1_se0,
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msm_mux_qup1_se1,
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msm_mux_qup1_se2,
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msm_mux_qup1_se2_l2_mira,
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msm_mux_qup1_se2_l2_mirb,
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msm_mux_qup1_se2_l3_mira,
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msm_mux_qup1_se2_l3_mirb,
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msm_mux_qup1_se3,
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msm_mux_qup1_se4,
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msm_mux_qup1_se5,
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msm_mux_qup1_se6,
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msm_mux_qup1_se6_l1_mira,
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msm_mux_qup1_se6_l1_mirb,
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msm_mux_qup1_se6_l3_mira,
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msm_mux_qup1_se6_l3_mirb,
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msm_mux_qup1_se7,
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msm_mux_qup1_se7_l0_mira,
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msm_mux_qup1_se7_l0_mirb,
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msm_mux_qup1_se7_l1_mira,
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msm_mux_qup1_se7_l1_mirb,
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msm_mux_qup2_se0,
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msm_mux_qup2_se1,
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msm_mux_qup2_se2,
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msm_mux_qup2_se3,
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msm_mux_qup2_se3_l0_mira,
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msm_mux_qup2_se3_l0_mirb,
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msm_mux_qup2_se3_l1_mira,
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msm_mux_qup2_se3_l1_mirb,
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msm_mux_qup2_se4,
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msm_mux_qup2_se5,
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msm_mux_qup2_se6,
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@ -978,7 +994,23 @@ static const char *const qup1_se1_groups[] = {
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};
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static const char *const qup1_se2_groups[] = {
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"gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gpio42", "gpio30",
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"gpio52", "gpio53", "gpio40", "gpio42", "gpio30",
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};
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static const char *const qup1_se2_l2_mira_groups[] = {
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"gpio54",
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};
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static const char *const qup1_se2_l2_mirb_groups[] = {
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"gpio52",
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};
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static const char *const qup1_se2_l3_mira_groups[] = {
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"gpio55",
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};
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static const char *const qup1_se2_l3_mirb_groups[] = {
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"gpio53",
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};
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static const char *const qup1_se3_groups[] = {
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@ -994,11 +1026,43 @@ static const char *const qup1_se5_groups[] = {
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};
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static const char *const qup1_se6_groups[] = {
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"gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55",
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"gpio40", "gpio42",
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};
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static const char *const qup1_se6_l1_mira_groups[] = {
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"gpio42",
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};
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static const char *const qup1_se6_l1_mirb_groups[] = {
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"gpio54",
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};
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static const char *const qup1_se6_l3_mira_groups[] = {
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"gpio40",
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};
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static const char *const qup1_se6_l3_mirb_groups[] = {
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"gpio55",
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};
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static const char *const qup1_se7_groups[] = {
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"gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78",
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"gpio78", "gpio114",
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};
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static const char *const qup1_se7_l0_mira_groups[] = {
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"gpio81",
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};
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static const char *const qup1_se7_l0_mirb_groups[] = {
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"gpio78",
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};
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static const char *const qup1_se7_l1_mira_groups[] = {
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"gpio80",
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};
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static const char *const qup1_se7_l1_mirb_groups[] = {
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"gpio114",
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};
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static const char *const qup2_se0_groups[] = {
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@ -1014,7 +1078,23 @@ static const char *const qup2_se2_groups[] = {
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};
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static const char *const qup2_se3_groups[] = {
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"gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116",
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"gpio100", "gpio116",
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};
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static const char *const qup2_se3_l0_mira_groups[] = {
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"gpio79",
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};
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static const char *const qup2_se3_l0_mirb_groups[] = {
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"gpio116",
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};
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static const char *const qup2_se3_l1_mira_groups[] = {
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"gpio97",
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};
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static const char *const qup2_se3_l1_mirb_groups[] = {
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"gpio100",
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};
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static const char *const qup2_se4_groups[] = {
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@ -1236,15 +1316,31 @@ static const struct pinfunction eliza_functions[] = {
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MSM_PIN_FUNCTION(qup1_se0),
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MSM_PIN_FUNCTION(qup1_se1),
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MSM_PIN_FUNCTION(qup1_se2),
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MSM_PIN_FUNCTION(qup1_se2_l2_mira),
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MSM_PIN_FUNCTION(qup1_se2_l2_mirb),
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MSM_PIN_FUNCTION(qup1_se2_l3_mira),
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MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
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MSM_PIN_FUNCTION(qup1_se3),
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MSM_PIN_FUNCTION(qup1_se4),
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MSM_PIN_FUNCTION(qup1_se5),
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MSM_PIN_FUNCTION(qup1_se6),
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MSM_PIN_FUNCTION(qup1_se6_l1_mira),
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MSM_PIN_FUNCTION(qup1_se6_l1_mirb),
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MSM_PIN_FUNCTION(qup1_se6_l3_mira),
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MSM_PIN_FUNCTION(qup1_se6_l3_mirb),
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MSM_PIN_FUNCTION(qup1_se7),
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MSM_PIN_FUNCTION(qup1_se7_l0_mira),
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MSM_PIN_FUNCTION(qup1_se7_l0_mirb),
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MSM_PIN_FUNCTION(qup1_se7_l1_mira),
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MSM_PIN_FUNCTION(qup1_se7_l1_mirb),
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MSM_PIN_FUNCTION(qup2_se0),
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MSM_PIN_FUNCTION(qup2_se1),
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MSM_PIN_FUNCTION(qup2_se2),
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MSM_PIN_FUNCTION(qup2_se3),
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MSM_PIN_FUNCTION(qup2_se3_l0_mira),
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MSM_PIN_FUNCTION(qup2_se3_l0_mirb),
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MSM_PIN_FUNCTION(qup2_se3_l1_mira),
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MSM_PIN_FUNCTION(qup2_se3_l1_mirb),
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MSM_PIN_FUNCTION(qup2_se4),
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MSM_PIN_FUNCTION(qup2_se5),
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MSM_PIN_FUNCTION(qup2_se6),
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@ -1326,9 +1422,9 @@ static const struct msm_pingroup eliza_groups[] = {
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[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
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[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
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[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
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[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
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[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
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[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),
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[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),
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[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6_l1_mira, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),
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[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),
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[44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),
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[45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),
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@ -1338,10 +1434,10 @@ static const struct msm_pingroup eliza_groups[] = {
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[49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _),
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[50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),
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[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),
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[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),
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[53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),
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[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
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[55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),
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[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),
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[53] = PINGROUP(53, qup1_se2, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),
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[54] = PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
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[55] = PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),
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[56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),
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[57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
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[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),
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@ -1364,10 +1460,10 @@ static const struct msm_pingroup eliza_groups[] = {
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[75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),
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[76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),
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[77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),
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[78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),
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[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _),
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[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),
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[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _),
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[78] = PINGROUP(78, qup1_se7, qup1_se7_l0_mirb, _, phase_flag, _, _, _, _, _, _, _),
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[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, _, _, _),
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[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _, _, _, _, _, _, _),
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[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _, _, _, _, _, _),
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[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),
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[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),
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[84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),
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@ -1383,10 +1479,10 @@ static const struct msm_pingroup eliza_groups[] = {
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[94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),
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[95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),
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[96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),
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[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _),
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[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, _, _, _),
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[98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),
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[99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),
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[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _),
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[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _),
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[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
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[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),
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[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),
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@ -1400,9 +1496,9 @@ static const struct msm_pingroup eliza_groups[] = {
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[111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),
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[112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),
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[113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),
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[114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),
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[114] = PINGROUP(114, qup1_se7, qup1_se7_l1_mirb, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),
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[115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),
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[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _),
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[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3_l0_mirb, _, _, _, _, _, _, _),
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[117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),
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[118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),
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[119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),
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