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dt-bindings: pinctrl: brcm,nsp-gpio: Convert to DT schema
The brcm,nsp-gpio-a compatible used by the NSP GPIO controller was only documented in the legacy text binding, so dtbs_check reported "failed to match any schema" for the gpio@20 node in bcm-nsp.dtsi. Convert the text binding to DT schema. Beyond a direct conversion: - Require pin configuration nodes to use a '-pins' suffix and GPIO hogs a '-hog' suffix, as the old example used arbitrary node names. No in-tree DTS has child nodes under this controller, so nothing is affected. - Document slew-rate, which the driver supports but the text binding never listed. - Add #interrupt-cells and gpio-line-names, and make #interrupt-cells depend on interrupt-controller. Assisted-by: LLM Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Rosen Penev
Linus Walleij
parent
2430546e8d
commit
4f0dbdbdb3
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Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
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Required properties:
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- compatible:
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Must be "brcm,nsp-gpio-a"
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- reg:
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Should contain the register physical address and length for each of
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GPIO base, IO control registers
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- #gpio-cells:
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Must be two. The first cell is the GPIO pin number (within the
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controller's pin space) and the second cell is used for the following:
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bit[0]: polarity (0 for active high and 1 for active low)
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- gpio-controller:
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Specifies that the node is a GPIO controller
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- ngpios:
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Number of gpios supported (58x25 supports 32 and 58x23 supports 24)
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Optional properties:
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- interrupts:
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Interrupt ID
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- interrupt-controller:
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Specifies that the node is an interrupt controller
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- gpio-ranges:
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Specifies the mapping between gpio controller and pin-controllers pins.
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This requires 4 fields in cells defined as -
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1. Phandle of pin-controller.
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2. GPIO base pin offset.
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3 Pin-control base pin offset.
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4. number of gpio pins which are linearly mapped from pin base.
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Supported generic PINCONF properties in child nodes:
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- pins:
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The list of pins (within the controller's own pin space) that properties
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in the node apply to. Pin names are "gpio-<pin>"
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- bias-disable:
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Disable pin bias
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- bias-pull-up:
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Enable internal pull up resistor
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- bias-pull-down:
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Enable internal pull down resistor
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- drive-strength:
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Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
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Example:
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gpioa: gpio@18000020 {
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compatible = "brcm,nsp-gpio-a";
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reg = <0x18000020 0x100>,
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<0x1803f1c4 0x1c>;
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#gpio-cells = <2>;
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gpio-controller;
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ngpios = <32>;
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gpio-ranges = <&pinctrl 0 0 31>;
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interrupt-controller;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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/* Hog a few default settings */
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pinctrl-names = "default";
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pinctrl-0 = <&led>;
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led: led {
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pins = "gpio-1";
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bias-pull-up;
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};
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pwr: pwr {
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gpio-hog;
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gpios = <3 1>;
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output-high;
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};
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};
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130
Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml
Normal file
130
Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.yaml
Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/brcm,nsp-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom Northstar Plus (NSP) GPIO/PINCONF Controller
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maintainers:
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- Ray Jui <rjui@broadcom.com>
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- Scott Branden <sbranden@broadcom.com>
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description: |
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The chipCommonA GPIO block also provides generic pin configuration for the
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pins it controls: bias, pull up/down, slew rate and drive strength. Pin
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configuration is described in '-pins' child nodes, referenced through the
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standard pinctrl-0/pinctrl-names properties. Child nodes named '*-hog' are
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treated as GPIO hogs.
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properties:
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compatible:
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const: brcm,nsp-gpio-a
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reg:
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items:
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- description: GPIO base registers
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- description: IO control registers
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"#gpio-cells":
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const: 2
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description: |
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The first cell is the GPIO pin number (within the controller's pin
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space) and the second cell is used for the following:
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bit[0]: polarity (0 for active high and 1 for active low)
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gpio-controller: true
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ngpios:
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description: Number of GPIOs supported (58x25 supports 32 and 58x23 supports 24)
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maximum: 32
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interrupts:
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maxItems: 1
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"#interrupt-cells":
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const: 2
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interrupt-controller: true
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gpio-ranges: true
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gpio-line-names: true
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required:
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- compatible
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- reg
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- "#gpio-cells"
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- gpio-controller
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- ngpios
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dependencies:
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interrupt-controller: ['#interrupt-cells']
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patternProperties:
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'-pins$':
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type: object
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$ref: pincfg-node.yaml#
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properties:
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pins:
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$ref: /schemas/types.yaml#/definitions/string-array
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items:
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pattern: '^gpio-'
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bias-disable: true
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bias-pull-up: true
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bias-pull-down: true
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drive-strength:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ]
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slew-rate:
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description: 0 disables and 1 enables slew rate control
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enum: [ 0, 1 ]
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required:
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- pins
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additionalProperties: false
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'-hog(-[0-9]+)?$':
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type: object
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required:
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- gpio-hog
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gpio@18000020 {
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compatible = "brcm,nsp-gpio-a";
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reg = <0x18000020 0x100>,
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<0x1803f1c4 0x1c>;
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#gpio-cells = <2>;
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gpio-controller;
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ngpios = <32>;
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gpio-ranges = <&pinctrl 0 0 31>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&led_pins>;
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led_pins: led-pins {
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pins = "gpio-1";
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bias-pull-up;
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drive-strength = <16>;
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};
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/* GPIO hog */
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pwr-hog {
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gpio-hog;
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gpios = <3 1>;
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output-high;
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};
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};
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