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Qualcomm pin control updates for v7.4-rc1

Browse Source 
New drivers:
 - add the TLMM drivers for Kuno and MSM8952
 - add the LPASS LPI driver for Hawi
 
 New model support:
 - support PMAU0102 GPIO in pinctrl-spmi-gpio
 
 Driver improvements:
 - fix/unify naming convention in defines specific to Qualcomm pinctrl
   drivers
 - extend debugfs verbosity for pinctrl-lpass-lpi
 - make the return type from kcalloc() const in tlmm-test
 
 Devicetree bindings:
 - add binding documents for new drivers
 - document compatibles for new models
 - document the gpio-line-names property for qcom,sc8280xp-tlmm
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEkeUTLeW1Rh17omX8BZ0uy/82hMMFAmrHX04ACgkQBZ0uy/82
 hMOrCw/+MH4F54/8/U0z3Culd5ridWQa91fK52cGfnukrxL3Uwo8bva08ZBLS+Od
 bXeESRTIOk7XgeEpw4S1CI6f6n2vEiCb/9HUv8WVWaVxK6DBLEXbroDTDeV7krnW
 psMp4e2MNuqn2UfBwyRvaqQVNev6tp7y0QkdL0ZfBA2So9UfHXfwedfzvuLrVJAs
 bCfUOWqLOWnCv0kL8h1HMmVtyBEWEoarFaSZ7TSCuQMRBrE0ydF4Bg58SKo3EaFS
 A3MrfjL2lE2JtiL4/rTFvFFU+fRdyypS5PPefMr/WeojHKRMLZnvZcR4gLJlWssR
 rN2shMfGYdtYBmJPhKkbpgTPK3Dn4YylAVfTq/sWBH3i70DBafr+plJc39ziSdGd
 5ddw2UipBwQ17pIxSEXSka6d7YNxV9XyC99Z8G3sXimY0J9Ckbr9c6sj/pE7GWY9
 LzxF/FHLsqCU9VL9olNXfgV41BTxLyHU2tqB1M7kYRt3htsndXKtv+J8+6rB9N/Z
 Dgl52SFOVngsiRRCYz5uF7iNz80WWMJW4Z/si7FHOiSfx1HQYYcyg6H6Kotiu2I6
 kMAc6fPQJskBX2I4UazOsUyiItZf/CpOf2IxGNFCokeYGQjF/S/Kx7EEzHnwpbIq
 RII+mpTiMnh363hRPds2wQMws6ugbDNELPw6+hAHk5Of6DRtzaA=
 =+sqz
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-qcom-updates-for-v7.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel

Qualcomm pin control updates for v7.4-rc1

New drivers:
- add the TLMM drivers for Kuno and MSM8952
- add the LPASS LPI driver for Hawi

New model support:
- support PMAU0102 GPIO in pinctrl-spmi-gpio

Driver improvements:
- fix/unify naming convention in defines specific to Qualcomm pinctrl
  drivers
- extend debugfs verbosity for pinctrl-lpass-lpi
- make the return type from kcalloc() const in tlmm-test

Devicetree bindings:
- add binding documents for new drivers
- document compatibles for new models
- document the gpio-line-names property for qcom,sc8280xp-tlmm

Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij 2026-10-08 13:40:20 +02:00
commit 2430546e8d
20 changed files with 3282 additions and 580 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

109
Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml Normal file
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@ -0,0 +1,109 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Hawi SoC LPASS LPI TLMM
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
- Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC.
properties:
compatible:
const: qcom,hawi-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
clocks:
items:
- description: LPASS LPR(Low Power Resource) voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: lpr
- const: audio
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-hawi-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-hawi-lpass-state"
additionalProperties: false
$defs:
qcom-hawi-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
function:
enum: [dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws,
lpass_lpi_dbg_clk, qca_swr_clk, qca_swr_data, slimbus_clk,
slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_clk1,
swr_tx_data, va_i2s0_clk, va_i2s0_data, va_i2s0_ws,
wsa2_swr_clk, wsa2_swr_data, wsa_swr_clk, wsa_swr_data]
description:
Specify the alternative function to be configured for the specified
pins.
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
lpass_tlmm: pinctrl@7f60000 {
compatible = "qcom,hawi-lpass-lpi-pinctrl";
reg = <0x07f60000 0x20000>;
clocks = <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "lpr", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
tx-swr-sleep-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
bias-pull-down;
};
};

110
Documentation/devicetree/bindings/pinctrl/qcom,kuno-tlmm.yaml Normal file
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@ -0,0 +1,110 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,kuno-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Kuno TLMM block
maintainers:
- Hardeep Sharma <hardeep.sharma@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Kuno SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,kuno-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 55
gpio-line-names:
maxItems: 110
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-kuno-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-kuno-tlmm-state"
additionalProperties: false
$defs:
qcom-kuno-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9])$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, audio_ref_clk, coex_uart, ebi2_lcd_a,
ebi2_lcd_cs, ebi2_lcd_reset, ebi2_lcd_te, emac_mdc, emac_mdio,
emac_pps_in, emac_ptp_aux, emac_ptp_pps, gcc_gp1_clk,
gcc_gp2_clk, gcc_gp3_clk, mi2s0_data0, mi2s0_data1, mi2s0_sck,
mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
mi2s_mclk, nav_gpio, pci_e_rst,
pcie_clkreq_n, pll_bist_sync, pll_clk_aux, qdss_cti_trig0,
qdss_cti_trig1, qdss_cti_trig1_mire, qdss_gpio_traceclk,
qdss_gpio_tracectl,
qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se3_mirb,
qup0_se4, sdc4_clk, sdc4_cmd,
sdc4_data, sdc4_tb_trig, sgmii_phy_intr, spmi_coex_clk,
spmi_coex_data, spmi_vgi_hwevent, uim1_clk, uim1_data,
uim1_present, uim1_reset, usb2phy_ac_en ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f000000 {
compatible = "qcom,kuno-tlmm";
reg = <0x0f000000 0x400000>;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 110>;
interrupt-controller;
#interrupt-cells = <2>;
spmi-state {
pins = "gpio78", "gpio79";
function = "spmi_vgi_hwevent";
};
};
...

146
Documentation/devicetree/bindings/pinctrl/qcom,msm8952-pinctrl.yaml Normal file
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@ -0,0 +1,146 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8952-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8952 TLMM pin controller
maintainers:
- Muzaffer Kadir <muzafferkadir@mainlining.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MSM8952 SoC.
properties:
compatible:
const: qcom,msm8952-pinctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 66
gpio-line-names:
maxItems: 134
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-msm8952-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-msm8952-tlmm-state"
additionalProperties: false
$defs:
qcom-msm8952-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-3])$"
- enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, blsp_uart1, blsp_spi1, adsp_ext, blsp_i2c1, prng_rosc, qdss_cti_trig_out_b0,
qdss_cti_trig_out_a1, blsp_spi2, blsp_uart2, ldo_update, qdss_tracedata_b,
pbs1, pwr_modem_enabled_b, blsp_i2c3, gcc_gp2_clk_b, atest_combodac_to_gpio_native,
ldo_en, blsp_i2c2, gcc_gp1_clk_b, atest_gpsadc_dtest0_native, blsp_spi3,
blsp_uart3, sec_mi2s, pbs0, gcc_gp3_clk_b, blsp_spi4, blsp_uart4, pbs2,
pwr_nav_enabled_b, pwr_crypto_enabled_b, blsp_i2c4, blsp_spi5, blsp_uart5,
qdss_traceclk_a, atest_bbrx1, qdss_tracectl_b, qdss_cti_trig_in_b0, blsp_i2c6,
qdss_traceclk_b, atest_wlan0, m_voc, qdss_cti_trig_in_a0, atest_bbrx0, blsp_i2c5,
qdss_tracectl_a, atest_gpsadc_dtest1_native, qdss_tracedata_a, blsp_spi6,
blsp_uart6, atest_wlan1, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a,
cam_mclk, cci_i2c, pwr_modem_enabled_a, cci_timer0, cci_timer1, pwr_nav_enabled_a,
pwr_crypto_enabled_a, cci_async, sd_write, qdss_cti_trig_out_a0, gcc_gp1_clk_a,
gcc_gp2_clk_a, gcc_gp3_clk_a, blsp6_spi, qdss_cti_trig_in_b1, uim_batt,
qdss_cti_trig_out_b1, uim1_data, uim1_clk, uim1_reset, uim1_present, uim2_data,
uim2_clk, uim2_reset, uim2_present, uim3_data, usb_fs, uim3_clk, uim3_reset,
uim3_present, atest_char3, dbg_out, bimc_dte0, sec_mi2s_mclk_b, pri_mi2s,
atest_char1, ebi_cdc, atest_char0, cdc_pdm0, pri_mi2s_mclk_b, lpass_slimbus,
lpass_slimbus0, lpass_slimbus1, wcss_bt, atest_char2, ebi_ch0, wcss_wlan2,
wcss_wlan1, wcss_wlan0, wcss_wlan, wcss_fm, ext_lpass, gcc_tlmm, dmic0_clk,
dmic0_data, qdss_cti_trig_in_a1, blsp_spi7, blsp_uart7, pri_mi2s_ws, wsa_io,
blsp_i2c7, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, nav_pps_in_a,
pa_indicator, nav_pps_in_b, nav_pps, modem_tsync, nav_tsync, ssbi_wtr1,
gsm1_tx, gsm0_tx, atest_char, atest_tsens, bimc_dte1,
gp_mn, gp_pdm_0a, gp_pdm_0b, gp_pdm_1a, gp_pdm_1b,
gp_pdm_2a, gp_pdm_2b, gp0_clk, gp1_clk]
required:
- pins
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
msmgpio: pinctrl@1000000 {
compatible = "qcom,msm8952-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&msmgpio 0 0 134>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1-uart2-sleep-state {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
spi1-default-state {
spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
cs-pins {
pins = "gpio2";
function = "blsp_spi1";
drive-strength = <2>;
bias-disable;
};
};
};

3
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -57,6 +57,7 @@ properties:
- qcom,pm8994-gpio
- qcom,pm8998-gpio
- qcom,pma8084-gpio
- qcom,pmau0102-gpio
- qcom,pmc8180-gpio
- qcom,pmc8180c-gpio
- qcom,pmc8380-gpio
@ -281,6 +282,7 @@ allOf:
- qcom,pm8150l-gpio
- qcom,pm8550-gpio
- qcom,pm8550b-gpio
- qcom,pmau0102-gpio
- qcom,pmc8180c-gpio
- qcom,pmp8074-gpio
- qcom,pms405-gpio
@ -496,6 +498,7 @@ $defs:
- gpio1-gpio22 for pm8994
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084
- gpio1-gpio12 for pmau0102
- gpio1-gpio14 for pmcx0102
- gpio1-gpio4 for pmd8028
- gpio1-gpio4 for pmg1110

3
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
View File

@ -27,6 +27,9 @@ properties:
gpio-reserved-ranges: true
gpio-line-names:
maxItems: 230
patternProperties:
"-state$":
oneOf:

10
drivers/pinctrl/qcom/Kconfig
View File

@ -62,6 +62,16 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
config PINCTRL_HAWI_LPASS_LPI
tristate "Qualcomm Technologies Inc Hawi LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc Hawi
platform.
config PINCTRL_MILOS_LPASS_LPI
tristate "Qualcomm Milos LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST

19
drivers/pinctrl/qcom/Kconfig.msm
View File

@ -153,6 +153,17 @@ config PINCTRL_KAANAPALI
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc Kaanapali platform.
config PINCTRL_KUNO
tristate "Qualcomm Kuno pin controller driver"
depends on ARM || COMPILE_TEST
default ARCH_QCOM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc Kuno platform.
Say Y here to compile statically, or M here to compile it as a
module. If unsure, say N.
config PINCTRL_MAILI
tristate "Qualcomm Technologies Inc Maili pin controller driver"
depends on ARM64 || COMPILE_TEST
@ -232,6 +243,14 @@ config PINCTRL_MSM8917
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8917, MSM8937 platform.
config PINCTRL_MSM8952
tristate "Qualcomm 8952 pin controller driver"
depends on ARM64 || COMPILE_TEST
default ARCH_QCOM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8952 platform.
config PINCTRL_MSM8953
tristate "Qualcomm 8953 pin controller driver"
depends on ARM64 || COMPILE_TEST

3
drivers/pinctrl/qcom/Makefile
View File

@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o
obj-$(CONFIG_PINCTRL_HAWI_LPASS_LPI) += pinctrl-hawi-lpass-lpi.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
@ -17,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o
obj-$(CONFIG_PINCTRL_IPQ9650) += pinctrl-ipq9650.o
obj-$(CONFIG_PINCTRL_KAANAPALI) += pinctrl-kaanapali.o
obj-$(CONFIG_PINCTRL_KUNO) += pinctrl-kuno.o
obj-$(CONFIG_PINCTRL_MAILI) += pinctrl-maili.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
@ -25,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8909) += pinctrl-msm8909.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
obj-$(CONFIG_PINCTRL_MSM8917) += pinctrl-msm8917.o
obj-$(CONFIG_PINCTRL_MSM8952) += pinctrl-msm8952.o
obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o
obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o
obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o

188
drivers/pinctrl/qcom/pinctrl-apq8064.c
View File

@ -214,17 +214,17 @@ static const unsigned int sdc3_data_pins[] = { 95 };
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
APQ_MUX_gpio, \
APQ_MUX_##f1, \
APQ_MUX_##f2, \
APQ_MUX_##f3, \
APQ_MUX_##f4, \
APQ_MUX_##f5, \
APQ_MUX_##f6, \
APQ_MUX_##f7, \
APQ_MUX_##f8, \
APQ_MUX_##f9, \
APQ_MUX_##f10, \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
}, \
.nfuncs = 11, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -276,48 +276,48 @@ static const unsigned int sdc3_data_pins[] = { 95 };
}
enum apq8064_functions {
APQ_MUX_cam_mclk,
APQ_MUX_codec_mic_i2s,
APQ_MUX_codec_spkr_i2s,
APQ_MUX_gp_clk_0a,
APQ_MUX_gp_clk_0b,
APQ_MUX_gp_clk_1a,
APQ_MUX_gp_clk_1b,
APQ_MUX_gp_clk_2a,
APQ_MUX_gp_clk_2b,
APQ_MUX_gpio,
APQ_MUX_gsbi1,
APQ_MUX_gsbi2,
APQ_MUX_gsbi3,
APQ_MUX_gsbi4,
APQ_MUX_gsbi4_cam_i2c,
APQ_MUX_gsbi5,
APQ_MUX_gsbi5_spi_cs1,
APQ_MUX_gsbi5_spi_cs2,
APQ_MUX_gsbi5_spi_cs3,
APQ_MUX_gsbi6,
APQ_MUX_gsbi6_spi_cs1,
APQ_MUX_gsbi6_spi_cs2,
APQ_MUX_gsbi6_spi_cs3,
APQ_MUX_gsbi7,
APQ_MUX_gsbi7_spi_cs1,
APQ_MUX_gsbi7_spi_cs2,
APQ_MUX_gsbi7_spi_cs3,
APQ_MUX_gsbi_cam_i2c,
APQ_MUX_hdmi,
APQ_MUX_mi2s,
APQ_MUX_riva_bt,
APQ_MUX_riva_fm,
APQ_MUX_riva_wlan,
APQ_MUX_sdc2,
APQ_MUX_sdc4,
APQ_MUX_slimbus,
APQ_MUX_spkr_i2s,
APQ_MUX_tsif1,
APQ_MUX_tsif2,
APQ_MUX_usb2_hsic,
APQ_MUX_ps_hold,
APQ_MUX_NA,
msm_mux_cam_mclk,
msm_mux_codec_mic_i2s,
msm_mux_codec_spkr_i2s,
msm_mux_gp_clk_0a,
msm_mux_gp_clk_0b,
msm_mux_gp_clk_1a,
msm_mux_gp_clk_1b,
msm_mux_gp_clk_2a,
msm_mux_gp_clk_2b,
msm_mux_gpio,
msm_mux_gsbi1,
msm_mux_gsbi2,
msm_mux_gsbi3,
msm_mux_gsbi4,
msm_mux_gsbi4_cam_i2c,
msm_mux_gsbi5,
msm_mux_gsbi5_spi_cs1,
msm_mux_gsbi5_spi_cs2,
msm_mux_gsbi5_spi_cs3,
msm_mux_gsbi6,
msm_mux_gsbi6_spi_cs1,
msm_mux_gsbi6_spi_cs2,
msm_mux_gsbi6_spi_cs3,
msm_mux_gsbi7,
msm_mux_gsbi7_spi_cs1,
msm_mux_gsbi7_spi_cs2,
msm_mux_gsbi7_spi_cs3,
msm_mux_gsbi_cam_i2c,
msm_mux_hdmi,
msm_mux_mi2s,
msm_mux_riva_bt,
msm_mux_riva_fm,
msm_mux_riva_wlan,
msm_mux_sdc2,
msm_mux_sdc4,
msm_mux_slimbus,
msm_mux_spkr_i2s,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_usb2_hsic,
msm_mux_ps_hold,
msm_mux_NA,
};
static const char * const cam_mclk_groups[] = {
@ -457,47 +457,47 @@ static const char * const usb2_hsic_groups[] = {
};
static const struct pinfunction apq8064_functions[] = {
APQ_PIN_FUNCTION(cam_mclk),
APQ_PIN_FUNCTION(codec_mic_i2s),
APQ_PIN_FUNCTION(codec_spkr_i2s),
APQ_PIN_FUNCTION(gp_clk_0a),
APQ_PIN_FUNCTION(gp_clk_0b),
APQ_PIN_FUNCTION(gp_clk_1a),
APQ_PIN_FUNCTION(gp_clk_1b),
APQ_PIN_FUNCTION(gp_clk_2a),
APQ_PIN_FUNCTION(gp_clk_2b),
APQ_PIN_FUNCTION(gpio),
APQ_PIN_FUNCTION(gsbi1),
APQ_PIN_FUNCTION(gsbi2),
APQ_PIN_FUNCTION(gsbi3),
APQ_PIN_FUNCTION(gsbi4),
APQ_PIN_FUNCTION(gsbi4_cam_i2c),
APQ_PIN_FUNCTION(gsbi5),
APQ_PIN_FUNCTION(gsbi5_spi_cs1),
APQ_PIN_FUNCTION(gsbi5_spi_cs2),
APQ_PIN_FUNCTION(gsbi5_spi_cs3),
APQ_PIN_FUNCTION(gsbi6),
APQ_PIN_FUNCTION(gsbi6_spi_cs1),
APQ_PIN_FUNCTION(gsbi6_spi_cs2),
APQ_PIN_FUNCTION(gsbi6_spi_cs3),
APQ_PIN_FUNCTION(gsbi7),
APQ_PIN_FUNCTION(gsbi7_spi_cs1),
APQ_PIN_FUNCTION(gsbi7_spi_cs2),
APQ_PIN_FUNCTION(gsbi7_spi_cs3),
APQ_PIN_FUNCTION(gsbi_cam_i2c),
APQ_PIN_FUNCTION(hdmi),
APQ_PIN_FUNCTION(mi2s),
APQ_PIN_FUNCTION(riva_bt),
APQ_PIN_FUNCTION(riva_fm),
APQ_PIN_FUNCTION(riva_wlan),
APQ_PIN_FUNCTION(sdc2),
APQ_PIN_FUNCTION(sdc4),
APQ_PIN_FUNCTION(slimbus),
APQ_PIN_FUNCTION(spkr_i2s),
APQ_PIN_FUNCTION(tsif1),
APQ_PIN_FUNCTION(tsif2),
APQ_PIN_FUNCTION(usb2_hsic),
APQ_PIN_FUNCTION(ps_hold),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(codec_mic_i2s),
MSM_PIN_FUNCTION(codec_spkr_i2s),
MSM_PIN_FUNCTION(gp_clk_0a),
MSM_PIN_FUNCTION(gp_clk_0b),
MSM_PIN_FUNCTION(gp_clk_1a),
MSM_PIN_FUNCTION(gp_clk_1b),
MSM_PIN_FUNCTION(gp_clk_2a),
MSM_PIN_FUNCTION(gp_clk_2b),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsbi1),
MSM_PIN_FUNCTION(gsbi2),
MSM_PIN_FUNCTION(gsbi3),
MSM_PIN_FUNCTION(gsbi4),
MSM_PIN_FUNCTION(gsbi4_cam_i2c),
MSM_PIN_FUNCTION(gsbi5),
MSM_PIN_FUNCTION(gsbi5_spi_cs1),
MSM_PIN_FUNCTION(gsbi5_spi_cs2),
MSM_PIN_FUNCTION(gsbi5_spi_cs3),
MSM_PIN_FUNCTION(gsbi6),
MSM_PIN_FUNCTION(gsbi6_spi_cs1),
MSM_PIN_FUNCTION(gsbi6_spi_cs2),
MSM_PIN_FUNCTION(gsbi6_spi_cs3),
MSM_PIN_FUNCTION(gsbi7),
MSM_PIN_FUNCTION(gsbi7_spi_cs1),
MSM_PIN_FUNCTION(gsbi7_spi_cs2),
MSM_PIN_FUNCTION(gsbi7_spi_cs3),
MSM_PIN_FUNCTION(gsbi_cam_i2c),
MSM_PIN_FUNCTION(hdmi),
MSM_PIN_FUNCTION(mi2s),
MSM_PIN_FUNCTION(riva_bt),
MSM_PIN_FUNCTION(riva_fm),
MSM_PIN_FUNCTION(riva_wlan),
MSM_PIN_FUNCTION(sdc2),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(slimbus),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(usb2_hsic),
MSM_PIN_FUNCTION(ps_hold),
};
static const struct msm_pingroup apq8064_groups[] = {

502
drivers/pinctrl/qcom/pinctrl-apq8084.c
View File

@ -329,14 +329,14 @@ static const unsigned int sdc2_data_pins[] = { 152 };
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
APQ_MUX_gpio, \
APQ_MUX_##f1, \
APQ_MUX_##f2, \
APQ_MUX_##f3, \
APQ_MUX_##f4, \
APQ_MUX_##f5, \
APQ_MUX_##f6, \
APQ_MUX_##f7 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7 \
}, \
.nfuncs = 8, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -386,128 +386,128 @@ static const unsigned int sdc2_data_pins[] = { 152 };
}
enum apq8084_functions {
APQ_MUX_adsp_ext,
APQ_MUX_audio_ref,
APQ_MUX_blsp_i2c1,
APQ_MUX_blsp_i2c2,
APQ_MUX_blsp_i2c3,
APQ_MUX_blsp_i2c4,
APQ_MUX_blsp_i2c5,
APQ_MUX_blsp_i2c6,
APQ_MUX_blsp_i2c7,
APQ_MUX_blsp_i2c8,
APQ_MUX_blsp_i2c9,
APQ_MUX_blsp_i2c10,
APQ_MUX_blsp_i2c11,
APQ_MUX_blsp_i2c12,
APQ_MUX_blsp_spi1,
APQ_MUX_blsp_spi1_cs1,
APQ_MUX_blsp_spi1_cs2,
APQ_MUX_blsp_spi1_cs3,
APQ_MUX_blsp_spi2,
APQ_MUX_blsp_spi3,
APQ_MUX_blsp_spi3_cs1,
APQ_MUX_blsp_spi3_cs2,
APQ_MUX_blsp_spi3_cs3,
APQ_MUX_blsp_spi4,
APQ_MUX_blsp_spi5,
APQ_MUX_blsp_spi6,
APQ_MUX_blsp_spi7,
APQ_MUX_blsp_spi8,
APQ_MUX_blsp_spi9,
APQ_MUX_blsp_spi10,
APQ_MUX_blsp_spi10_cs1,
APQ_MUX_blsp_spi10_cs2,
APQ_MUX_blsp_spi10_cs3,
APQ_MUX_blsp_spi11,
APQ_MUX_blsp_spi12,
APQ_MUX_blsp_uart1,
APQ_MUX_blsp_uart2,
APQ_MUX_blsp_uart3,
APQ_MUX_blsp_uart4,
APQ_MUX_blsp_uart5,
APQ_MUX_blsp_uart6,
APQ_MUX_blsp_uart7,
APQ_MUX_blsp_uart8,
APQ_MUX_blsp_uart9,
APQ_MUX_blsp_uart10,
APQ_MUX_blsp_uart11,
APQ_MUX_blsp_uart12,
APQ_MUX_blsp_uim1,
APQ_MUX_blsp_uim2,
APQ_MUX_blsp_uim3,
APQ_MUX_blsp_uim4,
APQ_MUX_blsp_uim5,
APQ_MUX_blsp_uim6,
APQ_MUX_blsp_uim7,
APQ_MUX_blsp_uim8,
APQ_MUX_blsp_uim9,
APQ_MUX_blsp_uim10,
APQ_MUX_blsp_uim11,
APQ_MUX_blsp_uim12,
APQ_MUX_cam_mclk0,
APQ_MUX_cam_mclk1,
APQ_MUX_cam_mclk2,
APQ_MUX_cam_mclk3,
APQ_MUX_cci_async,
APQ_MUX_cci_async_in0,
APQ_MUX_cci_i2c0,
APQ_MUX_cci_i2c1,
APQ_MUX_cci_timer0,
APQ_MUX_cci_timer1,
APQ_MUX_cci_timer2,
APQ_MUX_cci_timer3,
APQ_MUX_cci_timer4,
APQ_MUX_edp_hpd,
APQ_MUX_gcc_gp1,
APQ_MUX_gcc_gp2,
APQ_MUX_gcc_gp3,
APQ_MUX_gcc_obt,
APQ_MUX_gcc_vtt,
APQ_MUX_gp_mn,
APQ_MUX_gp_pdm0,
APQ_MUX_gp_pdm1,
APQ_MUX_gp_pdm2,
APQ_MUX_gp0_clk,
APQ_MUX_gp1_clk,
APQ_MUX_gpio,
APQ_MUX_hdmi_cec,
APQ_MUX_hdmi_ddc,
APQ_MUX_hdmi_dtest,
APQ_MUX_hdmi_hpd,
APQ_MUX_hdmi_rcv,
APQ_MUX_hsic,
APQ_MUX_ldo_en,
APQ_MUX_ldo_update,
APQ_MUX_mdp_vsync,
APQ_MUX_pci_e0,
APQ_MUX_pci_e0_n,
APQ_MUX_pci_e0_rst,
APQ_MUX_pci_e1,
APQ_MUX_pci_e1_rst,
APQ_MUX_pci_e1_rst_n,
APQ_MUX_pci_e1_clkreq_n,
APQ_MUX_pri_mi2s,
APQ_MUX_qua_mi2s,
APQ_MUX_sata_act,
APQ_MUX_sata_devsleep,
APQ_MUX_sata_devsleep_n,
APQ_MUX_sd_write,
APQ_MUX_sdc_emmc_mode,
APQ_MUX_sdc3,
APQ_MUX_sdc4,
APQ_MUX_sec_mi2s,
APQ_MUX_slimbus,
APQ_MUX_spdif_tx,
APQ_MUX_spkr_i2s,
APQ_MUX_spkr_i2s_ws,
APQ_MUX_spss_geni,
APQ_MUX_ter_mi2s,
APQ_MUX_tsif1,
APQ_MUX_tsif2,
APQ_MUX_uim,
APQ_MUX_uim_batt_alarm,
APQ_MUX_NA,
msm_mux_adsp_ext,
msm_mux_audio_ref,
msm_mux_blsp_i2c1,
msm_mux_blsp_i2c2,
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
msm_mux_blsp_i2c6,
msm_mux_blsp_i2c7,
msm_mux_blsp_i2c8,
msm_mux_blsp_i2c9,
msm_mux_blsp_i2c10,
msm_mux_blsp_i2c11,
msm_mux_blsp_i2c12,
msm_mux_blsp_spi1,
msm_mux_blsp_spi1_cs1,
msm_mux_blsp_spi1_cs2,
msm_mux_blsp_spi1_cs3,
msm_mux_blsp_spi2,
msm_mux_blsp_spi3,
msm_mux_blsp_spi3_cs1,
msm_mux_blsp_spi3_cs2,
msm_mux_blsp_spi3_cs3,
msm_mux_blsp_spi4,
msm_mux_blsp_spi5,
msm_mux_blsp_spi6,
msm_mux_blsp_spi7,
msm_mux_blsp_spi8,
msm_mux_blsp_spi9,
msm_mux_blsp_spi10,
msm_mux_blsp_spi10_cs1,
msm_mux_blsp_spi10_cs2,
msm_mux_blsp_spi10_cs3,
msm_mux_blsp_spi11,
msm_mux_blsp_spi12,
msm_mux_blsp_uart1,
msm_mux_blsp_uart2,
msm_mux_blsp_uart3,
msm_mux_blsp_uart4,
msm_mux_blsp_uart5,
msm_mux_blsp_uart6,
msm_mux_blsp_uart7,
msm_mux_blsp_uart8,
msm_mux_blsp_uart9,
msm_mux_blsp_uart10,
msm_mux_blsp_uart11,
msm_mux_blsp_uart12,
msm_mux_blsp_uim1,
msm_mux_blsp_uim2,
msm_mux_blsp_uim3,
msm_mux_blsp_uim4,
msm_mux_blsp_uim5,
msm_mux_blsp_uim6,
msm_mux_blsp_uim7,
msm_mux_blsp_uim8,
msm_mux_blsp_uim9,
msm_mux_blsp_uim10,
msm_mux_blsp_uim11,
msm_mux_blsp_uim12,
msm_mux_cam_mclk0,
msm_mux_cam_mclk1,
msm_mux_cam_mclk2,
msm_mux_cam_mclk3,
msm_mux_cci_async,
msm_mux_cci_async_in0,
msm_mux_cci_i2c0,
msm_mux_cci_i2c1,
msm_mux_cci_timer0,
msm_mux_cci_timer1,
msm_mux_cci_timer2,
msm_mux_cci_timer3,
msm_mux_cci_timer4,
msm_mux_edp_hpd,
msm_mux_gcc_gp1,
msm_mux_gcc_gp2,
msm_mux_gcc_gp3,
msm_mux_gcc_obt,
msm_mux_gcc_vtt,
msm_mux_gp_mn,
msm_mux_gp_pdm0,
msm_mux_gp_pdm1,
msm_mux_gp_pdm2,
msm_mux_gp0_clk,
msm_mux_gp1_clk,
msm_mux_gpio,
msm_mux_hdmi_cec,
msm_mux_hdmi_ddc,
msm_mux_hdmi_dtest,
msm_mux_hdmi_hpd,
msm_mux_hdmi_rcv,
msm_mux_hsic,
msm_mux_ldo_en,
msm_mux_ldo_update,
msm_mux_mdp_vsync,
msm_mux_pci_e0,
msm_mux_pci_e0_n,
msm_mux_pci_e0_rst,
msm_mux_pci_e1,
msm_mux_pci_e1_rst,
msm_mux_pci_e1_rst_n,
msm_mux_pci_e1_clkreq_n,
msm_mux_pri_mi2s,
msm_mux_qua_mi2s,
msm_mux_sata_act,
msm_mux_sata_devsleep,
msm_mux_sata_devsleep_n,
msm_mux_sd_write,
msm_mux_sdc_emmc_mode,
msm_mux_sdc3,
msm_mux_sdc4,
msm_mux_sec_mi2s,
msm_mux_slimbus,
msm_mux_spdif_tx,
msm_mux_spkr_i2s,
msm_mux_spkr_i2s_ws,
msm_mux_spss_geni,
msm_mux_ter_mi2s,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_uim,
msm_mux_uim_batt_alarm,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -897,127 +897,127 @@ static const char * const uim_batt_alarm_groups[] = {
"gpio102"
};
static const struct pinfunction apq8084_functions[] = {
APQ_PIN_FUNCTION(adsp_ext),
APQ_PIN_FUNCTION(audio_ref),
APQ_PIN_FUNCTION(blsp_i2c1),
APQ_PIN_FUNCTION(blsp_i2c2),
APQ_PIN_FUNCTION(blsp_i2c3),
APQ_PIN_FUNCTION(blsp_i2c4),
APQ_PIN_FUNCTION(blsp_i2c5),
APQ_PIN_FUNCTION(blsp_i2c6),
APQ_PIN_FUNCTION(blsp_i2c7),
APQ_PIN_FUNCTION(blsp_i2c8),
APQ_PIN_FUNCTION(blsp_i2c9),
APQ_PIN_FUNCTION(blsp_i2c10),
APQ_PIN_FUNCTION(blsp_i2c11),
APQ_PIN_FUNCTION(blsp_i2c12),
APQ_PIN_FUNCTION(blsp_spi1),
APQ_PIN_FUNCTION(blsp_spi1_cs1),
APQ_PIN_FUNCTION(blsp_spi1_cs2),
APQ_PIN_FUNCTION(blsp_spi1_cs3),
APQ_PIN_FUNCTION(blsp_spi2),
APQ_PIN_FUNCTION(blsp_spi3),
APQ_PIN_FUNCTION(blsp_spi3_cs1),
APQ_PIN_FUNCTION(blsp_spi3_cs2),
APQ_PIN_FUNCTION(blsp_spi3_cs3),
APQ_PIN_FUNCTION(blsp_spi4),
APQ_PIN_FUNCTION(blsp_spi5),
APQ_PIN_FUNCTION(blsp_spi6),
APQ_PIN_FUNCTION(blsp_spi7),
APQ_PIN_FUNCTION(blsp_spi8),
APQ_PIN_FUNCTION(blsp_spi9),
APQ_PIN_FUNCTION(blsp_spi10),
APQ_PIN_FUNCTION(blsp_spi10_cs1),
APQ_PIN_FUNCTION(blsp_spi10_cs2),
APQ_PIN_FUNCTION(blsp_spi10_cs3),
APQ_PIN_FUNCTION(blsp_spi11),
APQ_PIN_FUNCTION(blsp_spi12),
APQ_PIN_FUNCTION(blsp_uart1),
APQ_PIN_FUNCTION(blsp_uart2),
APQ_PIN_FUNCTION(blsp_uart3),
APQ_PIN_FUNCTION(blsp_uart4),
APQ_PIN_FUNCTION(blsp_uart5),
APQ_PIN_FUNCTION(blsp_uart6),
APQ_PIN_FUNCTION(blsp_uart7),
APQ_PIN_FUNCTION(blsp_uart8),
APQ_PIN_FUNCTION(blsp_uart9),
APQ_PIN_FUNCTION(blsp_uart10),
APQ_PIN_FUNCTION(blsp_uart11),
APQ_PIN_FUNCTION(blsp_uart12),
APQ_PIN_FUNCTION(blsp_uim1),
APQ_PIN_FUNCTION(blsp_uim2),
APQ_PIN_FUNCTION(blsp_uim3),
APQ_PIN_FUNCTION(blsp_uim4),
APQ_PIN_FUNCTION(blsp_uim5),
APQ_PIN_FUNCTION(blsp_uim6),
APQ_PIN_FUNCTION(blsp_uim7),
APQ_PIN_FUNCTION(blsp_uim8),
APQ_PIN_FUNCTION(blsp_uim9),
APQ_PIN_FUNCTION(blsp_uim10),
APQ_PIN_FUNCTION(blsp_uim11),
APQ_PIN_FUNCTION(blsp_uim12),
APQ_PIN_FUNCTION(cam_mclk0),
APQ_PIN_FUNCTION(cam_mclk1),
APQ_PIN_FUNCTION(cam_mclk2),
APQ_PIN_FUNCTION(cam_mclk3),
APQ_PIN_FUNCTION(cci_async),
APQ_PIN_FUNCTION(cci_async_in0),
APQ_PIN_FUNCTION(cci_i2c0),
APQ_PIN_FUNCTION(cci_i2c1),
APQ_PIN_FUNCTION(cci_timer0),
APQ_PIN_FUNCTION(cci_timer1),
APQ_PIN_FUNCTION(cci_timer2),
APQ_PIN_FUNCTION(cci_timer3),
APQ_PIN_FUNCTION(cci_timer4),
APQ_PIN_FUNCTION(edp_hpd),
APQ_PIN_FUNCTION(gcc_gp1),
APQ_PIN_FUNCTION(gcc_gp2),
APQ_PIN_FUNCTION(gcc_gp3),
APQ_PIN_FUNCTION(gcc_obt),
APQ_PIN_FUNCTION(gcc_vtt),
APQ_PIN_FUNCTION(gp_mn),
APQ_PIN_FUNCTION(gp_pdm0),
APQ_PIN_FUNCTION(gp_pdm1),
APQ_PIN_FUNCTION(gp_pdm2),
APQ_PIN_FUNCTION(gp0_clk),
APQ_PIN_FUNCTION(gp1_clk),
APQ_PIN_FUNCTION(gpio),
APQ_PIN_FUNCTION(hdmi_cec),
APQ_PIN_FUNCTION(hdmi_ddc),
APQ_PIN_FUNCTION(hdmi_dtest),
APQ_PIN_FUNCTION(hdmi_hpd),
APQ_PIN_FUNCTION(hdmi_rcv),
APQ_PIN_FUNCTION(hsic),
APQ_PIN_FUNCTION(ldo_en),
APQ_PIN_FUNCTION(ldo_update),
APQ_PIN_FUNCTION(mdp_vsync),
APQ_PIN_FUNCTION(pci_e0),
APQ_PIN_FUNCTION(pci_e0_n),
APQ_PIN_FUNCTION(pci_e0_rst),
APQ_PIN_FUNCTION(pci_e1),
APQ_PIN_FUNCTION(pci_e1_rst),
APQ_PIN_FUNCTION(pci_e1_rst_n),
APQ_PIN_FUNCTION(pci_e1_clkreq_n),
APQ_PIN_FUNCTION(pri_mi2s),
APQ_PIN_FUNCTION(qua_mi2s),
APQ_PIN_FUNCTION(sata_act),
APQ_PIN_FUNCTION(sata_devsleep),
APQ_PIN_FUNCTION(sata_devsleep_n),
APQ_PIN_FUNCTION(sd_write),
APQ_PIN_FUNCTION(sdc_emmc_mode),
APQ_PIN_FUNCTION(sdc3),
APQ_PIN_FUNCTION(sdc4),
APQ_PIN_FUNCTION(sec_mi2s),
APQ_PIN_FUNCTION(slimbus),
APQ_PIN_FUNCTION(spdif_tx),
APQ_PIN_FUNCTION(spkr_i2s),
APQ_PIN_FUNCTION(spkr_i2s_ws),
APQ_PIN_FUNCTION(spss_geni),
APQ_PIN_FUNCTION(ter_mi2s),
APQ_PIN_FUNCTION(tsif1),
APQ_PIN_FUNCTION(tsif2),
APQ_PIN_FUNCTION(uim),
APQ_PIN_FUNCTION(uim_batt_alarm),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(blsp_i2c9),
MSM_PIN_FUNCTION(blsp_i2c10),
MSM_PIN_FUNCTION(blsp_i2c11),
MSM_PIN_FUNCTION(blsp_i2c12),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi1_cs1),
MSM_PIN_FUNCTION(blsp_spi1_cs2),
MSM_PIN_FUNCTION(blsp_spi1_cs3),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi3_cs1),
MSM_PIN_FUNCTION(blsp_spi3_cs2),
MSM_PIN_FUNCTION(blsp_spi3_cs3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(blsp_spi9),
MSM_PIN_FUNCTION(blsp_spi10),
MSM_PIN_FUNCTION(blsp_spi10_cs1),
MSM_PIN_FUNCTION(blsp_spi10_cs2),
MSM_PIN_FUNCTION(blsp_spi10_cs3),
MSM_PIN_FUNCTION(blsp_spi11),
MSM_PIN_FUNCTION(blsp_spi12),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(blsp_uart7),
MSM_PIN_FUNCTION(blsp_uart8),
MSM_PIN_FUNCTION(blsp_uart9),
MSM_PIN_FUNCTION(blsp_uart10),
MSM_PIN_FUNCTION(blsp_uart11),
MSM_PIN_FUNCTION(blsp_uart12),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(blsp_uim3),
MSM_PIN_FUNCTION(blsp_uim4),
MSM_PIN_FUNCTION(blsp_uim5),
MSM_PIN_FUNCTION(blsp_uim6),
MSM_PIN_FUNCTION(blsp_uim7),
MSM_PIN_FUNCTION(blsp_uim8),
MSM_PIN_FUNCTION(blsp_uim9),
MSM_PIN_FUNCTION(blsp_uim10),
MSM_PIN_FUNCTION(blsp_uim11),
MSM_PIN_FUNCTION(blsp_uim12),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cam_mclk2),
MSM_PIN_FUNCTION(cam_mclk3),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_async_in0),
MSM_PIN_FUNCTION(cci_i2c0),
MSM_PIN_FUNCTION(cci_i2c1),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(edp_hpd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gcc_obt),
MSM_PIN_FUNCTION(gcc_vtt),
MSM_PIN_FUNCTION(gp_mn),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gp0_clk),
MSM_PIN_FUNCTION(gp1_clk),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(hdmi_cec),
MSM_PIN_FUNCTION(hdmi_ddc),
MSM_PIN_FUNCTION(hdmi_dtest),
MSM_PIN_FUNCTION(hdmi_hpd),
MSM_PIN_FUNCTION(hdmi_rcv),
MSM_PIN_FUNCTION(hsic),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e0_n),
MSM_PIN_FUNCTION(pci_e0_rst),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(pci_e1_rst),
MSM_PIN_FUNCTION(pci_e1_rst_n),
MSM_PIN_FUNCTION(pci_e1_clkreq_n),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(sata_act),
MSM_PIN_FUNCTION(sata_devsleep),
MSM_PIN_FUNCTION(sata_devsleep_n),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc_emmc_mode),
MSM_PIN_FUNCTION(sdc3),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(slimbus),
MSM_PIN_FUNCTION(spdif_tx),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(spkr_i2s_ws),
MSM_PIN_FUNCTION(spss_geni),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(uim),
MSM_PIN_FUNCTION(uim_batt_alarm),
};
static const struct msm_pingroup apq8084_groups[] = {

244
drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c Normal file
View File

@ -0,0 +1,244 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include "pinctrl-lpass-lpi.h"
enum lpass_lpi_functions {
LPI_MUX_dmic1_clk,
LPI_MUX_dmic1_data,
LPI_MUX_dmic2_clk,
LPI_MUX_dmic2_data,
LPI_MUX_dmic3_clk,
LPI_MUX_dmic3_data,
LPI_MUX_dmic4_clk,
LPI_MUX_dmic4_data,
LPI_MUX_ext_mclk1_a,
LPI_MUX_ext_mclk1_b,
LPI_MUX_ext_mclk1_c,
LPI_MUX_ext_mclk1_d,
LPI_MUX_ext_mclk1_e,
LPI_MUX_i2s0_clk,
LPI_MUX_i2s0_data,
LPI_MUX_i2s0_ws,
LPI_MUX_i2s1_clk,
LPI_MUX_i2s1_data,
LPI_MUX_i2s1_ws,
LPI_MUX_i2s2_clk,
LPI_MUX_i2s2_data,
LPI_MUX_i2s2_ws,
LPI_MUX_i2s3_clk,
LPI_MUX_i2s3_data,
LPI_MUX_i2s3_ws,
LPI_MUX_lpass_lpi_dbg_clk,
LPI_MUX_qca_swr_clk,
LPI_MUX_qca_swr_data,
LPI_MUX_slimbus_clk,
LPI_MUX_slimbus_data,
LPI_MUX_swr_rx_clk,
LPI_MUX_swr_rx_data,
LPI_MUX_swr_tx_clk,
LPI_MUX_swr_tx_clk1,
LPI_MUX_swr_tx_data,
LPI_MUX_va_i2s0_clk,
LPI_MUX_va_i2s0_data,
LPI_MUX_va_i2s0_ws,
LPI_MUX_wsa2_swr_clk,
LPI_MUX_wsa2_swr_data,
LPI_MUX_wsa_swr_clk,
LPI_MUX_wsa_swr_data,
LPI_MUX_gpio,
LPI_MUX__,
};
static const struct pinctrl_pin_desc hawi_lpi_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22",
};
static const char * const swr_tx_clk_groups[] = { "gpio0" };
static const char * const i2s0_clk_groups[] = { "gpio0" };
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
static const char * const i2s0_ws_groups[] = { "gpio1" };
static const char * const swr_rx_clk_groups[] = { "gpio3" };
static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
static const char * const ext_mclk1_c_groups[] = { "gpio5" };
static const char * const dmic1_clk_groups[] = { "gpio6" };
static const char * const va_i2s0_clk_groups[] = { "gpio6" };
static const char * const dmic1_data_groups[] = { "gpio7" };
static const char * const va_i2s0_ws_groups[] = { "gpio7" };
static const char * const dmic2_clk_groups[] = { "gpio8" };
static const char * const va_i2s0_data_groups[] = { "gpio8", "gpio9" };
static const char * const dmic2_data_groups[] = { "gpio9" };
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
static const char * const i2s1_clk_groups[] = { "gpio10" };
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
static const char * const i2s1_ws_groups[] = { "gpio11" };
static const char * const wsa_swr_data_groups[] = { "gpio11", "gpio21" };
static const char * const dmic3_clk_groups[] = { "gpio12" };
static const char * const i2s3_clk_groups[] = { "gpio12" };
static const char * const dmic3_data_groups[] = { "gpio13" };
static const char * const i2s3_ws_groups[] = { "gpio13" };
static const char * const ext_mclk1_a_groups[] = { "gpio13" };
static const char * const lpass_lpi_dbg_clk_groups[] = { "gpio13" };
static const char * const swr_tx_clk1_groups[] = { "gpio14" };
static const char * const ext_mclk1_d_groups[] = { "gpio14" };
static const char * const i2s1_data_groups[] = { "gpio15", "gpio16", "gpio21", "gpio22" };
static const char * const wsa2_swr_clk_groups[] = { "gpio15" };
static const char * const wsa2_swr_data_groups[] = { "gpio16", "gpio22" };
static const char * const dmic4_clk_groups[] = { "gpio17" };
static const char * const i2s3_data_groups[] = { "gpio17", "gpio18" };
static const char * const dmic4_data_groups[] = { "gpio18" };
static const char * const i2s2_clk_groups[] = { "gpio19" };
static const char * const slimbus_clk_groups[] = { "gpio19" };
static const char * const qca_swr_clk_groups[] = { "gpio19" };
static const char * const i2s2_ws_groups[] = { "gpio20" };
static const char * const slimbus_data_groups[] = { "gpio20" };
static const char * const qca_swr_data_groups[] = { "gpio20" };
static const char * const i2s2_data_groups[] = { "gpio21", "gpio22" };
static const char * const ext_mclk1_e_groups[] = { "gpio22" };
static const struct lpi_pingroup hawi_groups[] = {
LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _),
LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _),
LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _),
LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _),
LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _),
LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _),
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, va_i2s0_clk, _, _),
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, va_i2s0_ws, _, _),
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, va_i2s0_data, _, _),
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, va_i2s0_data, ext_mclk1_b, _),
LPI_PINGROUP(10, 11, i2s1_clk, wsa_swr_clk, _, _),
LPI_PINGROUP(11, 11, i2s1_ws, wsa_swr_data, _, _),
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _),
LPI_PINGROUP6(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _, lpass_lpi_dbg_clk),
LPI_PINGROUP(14, 11, swr_tx_data, swr_tx_clk1, ext_mclk1_d, _),
LPI_PINGROUP(15, 11, i2s1_data, wsa2_swr_clk, _, _),
LPI_PINGROUP(16, 11, i2s1_data, wsa2_swr_data, _, _),
LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _),
LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _),
LPI_PINGROUP(19, LPI_NO_SLEW, i2s2_clk, slimbus_clk, qca_swr_clk, _),
LPI_PINGROUP(20, LPI_NO_SLEW, i2s2_ws, slimbus_data, qca_swr_data, _),
LPI_PINGROUP(21, 11, i2s2_data, _, wsa_swr_data, i2s1_data),
LPI_PINGROUP6(22, 11, i2s2_data, ext_mclk1_e, _, i2s1_data, wsa2_swr_data),
};
static const struct lpi_function hawi_functions[] = {
LPI_FUNCTION(gpio),
LPI_FUNCTION(dmic1_clk),
LPI_FUNCTION(dmic1_data),
LPI_FUNCTION(dmic2_clk),
LPI_FUNCTION(dmic2_data),
LPI_FUNCTION(dmic3_clk),
LPI_FUNCTION(dmic3_data),
LPI_FUNCTION(dmic4_clk),
LPI_FUNCTION(dmic4_data),
LPI_FUNCTION(ext_mclk1_a),
LPI_FUNCTION(ext_mclk1_b),
LPI_FUNCTION(ext_mclk1_c),
LPI_FUNCTION(ext_mclk1_d),
LPI_FUNCTION(ext_mclk1_e),
LPI_FUNCTION(i2s0_clk),
LPI_FUNCTION(i2s0_data),
LPI_FUNCTION(i2s0_ws),
LPI_FUNCTION(i2s1_clk),
LPI_FUNCTION(i2s1_data),
LPI_FUNCTION(i2s1_ws),
LPI_FUNCTION(i2s2_clk),
LPI_FUNCTION(i2s2_data),
LPI_FUNCTION(i2s2_ws),
LPI_FUNCTION(i2s3_clk),
LPI_FUNCTION(i2s3_data),
LPI_FUNCTION(i2s3_ws),
LPI_FUNCTION(lpass_lpi_dbg_clk),
LPI_FUNCTION(qca_swr_clk),
LPI_FUNCTION(qca_swr_data),
LPI_FUNCTION(slimbus_clk),
LPI_FUNCTION(slimbus_data),
LPI_FUNCTION(swr_rx_clk),
LPI_FUNCTION(swr_rx_data),
LPI_FUNCTION(swr_tx_clk),
LPI_FUNCTION(swr_tx_clk1),
LPI_FUNCTION(swr_tx_data),
LPI_FUNCTION(va_i2s0_clk),
LPI_FUNCTION(va_i2s0_data),
LPI_FUNCTION(va_i2s0_ws),
LPI_FUNCTION(wsa2_swr_clk),
LPI_FUNCTION(wsa2_swr_data),
LPI_FUNCTION(wsa_swr_clk),
LPI_FUNCTION(wsa_swr_data),
};
static const struct lpi_pinctrl_variant_data hawi_lpi_data = {
.pins = hawi_lpi_pins,
.npins = ARRAY_SIZE(hawi_lpi_pins),
.groups = hawi_groups,
.ngroups = ARRAY_SIZE(hawi_groups),
.functions = hawi_functions,
.nfunctions = ARRAY_SIZE(hawi_functions),
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
{
.compatible = "qcom,hawi-lpass-lpi-pinctrl",
.data = &hawi_lpi_data,
},
{ }
};
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
static const struct dev_pm_ops lpi_pinctrl_pm_ops = {
RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver lpi_pinctrl_driver = {
.driver = {
.name = "qcom-hawi-lpass-lpi-pinctrl",
.of_match_table = lpi_pinctrl_of_match,
.pm = pm_ptr(&lpi_pinctrl_pm_ops),
},
.probe = lpi_pinctrl_probe,
.remove = lpi_pinctrl_remove,
};
module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("Qualcomm Hawi LPI GPIO pin control driver");
MODULE_LICENSE("GPL");

208
drivers/pinctrl/qcom/pinctrl-ipq4019.c
View File

@ -221,21 +221,21 @@ DECLARE_QCA_GPIO_PINS(99);
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
qca_mux_gpio, /* gpio mode */ \
qca_mux_##f1, \
qca_mux_##f2, \
qca_mux_##f3, \
qca_mux_##f4, \
qca_mux_##f5, \
qca_mux_##f6, \
qca_mux_##f7, \
qca_mux_##f8, \
qca_mux_##f9, \
qca_mux_##f10, \
qca_mux_##f11, \
qca_mux_##f12, \
qca_mux_##f13, \
qca_mux_##f14 \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
msm_mux_##f11, \
msm_mux_##f12, \
msm_mux_##f13, \
msm_mux_##f14 \
}, \
.nfuncs = 15, \
.ctl_reg = 0x0 + 0x1000 * id, \
@ -260,51 +260,51 @@ DECLARE_QCA_GPIO_PINS(99);
enum ipq4019_functions {
qca_mux_gpio,
qca_mux_aud_pin,
qca_mux_audio_pwm,
qca_mux_blsp_i2c0,
qca_mux_blsp_i2c1,
qca_mux_blsp_spi0,
qca_mux_blsp_spi1,
qca_mux_blsp_uart0,
qca_mux_blsp_uart1,
qca_mux_chip_rst,
qca_mux_i2s_rx,
qca_mux_i2s_spdif_in,
qca_mux_i2s_spdif_out,
qca_mux_i2s_td,
qca_mux_i2s_tx,
qca_mux_jtag,
qca_mux_led0,
qca_mux_led1,
qca_mux_led2,
qca_mux_led3,
qca_mux_led4,
qca_mux_led5,
qca_mux_led6,
qca_mux_led7,
qca_mux_led8,
qca_mux_led9,
qca_mux_led10,
qca_mux_led11,
qca_mux_mdc,
qca_mux_mdio,
qca_mux_pcie,
qca_mux_pmu,
qca_mux_prng_rosc,
qca_mux_qpic,
qca_mux_rgmii,
qca_mux_rmii,
qca_mux_sdio,
qca_mux_smart0,
qca_mux_smart1,
qca_mux_smart2,
qca_mux_smart3,
qca_mux_tm,
qca_mux_wifi0,
qca_mux_wifi1,
qca_mux_NA,
msm_mux_gpio,
msm_mux_aud_pin,
msm_mux_audio_pwm,
msm_mux_blsp_i2c0,
msm_mux_blsp_i2c1,
msm_mux_blsp_spi0,
msm_mux_blsp_spi1,
msm_mux_blsp_uart0,
msm_mux_blsp_uart1,
msm_mux_chip_rst,
msm_mux_i2s_rx,
msm_mux_i2s_spdif_in,
msm_mux_i2s_spdif_out,
msm_mux_i2s_td,
msm_mux_i2s_tx,
msm_mux_jtag,
msm_mux_led0,
msm_mux_led1,
msm_mux_led2,
msm_mux_led3,
msm_mux_led4,
msm_mux_led5,
msm_mux_led6,
msm_mux_led7,
msm_mux_led8,
msm_mux_led9,
msm_mux_led10,
msm_mux_led11,
msm_mux_mdc,
msm_mux_mdio,
msm_mux_pcie,
msm_mux_pmu,
msm_mux_prng_rosc,
msm_mux_qpic,
msm_mux_rgmii,
msm_mux_rmii,
msm_mux_sdio,
msm_mux_smart0,
msm_mux_smart1,
msm_mux_smart2,
msm_mux_smart3,
msm_mux_tm,
msm_mux_wifi0,
msm_mux_wifi1,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -470,50 +470,50 @@ static const char * const wifi1_groups[] = {
};
static const struct pinfunction ipq4019_functions[] = {
QCA_PIN_FUNCTION(aud_pin),
QCA_PIN_FUNCTION(audio_pwm),
QCA_PIN_FUNCTION(blsp_i2c0),
QCA_PIN_FUNCTION(blsp_i2c1),
QCA_PIN_FUNCTION(blsp_spi0),
QCA_PIN_FUNCTION(blsp_spi1),
QCA_PIN_FUNCTION(blsp_uart0),
QCA_PIN_FUNCTION(blsp_uart1),
QCA_PIN_FUNCTION(chip_rst),
QCA_GPIO_PIN_FUNCTION(gpio),
QCA_PIN_FUNCTION(i2s_rx),
QCA_PIN_FUNCTION(i2s_spdif_in),
QCA_PIN_FUNCTION(i2s_spdif_out),
QCA_PIN_FUNCTION(i2s_td),
QCA_PIN_FUNCTION(i2s_tx),
QCA_PIN_FUNCTION(jtag),
QCA_PIN_FUNCTION(led0),
QCA_PIN_FUNCTION(led1),
QCA_PIN_FUNCTION(led2),
QCA_PIN_FUNCTION(led3),
QCA_PIN_FUNCTION(led4),
QCA_PIN_FUNCTION(led5),
QCA_PIN_FUNCTION(led6),
QCA_PIN_FUNCTION(led7),
QCA_PIN_FUNCTION(led8),
QCA_PIN_FUNCTION(led9),
QCA_PIN_FUNCTION(led10),
QCA_PIN_FUNCTION(led11),
QCA_PIN_FUNCTION(mdc),
QCA_PIN_FUNCTION(mdio),
QCA_PIN_FUNCTION(pcie),
QCA_PIN_FUNCTION(pmu),
QCA_PIN_FUNCTION(prng_rosc),
QCA_PIN_FUNCTION(qpic),
QCA_PIN_FUNCTION(rgmii),
QCA_PIN_FUNCTION(rmii),
QCA_PIN_FUNCTION(sdio),
QCA_PIN_FUNCTION(smart0),
QCA_PIN_FUNCTION(smart1),
QCA_PIN_FUNCTION(smart2),
QCA_PIN_FUNCTION(smart3),
QCA_PIN_FUNCTION(tm),
QCA_PIN_FUNCTION(wifi0),
QCA_PIN_FUNCTION(wifi1),
MSM_PIN_FUNCTION(aud_pin),
MSM_PIN_FUNCTION(audio_pwm),
MSM_PIN_FUNCTION(blsp_i2c0),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_spi0),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_uart0),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(chip_rst),
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(i2s_rx),
MSM_PIN_FUNCTION(i2s_spdif_in),
MSM_PIN_FUNCTION(i2s_spdif_out),
MSM_PIN_FUNCTION(i2s_td),
MSM_PIN_FUNCTION(i2s_tx),
MSM_PIN_FUNCTION(jtag),
MSM_PIN_FUNCTION(led0),
MSM_PIN_FUNCTION(led1),
MSM_PIN_FUNCTION(led2),
MSM_PIN_FUNCTION(led3),
MSM_PIN_FUNCTION(led4),
MSM_PIN_FUNCTION(led5),
MSM_PIN_FUNCTION(led6),
MSM_PIN_FUNCTION(led7),
MSM_PIN_FUNCTION(led8),
MSM_PIN_FUNCTION(led9),
MSM_PIN_FUNCTION(led10),
MSM_PIN_FUNCTION(led11),
MSM_PIN_FUNCTION(mdc),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(pcie),
MSM_PIN_FUNCTION(pmu),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qpic),
MSM_PIN_FUNCTION(rgmii),
MSM_PIN_FUNCTION(rmii),
MSM_PIN_FUNCTION(sdio),
MSM_PIN_FUNCTION(smart0),
MSM_PIN_FUNCTION(smart1),
MSM_PIN_FUNCTION(smart2),
MSM_PIN_FUNCTION(smart3),
MSM_PIN_FUNCTION(tm),
MSM_PIN_FUNCTION(wifi0),
MSM_PIN_FUNCTION(wifi1),
};
static const struct msm_pingroup ipq4019_groups[] = {

208
drivers/pinctrl/qcom/pinctrl-ipq8064.c
View File

@ -166,17 +166,17 @@ static const unsigned int sdc3_data_pins[] = { 71 };
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
IPQ_MUX_gpio, \
IPQ_MUX_##f1, \
IPQ_MUX_##f2, \
IPQ_MUX_##f3, \
IPQ_MUX_##f4, \
IPQ_MUX_##f5, \
IPQ_MUX_##f6, \
IPQ_MUX_##f7, \
IPQ_MUX_##f8, \
IPQ_MUX_##f9, \
IPQ_MUX_##f10, \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
}, \
.nfuncs = 11, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -228,53 +228,53 @@ static const unsigned int sdc3_data_pins[] = { 71 };
}
enum ipq8064_functions {
IPQ_MUX_gpio,
IPQ_MUX_mdio,
IPQ_MUX_mi2s,
IPQ_MUX_pdm,
IPQ_MUX_ssbi,
IPQ_MUX_spmi,
IPQ_MUX_audio_pcm,
IPQ_MUX_gsbi1,
IPQ_MUX_gsbi2,
IPQ_MUX_gsbi4,
IPQ_MUX_gsbi5,
IPQ_MUX_gsbi5_spi_cs1,
IPQ_MUX_gsbi5_spi_cs2,
IPQ_MUX_gsbi5_spi_cs3,
IPQ_MUX_gsbi6,
IPQ_MUX_gsbi7,
IPQ_MUX_nss_spi,
IPQ_MUX_sdc1,
IPQ_MUX_spdif,
IPQ_MUX_nand,
IPQ_MUX_tsif1,
IPQ_MUX_tsif2,
IPQ_MUX_usb_fs_n,
IPQ_MUX_usb_fs,
IPQ_MUX_usb2_hsic,
IPQ_MUX_rgmii2,
IPQ_MUX_sata,
IPQ_MUX_pcie1_rst,
IPQ_MUX_pcie1_prsnt,
IPQ_MUX_pcie1_pwrflt,
IPQ_MUX_pcie1_pwren_n,
IPQ_MUX_pcie1_pwren,
IPQ_MUX_pcie1_clk_req,
IPQ_MUX_pcie2_rst,
IPQ_MUX_pcie2_prsnt,
IPQ_MUX_pcie2_pwrflt,
IPQ_MUX_pcie2_pwren_n,
IPQ_MUX_pcie2_pwren,
IPQ_MUX_pcie2_clk_req,
IPQ_MUX_pcie3_rst,
IPQ_MUX_pcie3_prsnt,
IPQ_MUX_pcie3_pwrflt,
IPQ_MUX_pcie3_pwren_n,
IPQ_MUX_pcie3_pwren,
IPQ_MUX_pcie3_clk_req,
IPQ_MUX_ps_hold,
IPQ_MUX_NA,
msm_mux_gpio,
msm_mux_mdio,
msm_mux_mi2s,
msm_mux_pdm,
msm_mux_ssbi,
msm_mux_spmi,
msm_mux_audio_pcm,
msm_mux_gsbi1,
msm_mux_gsbi2,
msm_mux_gsbi4,
msm_mux_gsbi5,
msm_mux_gsbi5_spi_cs1,
msm_mux_gsbi5_spi_cs2,
msm_mux_gsbi5_spi_cs3,
msm_mux_gsbi6,
msm_mux_gsbi7,
msm_mux_nss_spi,
msm_mux_sdc1,
msm_mux_spdif,
msm_mux_nand,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_usb_fs_n,
msm_mux_usb_fs,
msm_mux_usb2_hsic,
msm_mux_rgmii2,
msm_mux_sata,
msm_mux_pcie1_rst,
msm_mux_pcie1_prsnt,
msm_mux_pcie1_pwrflt,
msm_mux_pcie1_pwren_n,
msm_mux_pcie1_pwren,
msm_mux_pcie1_clk_req,
msm_mux_pcie2_rst,
msm_mux_pcie2_prsnt,
msm_mux_pcie2_pwrflt,
msm_mux_pcie2_pwren_n,
msm_mux_pcie2_pwren,
msm_mux_pcie2_clk_req,
msm_mux_pcie3_rst,
msm_mux_pcie3_prsnt,
msm_mux_pcie3_pwrflt,
msm_mux_pcie3_pwren_n,
msm_mux_pcie3_pwren,
msm_mux_pcie3_clk_req,
msm_mux_ps_hold,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -480,52 +480,52 @@ static const char * const ps_hold_groups[] = {
};
static const struct pinfunction ipq8064_functions[] = {
IPQ_GPIO_PIN_FUNCTION(gpio),
IPQ_PIN_FUNCTION(mdio),
IPQ_PIN_FUNCTION(ssbi),
IPQ_PIN_FUNCTION(spmi),
IPQ_PIN_FUNCTION(mi2s),
IPQ_PIN_FUNCTION(pdm),
IPQ_PIN_FUNCTION(audio_pcm),
IPQ_PIN_FUNCTION(gsbi1),
IPQ_PIN_FUNCTION(gsbi2),
IPQ_PIN_FUNCTION(gsbi4),
IPQ_PIN_FUNCTION(gsbi5),
IPQ_PIN_FUNCTION(gsbi5_spi_cs1),
IPQ_PIN_FUNCTION(gsbi5_spi_cs2),
IPQ_PIN_FUNCTION(gsbi5_spi_cs3),
IPQ_PIN_FUNCTION(gsbi6),
IPQ_PIN_FUNCTION(gsbi7),
IPQ_PIN_FUNCTION(nss_spi),
IPQ_PIN_FUNCTION(sdc1),
IPQ_PIN_FUNCTION(spdif),
IPQ_PIN_FUNCTION(nand),
IPQ_PIN_FUNCTION(tsif1),
IPQ_PIN_FUNCTION(tsif2),
IPQ_PIN_FUNCTION(usb_fs_n),
IPQ_PIN_FUNCTION(usb_fs),
IPQ_PIN_FUNCTION(usb2_hsic),
IPQ_PIN_FUNCTION(rgmii2),
IPQ_PIN_FUNCTION(sata),
IPQ_GPIO_PIN_FUNCTION(pcie1_rst),
IPQ_PIN_FUNCTION(pcie1_prsnt),
IPQ_PIN_FUNCTION(pcie1_pwren_n),
IPQ_PIN_FUNCTION(pcie1_pwren),
IPQ_PIN_FUNCTION(pcie1_pwrflt),
IPQ_PIN_FUNCTION(pcie1_clk_req),
IPQ_GPIO_PIN_FUNCTION(pcie2_rst),
IPQ_PIN_FUNCTION(pcie2_prsnt),
IPQ_PIN_FUNCTION(pcie2_pwren_n),
IPQ_PIN_FUNCTION(pcie2_pwren),
IPQ_PIN_FUNCTION(pcie2_pwrflt),
IPQ_PIN_FUNCTION(pcie2_clk_req),
IPQ_GPIO_PIN_FUNCTION(pcie3_rst),
IPQ_PIN_FUNCTION(pcie3_prsnt),
IPQ_PIN_FUNCTION(pcie3_pwren_n),
IPQ_PIN_FUNCTION(pcie3_pwren),
IPQ_PIN_FUNCTION(pcie3_pwrflt),
IPQ_PIN_FUNCTION(pcie3_clk_req),
IPQ_PIN_FUNCTION(ps_hold),
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(ssbi),
MSM_PIN_FUNCTION(spmi),
MSM_PIN_FUNCTION(mi2s),
MSM_PIN_FUNCTION(pdm),
MSM_PIN_FUNCTION(audio_pcm),
MSM_PIN_FUNCTION(gsbi1),
MSM_PIN_FUNCTION(gsbi2),
MSM_PIN_FUNCTION(gsbi4),
MSM_PIN_FUNCTION(gsbi5),
MSM_PIN_FUNCTION(gsbi5_spi_cs1),
MSM_PIN_FUNCTION(gsbi5_spi_cs2),
MSM_PIN_FUNCTION(gsbi5_spi_cs3),
MSM_PIN_FUNCTION(gsbi6),
MSM_PIN_FUNCTION(gsbi7),
MSM_PIN_FUNCTION(nss_spi),
MSM_PIN_FUNCTION(sdc1),
MSM_PIN_FUNCTION(spdif),
MSM_PIN_FUNCTION(nand),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(usb_fs_n),
MSM_PIN_FUNCTION(usb_fs),
MSM_PIN_FUNCTION(usb2_hsic),
MSM_PIN_FUNCTION(rgmii2),
MSM_PIN_FUNCTION(sata),
MSM_GPIO_PIN_FUNCTION(pcie1_rst),
MSM_PIN_FUNCTION(pcie1_prsnt),
MSM_PIN_FUNCTION(pcie1_pwren_n),
MSM_PIN_FUNCTION(pcie1_pwren),
MSM_PIN_FUNCTION(pcie1_pwrflt),
MSM_PIN_FUNCTION(pcie1_clk_req),
MSM_GPIO_PIN_FUNCTION(pcie2_rst),
MSM_PIN_FUNCTION(pcie2_prsnt),
MSM_PIN_FUNCTION(pcie2_pwren_n),
MSM_PIN_FUNCTION(pcie2_pwren),
MSM_PIN_FUNCTION(pcie2_pwrflt),
MSM_PIN_FUNCTION(pcie2_clk_req),
MSM_GPIO_PIN_FUNCTION(pcie3_rst),
MSM_PIN_FUNCTION(pcie3_prsnt),
MSM_PIN_FUNCTION(pcie3_pwren_n),
MSM_PIN_FUNCTION(pcie3_pwren),
MSM_PIN_FUNCTION(pcie3_pwrflt),
MSM_PIN_FUNCTION(pcie3_clk_req),
MSM_PIN_FUNCTION(ps_hold),
};
static const struct msm_pingroup ipq8064_groups[] = {

801
drivers/pinctrl/qcom/pinctrl-kuno.c Normal file
View File

@ -0,0 +1,801 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-msm.h"
#define REG_BASE 0x100000
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9 \
}, \
.nfuncs = 10, \
.ctl_reg = REG_BASE + REG_SIZE * id, \
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
}
static const struct pinctrl_pin_desc kuno_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
DECLARE_MSM_GPIO_PINS(47);
DECLARE_MSM_GPIO_PINS(48);
DECLARE_MSM_GPIO_PINS(49);
DECLARE_MSM_GPIO_PINS(50);
DECLARE_MSM_GPIO_PINS(51);
DECLARE_MSM_GPIO_PINS(52);
DECLARE_MSM_GPIO_PINS(53);
DECLARE_MSM_GPIO_PINS(54);
DECLARE_MSM_GPIO_PINS(55);
DECLARE_MSM_GPIO_PINS(56);
DECLARE_MSM_GPIO_PINS(57);
DECLARE_MSM_GPIO_PINS(58);
DECLARE_MSM_GPIO_PINS(59);
DECLARE_MSM_GPIO_PINS(60);
DECLARE_MSM_GPIO_PINS(61);
DECLARE_MSM_GPIO_PINS(62);
DECLARE_MSM_GPIO_PINS(63);
DECLARE_MSM_GPIO_PINS(64);
DECLARE_MSM_GPIO_PINS(65);
DECLARE_MSM_GPIO_PINS(66);
DECLARE_MSM_GPIO_PINS(67);
DECLARE_MSM_GPIO_PINS(68);
DECLARE_MSM_GPIO_PINS(69);
DECLARE_MSM_GPIO_PINS(70);
DECLARE_MSM_GPIO_PINS(71);
DECLARE_MSM_GPIO_PINS(72);
DECLARE_MSM_GPIO_PINS(73);
DECLARE_MSM_GPIO_PINS(74);
DECLARE_MSM_GPIO_PINS(75);
DECLARE_MSM_GPIO_PINS(76);
DECLARE_MSM_GPIO_PINS(77);
DECLARE_MSM_GPIO_PINS(78);
DECLARE_MSM_GPIO_PINS(79);
DECLARE_MSM_GPIO_PINS(80);
DECLARE_MSM_GPIO_PINS(81);
DECLARE_MSM_GPIO_PINS(82);
DECLARE_MSM_GPIO_PINS(83);
DECLARE_MSM_GPIO_PINS(84);
DECLARE_MSM_GPIO_PINS(85);
DECLARE_MSM_GPIO_PINS(86);
DECLARE_MSM_GPIO_PINS(87);
DECLARE_MSM_GPIO_PINS(88);
DECLARE_MSM_GPIO_PINS(89);
DECLARE_MSM_GPIO_PINS(90);
DECLARE_MSM_GPIO_PINS(91);
DECLARE_MSM_GPIO_PINS(92);
DECLARE_MSM_GPIO_PINS(93);
DECLARE_MSM_GPIO_PINS(94);
DECLARE_MSM_GPIO_PINS(95);
DECLARE_MSM_GPIO_PINS(96);
DECLARE_MSM_GPIO_PINS(97);
DECLARE_MSM_GPIO_PINS(98);
DECLARE_MSM_GPIO_PINS(99);
DECLARE_MSM_GPIO_PINS(100);
DECLARE_MSM_GPIO_PINS(101);
DECLARE_MSM_GPIO_PINS(102);
DECLARE_MSM_GPIO_PINS(103);
DECLARE_MSM_GPIO_PINS(104);
DECLARE_MSM_GPIO_PINS(105);
DECLARE_MSM_GPIO_PINS(106);
DECLARE_MSM_GPIO_PINS(107);
DECLARE_MSM_GPIO_PINS(108);
DECLARE_MSM_GPIO_PINS(109);
enum kuno_functions {
msm_mux_gpio,
msm_mux_audio_ref_clk,
msm_mux_coex_uart,
msm_mux_ebi2_lcd_a,
msm_mux_ebi2_lcd_cs,
msm_mux_ebi2_lcd_reset,
msm_mux_ebi2_lcd_te,
msm_mux_emac_mdc,
msm_mux_emac_mdio,
msm_mux_emac_pps_in,
msm_mux_emac_ptp_aux,
msm_mux_emac_ptp_pps,
msm_mux_gcc_gp1_clk,
msm_mux_gcc_gp2_clk,
msm_mux_gcc_gp3_clk,
msm_mux_mi2s0_data0,
msm_mux_mi2s0_data1,
msm_mux_mi2s0_sck,
msm_mux_mi2s0_ws,
msm_mux_mi2s1_data0,
msm_mux_mi2s1_data1,
msm_mux_mi2s1_sck,
msm_mux_mi2s1_ws,
msm_mux_mi2s_mclk,
msm_mux_nav_gpio,
msm_mux_pci_e_rst,
msm_mux_pcie_clkreq_n,
msm_mux_pll_bist_sync,
msm_mux_pll_clk_aux,
msm_mux_qdss_cti_trig0,
msm_mux_qdss_cti_trig1,
msm_mux_qdss_cti_trig1_mire,
msm_mux_qdss_gpio_traceclk,
msm_mux_qdss_gpio_tracectl,
msm_mux_qup0_se0,
msm_mux_qup0_se1,
msm_mux_qup0_se2,
msm_mux_qup0_se3_mira,
msm_mux_qup0_se3_mirb,
msm_mux_qup0_se4,
msm_mux_sdc4_clk,
msm_mux_sdc4_cmd,
msm_mux_sdc4_data,
msm_mux_sdc4_tb_trig,
msm_mux_sgmii_phy_intr,
msm_mux_spmi_coex_clk,
msm_mux_spmi_coex_data,
msm_mux_spmi_vgi_hwevent,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
msm_mux_uim1_reset,
msm_mux_usb2phy_ac_en,
msm_mux__,
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
};
static const char * const audio_ref_clk_groups[] = {
"gpio62",
};
static const char * const coex_uart_groups[] = {
"gpio44", "gpio45",
};
static const char * const ebi2_lcd_a_groups[] = {
"gpio93",
};
static const char * const ebi2_lcd_cs_groups[] = {
"gpio94",
};
static const char * const ebi2_lcd_reset_groups[] = {
"gpio89",
};
static const char * const ebi2_lcd_te_groups[] = {
"gpio88",
};
static const char * const emac_mdc_groups[] = {
"gpio98",
};
static const char * const emac_mdio_groups[] = {
"gpio99",
};
static const char * const emac_pps_in_groups[] = {
"gpio88",
};
static const char * const emac_ptp_aux_groups[] = {
"gpio93", "gpio94",
};
static const char * const emac_ptp_pps_groups[] = {
"gpio93", "gpio94",
};
static const char * const gcc_gp1_clk_groups[] = {
"gpio34",
};
static const char * const gcc_gp2_clk_groups[] = {
"gpio46",
};
static const char * const gcc_gp3_clk_groups[] = {
"gpio35",
};
static const char * const mi2s0_data0_groups[] = {
"gpio13",
};
static const char * const mi2s0_data1_groups[] = {
"gpio14",
};
static const char * const mi2s0_sck_groups[] = {
"gpio15",
};
static const char * const mi2s0_ws_groups[] = {
"gpio12",
};
static const char * const mi2s1_data0_groups[] = {
"gpio17",
};
static const char * const mi2s1_data1_groups[] = {
"gpio18",
};
static const char * const mi2s1_sck_groups[] = {
"gpio19",
};
static const char * const mi2s1_ws_groups[] = {
"gpio16",
};
static const char * const mi2s_mclk_groups[] = {
"gpio62",
};
static const char * const nav_gpio_groups[] = {
"gpio31", "gpio32", "gpio33",
};
static const char * const pci_e_rst_groups[] = {
"gpio57",
};
static const char * const pcie_clkreq_n_groups[] = {
"gpio56",
};
static const char * const pll_bist_sync_groups[] = {
"gpio47",
};
static const char * const pll_clk_aux_groups[] = {
"gpio54",
};
static const char * const qdss_cti_trig0_groups[] = {
"gpio16", "gpio17", "gpio54", "gpio55", "gpio60", "gpio84", "gpio101",
"gpio102",
};
static const char * const qdss_cti_trig1_groups[] = {
"gpio16", "gpio17", "gpio54", "gpio55", "gpio65", "gpio66", "gpio101",
"gpio102",
};
static const char * const qdss_cti_trig1_mire_groups[] = {
"gpio65", "gpio66",
};
static const char * const qdss_gpio_traceclk_groups[] = {
"gpio8",
};
static const char * const qdss_gpio_tracectl_groups[] = {
"gpio9",
};
static const char * const qup0_se0_groups[] = {
"gpio14", "gpio18", "gpio19", "gpio48", "gpio49", "gpio92", "gpio101",
};
static const char * const qup0_se1_groups[] = {
"gpio14", "gpio63", "gpio64", "gpio65", "gpio66", "gpio92", "gpio101",
};
static const char * const qup0_se2_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7", "gpio14", "gpio92", "gpio101",
};
static const char * const qup0_se3_mira_groups[] = {
"gpio8", "gpio9", "gpio14", "gpio16", "gpio17", "gpio92", "gpio101",
};
static const char * const qup0_se3_mirb_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15",
};
static const char * const qup0_se4_groups[] = {
"gpio10", "gpio11", "gpio14", "gpio80", "gpio81", "gpio92", "gpio101",
};
static const char * const sdc4_clk_groups[] = {
"gpio103",
};
static const char * const sdc4_cmd_groups[] = {
"gpio102",
};
static const char * const sdc4_data_groups[] = {
"gpio104", "gpio105", "gpio106", "gpio107",
};
static const char * const sdc4_tb_trig_groups[] = {
"gpio101",
};
static const char * const sgmii_phy_intr_groups[] = {
"gpio91",
};
static const char * const spmi_coex_clk_groups[] = {
"gpio76",
};
static const char * const spmi_coex_data_groups[] = {
"gpio75",
};
static const char * const spmi_vgi_hwevent_groups[] = {
"gpio78", "gpio79",
};
static const char * const uim1_clk_groups[] = {
"gpio3",
};
static const char * const uim1_data_groups[] = {
"gpio0",
};
static const char * const uim1_present_groups[] = {
"gpio1",
};
static const char * const uim1_reset_groups[] = {
"gpio2",
};
static const char * const usb2phy_ac_en_groups[] = {
"gpio90",
};
static const struct pinfunction kuno_functions[] = {
MSM_GPIO_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(audio_ref_clk),
MSM_PIN_FUNCTION(coex_uart),
MSM_PIN_FUNCTION(ebi2_lcd_a),
MSM_PIN_FUNCTION(ebi2_lcd_cs),
MSM_PIN_FUNCTION(ebi2_lcd_reset),
MSM_PIN_FUNCTION(ebi2_lcd_te),
MSM_PIN_FUNCTION(emac_mdc),
MSM_PIN_FUNCTION(emac_mdio),
MSM_PIN_FUNCTION(emac_pps_in),
MSM_PIN_FUNCTION(emac_ptp_aux),
MSM_PIN_FUNCTION(emac_ptp_pps),
MSM_PIN_FUNCTION(gcc_gp1_clk),
MSM_PIN_FUNCTION(gcc_gp2_clk),
MSM_PIN_FUNCTION(gcc_gp3_clk),
MSM_PIN_FUNCTION(mi2s0_data0),
MSM_PIN_FUNCTION(mi2s0_data1),
MSM_PIN_FUNCTION(mi2s0_sck),
MSM_PIN_FUNCTION(mi2s0_ws),
MSM_PIN_FUNCTION(mi2s1_data0),
MSM_PIN_FUNCTION(mi2s1_data1),
MSM_PIN_FUNCTION(mi2s1_sck),
MSM_PIN_FUNCTION(mi2s1_ws),
MSM_PIN_FUNCTION(mi2s_mclk),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pci_e_rst),
MSM_PIN_FUNCTION(pcie_clkreq_n),
MSM_PIN_FUNCTION(pll_bist_sync),
MSM_PIN_FUNCTION(pll_clk_aux),
MSM_PIN_FUNCTION(qdss_cti_trig0),
MSM_PIN_FUNCTION(qdss_cti_trig1),
MSM_PIN_FUNCTION(qdss_cti_trig1_mire),
MSM_PIN_FUNCTION(qdss_gpio_traceclk),
MSM_PIN_FUNCTION(qdss_gpio_tracectl),
MSM_PIN_FUNCTION(qup0_se0),
MSM_PIN_FUNCTION(qup0_se1),
MSM_PIN_FUNCTION(qup0_se2),
MSM_PIN_FUNCTION(qup0_se3_mira),
MSM_PIN_FUNCTION(qup0_se3_mirb),
MSM_PIN_FUNCTION(qup0_se4),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sdc4_data),
MSM_PIN_FUNCTION(sdc4_tb_trig),
MSM_PIN_FUNCTION(sgmii_phy_intr),
MSM_PIN_FUNCTION(spmi_coex_clk),
MSM_PIN_FUNCTION(spmi_coex_data),
MSM_PIN_FUNCTION(spmi_vgi_hwevent),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(usb2phy_ac_en),
};
/* Every pin is maintained as a single group, and missing or non-existing pin
* would be maintained as dummy group to synchronize pin group index with
* pin descriptor registered with pinctrl core.
* Clients would not be able to request these dummy pin groups.
*/
static const struct msm_pingroup kuno_groups[] = {
[0] = PINGROUP(0, uim1_data, _, _, _, _, _, _, _, _),
[1] = PINGROUP(1, uim1_present, _, _, _, _, _, _, _, _),
[2] = PINGROUP(2, uim1_reset, _, _, _, _, _, _, _, _),
[3] = PINGROUP(3, uim1_clk, _, _, _, _, _, _, _, _),
[4] = PINGROUP(4, qup0_se2, _, _, _, _, _, _, _, _),
[5] = PINGROUP(5, qup0_se2, _, _, _, _, _, _, _, _),
[6] = PINGROUP(6, qup0_se2, _, _, _, _, _, _, _, _),
[7] = PINGROUP(7, qup0_se2, _, _, _, _, _, _, _, _),
[8] = PINGROUP(8, qup0_se3_mira, _, qdss_gpio_traceclk, _, _, _, _, _, _),
[9] = PINGROUP(9, qup0_se3_mira, _, qdss_gpio_tracectl, _, _, _, _, _, _),
[10] = PINGROUP(10, qup0_se4, _, _, _, _, _, _, _, _),
[11] = PINGROUP(11, qup0_se4, _, _, _, _, _, _, _, _),
[12] = PINGROUP(12, mi2s0_ws, qup0_se3_mirb, _, _, _, _, _, _, _),
[13] = PINGROUP(13, mi2s0_data0, qup0_se3_mirb, _, _, _, _, _, _, _),
[14] = PINGROUP(14, mi2s0_data1, qup0_se3_mirb, qup0_se0, qup0_se1, qup0_se2,
qup0_se3_mira, qup0_se4, _, _),
[15] = PINGROUP(15, mi2s0_sck, qup0_se3_mirb, _, _, _, _, _, _, _),
[16] = PINGROUP(16, mi2s1_ws, qup0_se3_mira, qdss_cti_trig1, qdss_cti_trig0,
_, _, _, _, _),
[17] = PINGROUP(17, mi2s1_data0, qup0_se3_mira, qdss_cti_trig1, qdss_cti_trig0,
_, _, _, _, _),
[18] = PINGROUP(18, mi2s1_data1, qup0_se0, _, _, _, _, _, _, _),
[19] = PINGROUP(19, mi2s1_sck, qup0_se0, _, _, _, _, _, _, _),
[20] = PINGROUP(20, _, _, _, _, _, _, _, _, _),
[21] = PINGROUP(21, _, _, _, _, _, _, _, _, _),
[22] = PINGROUP(22, _, _, _, _, _, _, _, _, _),
[23] = PINGROUP(23, _, _, _, _, _, _, _, _, _),
[24] = PINGROUP(24, _, _, _, _, _, _, _, _, _),
[25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),
[26] = PINGROUP(26, _, _, _, _, _, _, _, _, _),
[27] = PINGROUP(27, _, _, _, _, _, _, _, _, _),
[28] = PINGROUP(28, _, _, _, _, _, _, _, _, _),
[29] = PINGROUP(29, _, _, _, _, _, _, _, _, _),
[30] = PINGROUP(30, _, _, _, _, _, _, _, _, _),
[31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _),
[32] = PINGROUP(32, nav_gpio, _, _, _, _, _, _, _, _),
[33] = PINGROUP(33, nav_gpio, _, _, _, _, _, _, _, _),
[34] = PINGROUP(34, _, gcc_gp1_clk, _, _, _, _, _, _, _),
[35] = PINGROUP(35, _, _, gcc_gp3_clk, _, _, _, _, _, _),
[36] = PINGROUP(36, _, _, _, _, _, _, _, _, _),
[37] = PINGROUP(37, _, _, _, _, _, _, _, _, _),
[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _),
[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _),
[40] = PINGROUP(40, _, _, _, _, _, _, _, _, _),
[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _),
[42] = PINGROUP(42, _, _, _, _, _, _, _, _, _),
[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _),
[44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _),
[45] = PINGROUP(45, coex_uart, _, _, _, _, _, _, _, _),
[46] = PINGROUP(46, _, _, _, gcc_gp2_clk, _, _, _, _, _),
[47] = PINGROUP(47, _, pll_bist_sync, _, _, _, _, _, _, _),
[48] = PINGROUP(48, qup0_se0, _, _, _, _, _, _, _, _),
[49] = PINGROUP(49, qup0_se0, _, _, _, _, _, _, _, _),
[50] = PINGROUP(50, _, _, _, _, _, _, _, _, _),
[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _),
[52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),
[53] = PINGROUP(53, _, _, _, _, _, _, _, _, _),
[54] = PINGROUP(54, qdss_cti_trig1, qdss_cti_trig0, pll_clk_aux, _, _, _, _, _, _),
[55] = PINGROUP(55, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _, _),
[56] = PINGROUP(56, pcie_clkreq_n, _, _, _, _, _, _, _, _),
[57] = PINGROUP(57, pci_e_rst, _, _, _, _, _, _, _, _),
[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _),
[59] = PINGROUP(59, _, _, _, _, _, _, _, _, _),
[60] = PINGROUP(60, qdss_cti_trig0, _, _, _, _, _, _, _, _),
[61] = PINGROUP(61, _, _, _, _, _, _, _, _, _),
[62] = PINGROUP(62, mi2s_mclk, audio_ref_clk, _, _, _, _, _, _, _),
[63] = PINGROUP(63, qup0_se1, _, _, _, _, _, _, _, _),
[64] = PINGROUP(64, qup0_se1, _, _, _, _, _, _, _, _),
[65] = PINGROUP(65, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _, _, _, _, _),
[66] = PINGROUP(66, qup0_se1, qdss_cti_trig1, qdss_cti_trig1_mire, _, _, _, _, _, _),
[67] = PINGROUP(67, _, _, _, _, _, _, _, _, _),
[68] = PINGROUP(68, _, _, _, _, _, _, _, _, _),
[69] = PINGROUP(69, _, _, _, _, _, _, _, _, _),
[70] = PINGROUP(70, _, _, _, _, _, _, _, _, _),
[71] = PINGROUP(71, _, _, _, _, _, _, _, _, _),
[72] = PINGROUP(72, _, _, _, _, _, _, _, _, _),
[73] = PINGROUP(73, _, _, _, _, _, _, _, _, _),
[74] = PINGROUP(74, _, _, _, _, _, _, _, _, _),
[75] = PINGROUP(75, spmi_coex_data, _, _, _, _, _, _, _, _),
[76] = PINGROUP(76, spmi_coex_clk, _, _, _, _, _, _, _, _),
[77] = PINGROUP(77, _, _, _, _, _, _, _, _, _),
[78] = PINGROUP(78, spmi_vgi_hwevent, _, _, _, _, _, _, _, _),
[79] = PINGROUP(79, spmi_vgi_hwevent, _, _, _, _, _, _, _, _),
[80] = PINGROUP(80, qup0_se4, _, _, _, _, _, _, _, _),
[81] = PINGROUP(81, qup0_se4, _, _, _, _, _, _, _, _),
[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _),
[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _),
[84] = PINGROUP(84, qdss_cti_trig0, _, _, _, _, _, _, _, _),
[85] = PINGROUP(85, _, _, _, _, _, _, _, _, _),
[86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
[87] = PINGROUP(87, _, _, _, _, _, _, _, _, _),
[88] = PINGROUP(88, ebi2_lcd_te, emac_pps_in, _, _, _, _, _, _, _),
[89] = PINGROUP(89, ebi2_lcd_reset, _, _, _, _, _, _, _, _),
[90] = PINGROUP(90, usb2phy_ac_en, _, _, _, _, _, _, _, _),
[91] = PINGROUP(91, sgmii_phy_intr, _, _, _, _, _, _, _, _),
[92] = PINGROUP(92, qup0_se0, qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _, _, _, _),
[93] = PINGROUP(93, ebi2_lcd_a, emac_ptp_pps, emac_ptp_aux, _, _, _, _, _, _),
[94] = PINGROUP(94, ebi2_lcd_cs, emac_ptp_pps, emac_ptp_aux, _, _, _, _, _, _),
[95] = PINGROUP(95, _, _, _, _, _, _, _, _, _),
[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
[97] = PINGROUP(97, _, _, _, _, _, _, _, _, _),
[98] = PINGROUP(98, emac_mdc, _, _, _, _, _, _, _, _),
[99] = PINGROUP(99, emac_mdio, _, _, _, _, _, _, _, _),
[100] = PINGROUP(100, _, _, _, _, _, _, _, _, _),
[101] = PINGROUP(101, sdc4_tb_trig, qdss_cti_trig1, qdss_cti_trig0, qup0_se0,
qup0_se1, qup0_se2, qup0_se3_mira, qup0_se4, _),
[102] = PINGROUP(102, sdc4_cmd, qdss_cti_trig1, qdss_cti_trig0, _, _, _, _, _, _),
[103] = PINGROUP(103, sdc4_clk, _, _, _, _, _, _, _, _),
[104] = PINGROUP(104, sdc4_data, _, _, _, _, _, _, _, _),
[105] = PINGROUP(105, sdc4_data, _, _, _, _, _, _, _, _),
[106] = PINGROUP(106, sdc4_data, _, _, _, _, _, _, _, _),
[107] = PINGROUP(107, sdc4_data, _, _, _, _, _, _, _, _),
[108] = PINGROUP(108, _, _, _, _, _, _, _, _, _),
[109] = PINGROUP(109, _, _, _, _, _, _, _, _, _),
};
static const struct msm_gpio_wakeirq_map kuno_pdc_map[] = {
{ 1, 62 }, { 2, 83 }, { 4, 59 }, { 5, 107 }, { 6, 112 }, { 7, 119 },
{ 8, 123 }, { 10, 52 }, { 11, 73 }, { 12, 74 }, { 13, 75 }, { 14, 76 },
{ 15, 77 }, { 16, 81 }, { 17, 82 }, { 18, 80 }, { 19, 100 }, { 21, 88 },
{ 22, 99 }, { 23, 84 }, { 24, 85 }, { 25, 97 }, { 26, 86 }, { 27, 102 },
{ 28, 87 }, { 35, 103 }, { 43, 90 }, { 44, 60 }, { 45, 61 }, { 46, 104 },
{ 47, 89 }, { 48, 105 }, { 49, 106 }, { 50, 101 }, { 52, 109 }, { 53, 79 },
{ 54, 110 }, { 55, 111 }, { 56, 78 }, { 57, 71 }, { 60, 113 }, { 61, 114 },
{ 63, 115 }, { 64, 116 }, { 65, 57 }, { 66, 117 }, { 68, 64 }, { 69, 118 },
{ 71, 108 }, { 73, 120 }, { 74, 121 }, { 76, 47 }, { 77, 122 }, { 78, 65 },
{ 79, 66 }, { 80, 124 }, { 81, 125 }, { 82, 126 }, { 83, 127 }, { 84, 93 },
{ 85, 128 }, { 86, 129 }, { 87, 70 }, { 88, 130 }, { 96, 68 }, { 98, 50 },
{ 99, 67 }, { 100, 51 }, { 101, 53 }, { 102, 54 }, { 103, 98 }, { 104, 91 },
{ 105, 69 }, { 106, 55 }, { 107, 56 }, { 109, 72 },
};
static const struct msm_pinctrl_soc_data kuno_tlmm = {
.pins = kuno_pins,
.npins = ARRAY_SIZE(kuno_pins),
.functions = kuno_functions,
.nfunctions = ARRAY_SIZE(kuno_functions),
.groups = kuno_groups,
.ngroups = ARRAY_SIZE(kuno_groups),
.ngpios = 110,
.wakeirq_map = kuno_pdc_map,
.nwakeirq_map = ARRAY_SIZE(kuno_pdc_map),
};
static int kuno_tlmm_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &kuno_tlmm);
}
static const struct of_device_id kuno_tlmm_of_match[] = {
{ .compatible = "qcom,kuno-tlmm", },
{ },
};
MODULE_DEVICE_TABLE(of, kuno_tlmm_of_match);
static struct platform_driver kuno_tlmm_driver = {
.driver = {
.name = "kuno-tlmm",
.of_match_table = kuno_tlmm_of_match,
},
.probe = kuno_tlmm_probe,
};
static int __init kuno_tlmm_init(void)
{
return platform_driver_register(&kuno_tlmm_driver);
}
arch_initcall(kuno_tlmm_init);
static void __exit kuno_tlmm_exit(void)
{
platform_driver_unregister(&kuno_tlmm_driver);
}
module_exit(kuno_tlmm_exit);
MODULE_DESCRIPTION("QTI Kuno TLMM driver");
MODULE_LICENSE("GPL");

6
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
View File

@ -421,6 +421,7 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,
struct pinctrl_pin_desc pindesc;
unsigned int func;
int is_out;
int value;
int drive;
int pull;
u32 ctl_reg;
@ -443,7 +444,10 @@ static void lpi_gpio_dbg_show_one(struct seq_file *s,
drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
value = lpi_gpio_get(chip, offset);
seq_printf(s, " %-8s: %-3s", pindesc.name, is_out ? "out" : "in");
seq_printf(s, " %-4s func%d", str_high_low(value), func);
seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
seq_printf(s, " %s", pulls[pull]);
}

17
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
View File

@ -92,6 +92,23 @@ struct pinctrl_pin_desc;
.pin_offset = 0, \
}
#define LPI_PINGROUP6(id, soff, f1, f2, f3, f4, f5) \
{ \
.pin = id, \
.slew_offset = soff, \
.slew_base_spare_1 = false, \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
LPI_MUX_##f2, \
LPI_MUX_##f3, \
LPI_MUX_##f4, \
LPI_MUX_##f5, \
}, \
.nfuncs = 6, \
.pin_offset = 0, \
}
/*
* Slew rate control is done in the same register as rest of the
* pin configuration.

25
drivers/pinctrl/qcom/pinctrl-msm.h
View File

@ -14,21 +14,6 @@ struct platform_device;
struct pinctrl_pin_desc;
#define APQ_PIN_FUNCTION(fname) \
[APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define IPQ_PIN_FUNCTION(fname) \
[IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define IPQ_GPIO_PIN_FUNCTION(fname) \
[IPQ_MUX_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define MSM_PIN_FUNCTION(fname) \
[msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
@ -39,16 +24,6 @@ struct pinctrl_pin_desc;
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define QCA_PIN_FUNCTION(fname) \
[qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define QCA_GPIO_PIN_FUNCTION(fname) \
[qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
/**
* struct msm_pingroup - Qualcomm pingroup definition
* @grp: Generic data of the pin group (name and pins)

1257
drivers/pinctrl/qcom/pinctrl-msm8952.c Normal file
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File diff suppressed because it is too large Load Diff

1
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
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@ -1259,6 +1259,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pmau0102-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 },
{ .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },

2
drivers/pinctrl/qcom/tlmm-test.c
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@ -587,7 +587,7 @@ static int tlmm_reg_base(struct device_node *tlmm, struct resource *res)
return count;
}
reg_names = kcalloc(count, sizeof(char *), GFP_KERNEL);
reg_names = kcalloc(count, sizeof(*reg_names), GFP_KERNEL);
if (!reg_names)
return -ENOMEM;