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ARM: nxp: lpc: device tree updates for v6.18

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This pull request contains device tree changes for ARM NXP LPC32xx and
 ARM NXP LPC18xx/LPC43xx for v6.18, please pull the following:
 
 - Frank fixes a multitude of device tree checker warnings reported for
   NXP LPC18xx/LPC43xx powered boards,
 - Vladimir fixes a number of compile time warnings issued by a dt checker
   for NXP LPC32xx powered boards,
 - Vladimir replaces Roland as a maintainer of NXP LPC32xx platform
   device trees, Roland is inactive for more than 10 years.
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Merge tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx into soc/dt

ARM: nxp: lpc: device tree updates for v6.18

This pull request contains device tree changes for ARM NXP LPC32xx and
ARM NXP LPC18xx/LPC43xx for v6.18, please pull the following:

- Frank fixes a multitude of device tree checker warnings reported for
  NXP LPC18xx/LPC43xx powered boards,
- Vladimir fixes a number of compile time warnings issued by a dt checker
  for NXP LPC32xx powered boards,
- Vladimir replaces Roland as a maintainer of NXP LPC32xx platform
  device trees, Roland is inactive for more than 10 years.

* tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx:
  ARM: dts: lpc32xx: Correct PL080 DMA controller device node name
  ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
  ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
  ARM: dts: lpc32xx: Correct SD/MMC controller device node name
  ARM: dts: lpc32xx: Correct motor PWM device tree node name
  ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
  dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
  ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits
  ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller
  ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio
  ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'
  ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92
  ARM: dts: lpc: add cfg surfix in pinctrl child node
  ARM: dts: lpc: add #address-cells and #size-cells for sram node
  ARM: dts: lpc18xx: swap clock-names bic and cui
  ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0
  ARM: dts: lpc18xx: rename node name mmcsd to mmc
  ARM: dts: lpc18xx: rename node name flash-controller to spi

Link: https://lore.kernel.org/r/20250911130642.41958-1-vz@mleia.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-15 15:21:55 +02:00
commit 4c4457342a
9 changed files with 66 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx Platforms
maintainers:
- Roland Stigge <stigge@antcom.de>
- Vladimir Zapolskiy <vz@mleia.com>
properties:
compatible:

14
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
View File

@ -100,23 +100,25 @@ dmac: dma-controller@40002000 {
memcpy-bus-width = <32>;
};
spifi: flash-controller@40003000 {
spifi: spi@40003000 {
compatible = "nxp,lpc1773-spifi";
reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
reg-names = "spifi", "flash";
interrupts = <30>;
clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
clock-names = "spifi", "reg";
#address-cells = <1>;
#size-cells = <0>;
resets = <&rgu 53>;
status = "disabled";
};
mmcsd: mmcsd@40004000 {
mmcsd: mmc@40004000 {
compatible = "snps,dw-mshc";
reg = <0x40004000 0x1000>;
interrupts = <6>;
clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
clock-names = "ciu", "biu";
clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>;
clock-names = "biu", "ciu";
resets = <&rgu 20>;
status = "disabled";
};
@ -535,3 +537,7 @@ gpio: gpio@400f4000 {
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

11
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
View File

@ -77,12 +77,13 @@ mlc: flash@200a8000 {
status = "disabled";
};
dma: dma@31000000 {
dma: dma-controller@31000000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0x31000000 0x1000>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_DMA>;
clock-names = "apb_pclk";
#dma-cells = <2>;
};
usb {
@ -224,8 +225,8 @@ i2s0: i2s@20094000 {
status = "disabled";
};
sd: sd@20098000 {
compatible = "arm,pl18x", "arm,primecell";
sd: mmc@20098000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x20098000 0x1000>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<13 IRQ_TYPE_LEVEL_HIGH>;
@ -298,11 +299,11 @@ i2c2: i2c@400a8000 {
clocks = <&clk LPC32XX_CLK_I2C2>;
};
mpwm: mpwm@400e8000 {
mpwm: pwm@400e8000 {
compatible = "nxp,lpc3220-motor-pwm";
reg = <0x400e8000 0x78>;
#pwm-cells = <3>;
status = "disabled";
#pwm-cells = <2>;
};
};

6
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
View File

@ -108,14 +108,14 @@ i2c0_pins_cfg {
};
ssp_pins: ssp-pins {
ssp1_cs {
ssp1_cs_cfg {
pins = "p6_7";
function = "gpio";
bias-pull-up;
bias-disable;
};
ssp1_miso_mosi {
ssp1_miso_mosi_cfg {
pins = "p1_3", "p1_4";
function = "ssp1";
slew-rate = <1>;
@ -124,7 +124,7 @@ ssp1_miso_mosi {
input-schmitt-disable;
};
ssp1_sck {
ssp1_sck_cfg {
pins = "pf_4";
function = "ssp1";
slew-rate = <1>;

22
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
View File

@ -43,50 +43,50 @@ pca_buttons {
poll-interval = <100>;
autorepeat;
button0 {
button-0 {
label = "joy:right";
linux,code = <KEY_RIGHT>;
gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
};
button1 {
button-1 {
label = "joy:up";
linux,code = <KEY_UP>;
gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
};
button2 {
button-2 {
label = "joy:enter";
linux,code = <KEY_ENTER>;
gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
};
button3 {
button-3 {
label = "joy:left";
linux,code = <KEY_LEFT>;
gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
};
button4 {
button-4 {
label = "joy:down";
linux,code = <KEY_DOWN>;
gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
};
button5 {
button-5 {
label = "user:sw3";
linux,code = <KEY_F1>;
gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
};
button6 {
button-6 {
label = "user:sw4";
linux,code = <KEY_F2>;
gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
};
button7 {
button-7 {
label = "user:sw5";
linux,code = <KEY_F3>;
gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
@ -406,6 +406,9 @@ cs2 {
ext_sram: sram@2,0 {
compatible = "mmio-sram";
reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 2 0 0x80000>;
};
};
};
@ -451,8 +454,9 @@ &spifi {
pinctrl-names = "default";
pinctrl-0 = <&spifi_pins>;
flash {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;

9
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
View File

@ -24,16 +24,25 @@ soc {
sram0: sram@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
sram1: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
sram2: sram@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
};

21
arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
View File

@ -60,31 +60,31 @@ gpio_joystick {
poll-interval = <100>;
autorepeat;
button0 {
button-0 {
label = "joy_enter";
linux,code = <KEY_ENTER>;
gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
};
button1 {
button-1 {
label = "joy_left";
linux,code = <KEY_LEFT>;
gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>;
};
button2 {
button-2 {
label = "joy_up";
linux,code = <KEY_UP>;
gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>;
};
button3 {
button-3 {
label = "joy_right";
linux,code = <KEY_RIGHT>;
gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>;
};
button4 {
button-4 {
label = "joy_down";
linux,code = <KEY_DOWN>;
gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>;
@ -403,7 +403,7 @@ spifi_cs_cfg {
};
ssp0_pins: ssp0-pins {
ssp0_sck_miso_mosi {
ssp0_sck_miso_mosi_cfg {
pins = "pf_0", "pf_2", "pf_3";
function = "ssp0";
slew-rate = <1>;
@ -412,7 +412,7 @@ ssp0_sck_miso_mosi {
input-schmitt-disable;
};
ssp0_ssel {
ssp0_ssel_cfg {
pins = "pf_1";
function = "ssp0";
bias-pull-up;
@ -452,12 +452,12 @@ uart3_tx_cfg {
};
usb0_pins: usb0-pins {
usb0_pwr_enable {
usb0_pwr_enable_cfg {
pins = "p2_3";
function = "usb0";
};
usb0_pwr_fault {
usb0_pwr_fault_cfg {
pins = "p8_0";
function = "usb0";
bias-disable;
@ -582,8 +582,9 @@ &spifi {
pinctrl-names = "default";
pinctrl-0 = <&spifi_pins>;
flash {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-cpol;
spi-cpha;
spi-rx-bus-width = <4>;

6
arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
View File

@ -63,6 +63,7 @@ led6 {
panel: panel {
compatible = "innolux,at070tn92";
power-supply = <&vcc>;
port {
panel_input: endpoint {
@ -543,7 +544,7 @@ &mac {
pinctrl-0 = <&enet_rmii_pins>;
phy-handle = <&phy1>;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
@ -569,8 +570,9 @@ &spifi {
pinctrl-0 = <&spifi_pins>;
/* Atmel AT25DF321A */
flash {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <51000000>;
spi-cpol;
spi-cpha;

9
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
View File

@ -24,16 +24,25 @@ soc {
sram0: sram@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
sram1: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
sram2: sram@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
};
};