From c3ad87de22e57e35b1c516f85aa6ea5c81ec5754 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:46:57 -0400 Subject: [PATCH 01/18] ARM: dts: lpc18xx: rename node name flash-controller to spi Anyway it is SPI controller although intent to connect qspi flash. Rename node name flash-controller to spi to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): $nodename:0: 'flash-controller@40003000' does not match '^spi(@.*|-([0-9]|[1-9][0-9]+))?$ Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 6dd73290f0c6..e17298e89eeb 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -100,7 +100,7 @@ dmac: dma-controller@40002000 { memcpy-bus-width = <32>; }; - spifi: flash-controller@40003000 { + spifi: spi@40003000 { compatible = "nxp,lpc1773-spifi"; reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; reg-names = "spifi", "flash"; From 3d2a00271e0b425073750b6b2ca51460061d3fdd Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:46:58 -0400 Subject: [PATCH 02/18] ARM: dts: lpc18xx: rename node name mmcsd to mmc Change node name mmcsd to mmc to fix CHECK_DTB warnings: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: mmcsd@40004000 (snps,dw-mshc): $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$' Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index e17298e89eeb..80da477bae3d 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -111,7 +111,7 @@ spifi: spi@40003000 { status = "disabled"; }; - mmcsd: mmcsd@40004000 { + mmcsd: mmc@40004000 { compatible = "snps,dw-mshc"; reg = <0x40004000 0x1000>; interrupts = <6>; From 4e328041248c5f8a85f576fac16de6118c8d9bec Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:46:59 -0400 Subject: [PATCH 03/18] ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0 Change node name 'flash' to 'flash@0' to fix below CHECK_DTB warnings. arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): Unevaluated properties are not allowed ('flash' was unexpected) from schema $id: http://devicetree.org/schemas/mtd/nxp,lpc1773-spifi.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 3 ++- arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 3 ++- arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts index 93d0c2e99e7c..8fc89fb6eef1 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -451,8 +451,9 @@ &spifi { pinctrl-names = "default"; pinctrl-0 = <&spifi_pins>; - flash { + flash@0 { compatible = "jedec,spi-nor"; + reg = <0>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts index 4aefbc01dfc0..60bcfa5e0518 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts @@ -582,8 +582,9 @@ &spifi { pinctrl-names = "default"; pinctrl-0 = <&spifi_pins>; - flash { + flash@0 { compatible = "jedec,spi-nor"; + reg = <0>; spi-cpol; spi-cpha; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts index 846afb8ccbf1..22f7dd671c90 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts @@ -569,8 +569,9 @@ &spifi { pinctrl-0 = <&spifi_pins>; /* Atmel AT25DF321A */ - flash { + flash@0 { compatible = "jedec,spi-nor"; + reg = <0>; spi-max-frequency = <51000000>; spi-cpol; spi-cpha; From 5460b42b65cd36113114d45e519359f129c7331c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:00 -0400 Subject: [PATCH 04/18] ARM: dts: lpc18xx: swap clock-names bic and cui Swap clock-names bic and cui to fix below CHECK_DTB warnings: /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dtb: mmc@40004000 (snps,dw-mshc): clock-names:0: 'biu' was expected from schema $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml# /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dtb: mmc@40004000 (snps,dw-mshc): clock-names:1: 'ciu' was expected Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 80da477bae3d..0be2486f0717 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -115,8 +115,8 @@ mmcsd: mmc@40004000 { compatible = "snps,dw-mshc"; reg = <0x40004000 0x1000>; interrupts = <6>; - clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; - clock-names = "ciu", "biu"; + clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>; + clock-names = "biu", "ciu"; resets = <&rgu 20>; status = "disabled"; }; From 9276abee591ae0a82cc7184653ac8d77d2eb7b88 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:01 -0400 Subject: [PATCH 05/18] ARM: dts: lpc: add #address-cells and #size-cells for sram node Add #address-cells and #size-cells for sram node to fix below DTB_CHECK warnings: arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: sram@2,0 (mmio-sram): '#address-cells' is a required property Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 3 +++ arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 9 +++++++++ arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 9 +++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts index 8fc89fb6eef1..9d36283efe0f 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -406,6 +406,9 @@ cs2 { ext_sram: sram@2,0 { compatible = "mmio-sram"; reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 2 0 0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi index c4422f587055..707d22a219d8 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi @@ -24,16 +24,25 @@ soc { sram0: sram@10000000 { compatible = "mmio-sram"; reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram1: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram2: sram@20000000 { compatible = "mmio-sram"; reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi index 72f12db8d53a..d138ee7869ff 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi @@ -24,16 +24,25 @@ soc { sram0: sram@10000000 { compatible = "mmio-sram"; reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram1: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram2: sram@20000000 { compatible = "mmio-sram"; reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; }; From fcc5f89e3050e3bb3c25c49c87ea8d3100e2cf34 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:02 -0400 Subject: [PATCH 06/18] ARM: dts: lpc: add cfg surfix in pinctrl child node Add cfg surfix in pinctrl child node to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: pinctrl@40086000 (nxp,lpc1850-scu): ssp-pins: 'ssp1_cs', 'ssp1_miso_mosi', 'ssp1_sck' do not match any of the regexes: '^pinctrl-[0-9]+$', '_cfg$' from schema $id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 6 +++--- arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts index beddaba85393..5ff43c825944 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts @@ -108,14 +108,14 @@ i2c0_pins_cfg { }; ssp_pins: ssp-pins { - ssp1_cs { + ssp1_cs_cfg { pins = "p6_7"; function = "gpio"; bias-pull-up; bias-disable; }; - ssp1_miso_mosi { + ssp1_miso_mosi_cfg { pins = "p1_3", "p1_4"; function = "ssp1"; slew-rate = <1>; @@ -124,7 +124,7 @@ ssp1_miso_mosi { input-schmitt-disable; }; - ssp1_sck { + ssp1_sck_cfg { pins = "pf_4"; function = "ssp1"; slew-rate = <1>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts index 60bcfa5e0518..9dc8c3cc2211 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts @@ -403,7 +403,7 @@ spifi_cs_cfg { }; ssp0_pins: ssp0-pins { - ssp0_sck_miso_mosi { + ssp0_sck_miso_mosi_cfg { pins = "pf_0", "pf_2", "pf_3"; function = "ssp0"; slew-rate = <1>; @@ -412,7 +412,7 @@ ssp0_sck_miso_mosi { input-schmitt-disable; }; - ssp0_ssel { + ssp0_ssel_cfg { pins = "pf_1"; function = "ssp0"; bias-pull-up; @@ -452,12 +452,12 @@ uart3_tx_cfg { }; usb0_pins: usb0-pins { - usb0_pwr_enable { + usb0_pwr_enable_cfg { pins = "p2_3"; function = "usb0"; }; - usb0_pwr_fault { + usb0_pwr_fault_cfg { pins = "p8_0"; function = "usb0"; bias-disable; From 332d4e0092e8cb09f1cc0809260f1215d9371268 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:03 -0400 Subject: [PATCH 07/18] ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92 Add power-supply for innolux,at070tn92 to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: panel (innolux,at070tn92): 'power-supply' is a required property Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts index 22f7dd671c90..ca91bb8f6ada 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts @@ -63,6 +63,7 @@ led6 { panel: panel { compatible = "innolux,at070tn92"; + power-supply = <&vcc>; port { panel_input: endpoint { From caa9c67398d129ec8ab2d1db9a6038d0a35e31df Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:04 -0400 Subject: [PATCH 08/18] ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]' Change node name 'button[0-9]' to button-[0-9]' to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: pca_buttons (gpio-keys-polled): 'button0', ... do not match any of the regexes: '^(button|...', 'pinctrl-[0-9]+' Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 16 ++++++++-------- .../boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 10 +++++----- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts index 9d36283efe0f..18f757c56905 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -43,50 +43,50 @@ pca_buttons { poll-interval = <100>; autorepeat; - button0 { + button-0 { label = "joy:right"; linux,code = ; gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; }; - button1 { + button-1 { label = "joy:up"; linux,code = ; gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; }; - button2 { + button-2 { label = "joy:enter"; linux,code = ; gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; }; - button3 { + button-3 { label = "joy:left"; linux,code = ; gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; }; - button4 { + button-4 { label = "joy:down"; linux,code = ; gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; }; - button5 { + button-5 { label = "user:sw3"; linux,code = ; gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; }; - button6 { + button-6 { label = "user:sw4"; linux,code = ; gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; }; - button7 { + button-7 { label = "user:sw5"; linux,code = ; gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts index 9dc8c3cc2211..7ccb4c2ca571 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts @@ -60,31 +60,31 @@ gpio_joystick { poll-interval = <100>; autorepeat; - button0 { + button-0 { label = "joy_enter"; linux,code = ; gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; }; - button1 { + button-1 { label = "joy_left"; linux,code = ; gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; }; - button2 { + button-2 { label = "joy_up"; linux,code = ; gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; }; - button3 { + button-3 { label = "joy_right"; linux,code = ; gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; }; - button4 { + button-4 { label = "joy_down"; linux,code = ; gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; From 212480c0e7cdfaf22b2cbb2f9144c9f357de2b1a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:05 -0400 Subject: [PATCH 09/18] ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio Change node name mdio0 to mdio to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: ethernet@40010000 (nxp,lpc1850-dwmac): Unevaluated properties are not allowed ('mdio0' was unexpected) from schema $id: http://devicetree.org/schemas/net/nxp,lpc1850-dwmac.yaml Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts index ca91bb8f6ada..d18f2b2caf68 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts @@ -544,7 +544,7 @@ &mac { pinctrl-0 = <&enet_rmii_pins>; phy-handle = <&phy1>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; From a884b8fc2efd44665cd05a6878aa23345d97a5cb Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:06 -0400 Subject: [PATCH 10/18] ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller Add #address-cells and #szie-cells for spi flash controller to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #address-cells for SPI bus also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3 arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #size-cells for SPI bus also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3 Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 0be2486f0717..d212ca252b06 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -107,6 +107,8 @@ spifi: spi@40003000 { interrupts = <30>; clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; clock-names = "spifi", "reg"; + #address-cells = <1>; + #size-cells = <0>; resets = <&rgu 53>; status = "disabled"; }; From 70e42a63542e0d82ecfe2ae6c5fb5033a73c8c71 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:07 -0400 Subject: [PATCH 11/18] ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits Add missed arm,num-irq-priority-bits to fix below CHECK_DTBS warning: arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: interrupt-controller@e000e100 (arm,armv7m-nvic): 'arm,num-irq-priority-bits' is a required property from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index d212ca252b06..152e98cf0c4e 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -537,3 +537,7 @@ gpio: gpio@400f4000 { }; }; }; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; From b17b850da6f9c4440a49d96cded5faa85123aadf Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:41 +0300 Subject: [PATCH 12/18] dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms Make a formal change to reflect the actual NXP LPC32xx maintainership for the last years. Cc: Roland Stigge Acked-by: Rob Herring (Arm) Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml index f1bd6f50e726..6b7f5e6f99cf 100644 --- a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml +++ b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP LPC32xx Platforms maintainers: - - Roland Stigge + - Vladimir Zapolskiy properties: compatible: From 65ae9ea77e1f2a20ad2866f99596df7ccdbd3b95 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:42 +0300 Subject: [PATCH 13/18] ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt to yaml format") both types of PWM controlles on NXP LPC32xx SoC fairly gained 3 cells, reflect it in the platform dtsi file. The change removes a dt binding checker warning: mpwm@400e8000: #pwm-cells:0:0: 3 was expected Cc: Uwe Kleine-König Acked-by: Uwe Kleine-König Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 6cf405e9b082..916ab38f0a4c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -301,8 +301,8 @@ i2c2: i2c@400a8000 { mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + #pwm-cells = <3>; status = "disabled"; - #pwm-cells = <2>; }; }; From 2695035dc347a27f16268f8ab8e510a564c96d38 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:43 +0300 Subject: [PATCH 14/18] ARM: dts: lpc32xx: Correct motor PWM device tree node name Change once a customly selected 'mpwm' node name in favour of the expected 'pwm' one. The change eliminates a reported warning: mpwm@400e8000: $nodename:0: 'mpwm@400e8000' does not match '^pwm(@.*|-([0-9]|[1-9][0-9]+))?$' Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 916ab38f0a4c..761432673c39 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -298,7 +298,7 @@ i2c2: i2c@400a8000 { clocks = <&clk LPC32XX_CLK_I2C2>; }; - mpwm: mpwm@400e8000 { + mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; #pwm-cells = <3>; From 88f55f0a985e3d612c47e754b807a455b92db360 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:44 +0300 Subject: [PATCH 15/18] ARM: dts: lpc32xx: Correct SD/MMC controller device node name Change the PL180 SD/MMC controller device node name to the expected 'mmc' one. The change removes a reported warning: sd@20098000: $nodename:0: 'sd@20098000' does not match '^mmc(@.*)?$' Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 761432673c39..c8b9d70e9362 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -224,7 +224,7 @@ i2s0: i2s@20094000 { status = "disabled"; }; - sd: sd@20098000 { + sd: mmc@20098000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, From c4ceb7eeac34db30cd0c85b684b9ab26e9eb3cd2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:45 +0300 Subject: [PATCH 16/18] ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP The SD/MMC controller on NXP LPC32xx SoC is ARM PrimeCell PL180, it is reported by the driver: mmci-pl18x 20098000.sd: mmc0: PL180 manf 41 rev0 at 0x20098000 irq 36,37 (pio) Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index c8b9d70e9362..522d616a9205 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -225,7 +225,7 @@ i2s0: i2s@20094000 { }; sd: mmc@20098000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl180", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, <13 IRQ_TYPE_LEVEL_HIGH>; From 181ffb8b06848d7f1fd289d2497f5e134f55b09e Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:46 +0300 Subject: [PATCH 17/18] ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller For DMA controllers it is required to specify a number of the cells for users. The change eliminates the next build time reported warning: dma@31000000: '#dma-cells' is a required property Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 522d616a9205..a38f3c6dbe47 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -83,6 +83,7 @@ dma: dma@31000000 { interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_DMA>; clock-names = "apb_pclk"; + #dma-cells = <2>; }; usb { From d2dab63098bde9a6373eeb4672df806ad62a12da Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:47 +0300 Subject: [PATCH 18/18] ARM: dts: lpc32xx: Correct PL080 DMA controller device node name Rename PL080 DMA controller device node name to the expected one. The issue was reported by a dt binding checker: dma@31000000: $nodename:0: 'dma@31000000' does not match '^dma-controller(@.*)?$' Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index a38f3c6dbe47..2236901a0031 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -77,7 +77,7 @@ mlc: flash@200a8000 { status = "disabled"; }; - dma: dma@31000000 { + dma: dma-controller@31000000 { compatible = "arm,pl080", "arm,primecell"; reg = <0x31000000 0x1000>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;