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ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC

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Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able
to store the RTT time data.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/e8868ef06102241b47883ba10edaed751831be6d.1744666011.git.Ryan.Wanner@microchip.com
[claudiu.beznea: keep nodes sorted by their address]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This commit is contained in:
Ryan Wanner 2025-04-14 14:41:27 -07:00 committed by Claudiu Beznea
parent f5b56abe58
commit 4b3d951f28
1 changed files with 12 additions and 0 deletions
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12
arch/arm/boot/dts/microchip/sama7d65.dtsi
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@ -132,6 +132,13 @@ shdwc: poweroff@e001d200 {
status = "disabled";
};
rtt: rtc@e001d300 {
compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
reg = <0xe001d300 0x30>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk32k 0>;
};
clk32k: clock-controller@e001d500 {
compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
reg = <0xe001d500 0x4>;
@ -139,6 +146,11 @@ clk32k: clock-controller@e001d500 {
#clock-cells = <1>;
};
gpbr: syscon@e001d700 {
compatible = "microchip,sama7d65-gpbr", "syscon";
reg = <0xe001d700 0x48>;
};
rtc: rtc@e001d800 {
compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc";
reg = <0xe001d800 0x30>;