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ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support

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Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/354ecd628fdd292d2125570a6b10a93cbecb7706.1744666011.git.Ryan.Wanner@microchip.com
[claudiu.beznea: keep nodes sorted by their address]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This commit is contained in:
Ryan Wanner 2025-04-14 14:41:26 -07:00 committed by Claudiu Beznea
parent 0bbc54da32
commit f5b56abe58
1 changed files with 35 additions and 0 deletions
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35
arch/arm/boot/dts/microchip/sama7d65.dtsi
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@ -47,12 +47,37 @@ slow_xtal: clock-slowxtal {
};
};
ns_sram: sram@100000 {
compatible = "mmio-sram";
reg = <0x100000 0x20000>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
};
soc {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
securam: sram@e0000800 {
compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram";
reg = <0xe0000800 0x4000>;
ranges = <0 0xe0000800 0x4000>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
#address-cells = <1>;
#size-cells = <1>;
no-memory-wc;
};
secumod: security-module@e0004000 {
compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon";
reg = <0xe0004000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
};
sfrbu: sfr@e0008000 {
compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
reg = <0xe0008000 0x20>;
@ -526,6 +551,16 @@ i2c10: i2c@600 {
};
};
uddrc: uddrc@e3800000 {
compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
reg = <0xe3800000 0x4000>;
};
ddr3phy: ddr3phy@e3804000 {
compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
reg = <0xe3804000 0x1000>;
};
gic: interrupt-controller@e8c11000 {
compatible = "arm,cortex-a7-gic";
reg = <0xe8c11000 0x1000>,