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interconnect changes for 7.4

Browse Source 
This pull request contains the following interconnect updates for
 the 7.4-rc1 merge window:
 
 - New driver for Kuno SoC
 - Make important drivers default
 - Add multi-port QoS programming support
 - Add support for Milos OSM L3
 - Misc cleanups and fixes
 
 Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Merge tag 'icc-7.4-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next

Georgi writes:

interconnect changes for 7.4

This pull request contains the following interconnect updates for
the 7.4-rc1 merge window:

- New driver for Kuno SoC
- Make important drivers default
- Add multi-port QoS programming support
- Add support for Milos OSM L3
- Misc cleanups and fixes

Signed-off-by: Georgi Djakov <djakov@kernel.org>

* tag 'icc-7.4-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc: (21 commits)
  interconnect: mediatek: fix Makefile typo for mt8196
  interconnect: qcom: fix endian annotations of BCM aux data
  interconnect: qcom: Skip get_bw on QoS programming providers
  interconnect: qcom: use 64-bit SMD RPM bus votes
  interconnect: qcom: msm8976: Configure auxiliary GPU QoS port
  interconnect: qcom: msm8996: Configure auxiliary Venus QoS port
  interconnect: qcom: icc-rpm: Program SMD RPM auxiliary QoS ports
  interconnect: qcom: icc-rpm: Handle icc_link_create() failures
  interconnect: qcom: implement get_bw with rpmh_read
  interconnect: exynos: Remove the PM QoS request on unbind
  interconnect: Add kernel-doc for devm_of_icc_get(), icc_enable() and icc_disable()
  interconnect: qcom: icc-rpm: Don't skip small votes
  interconnect: qcom: Move bcm_div() to common code
  interconnect: fix typo "commited" in comments
  interconnect: qcom: Constify struct qcom_icc_qosbox
  interconnect: qcom: Add Kuno interconnect provider driver
  dt-bindings: interconnect: Add Qualcomm Kuno NoC
  dt-bindings: interconnect: OSM L3: Document Milos OSM L3 compatible
  interconnect: qcom: Add missing depends to Hawi, Maili, Nord and Shikra
  interconnect: qcom: Make important drivers default
  ...
This commit is contained in:
Greg Kroah-Hartman 2026-10-13 15:52:40 +02:00
commit 48671c0fac
22 changed files with 1608 additions and 155 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

118
Documentation/devicetree/bindings/interconnect/qcom,kuno-rpmh.yaml Normal file
View File

@ -0,0 +1,118 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,kuno-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on Kuno SoC
maintainers:
- Hardeep Sharma <hardeep.sharma@oss.qualcomm.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also: include/dt-bindings/interconnect/qcom,kuno.h
properties:
compatible:
enum:
- qcom,kuno-aggre-noc
- qcom,kuno-clk-virt
- qcom,kuno-cnoc-main
- qcom,kuno-dc-noc
- qcom,kuno-mc-virt
- qcom,kuno-mem-noc
- qcom,kuno-pcie-anoc
- qcom,kuno-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,kuno-clk-virt
- qcom,kuno-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
const: qcom,kuno-aggre-noc
then:
properties:
clocks:
items:
- description: System NoC USB SF AXI clock
- description: IPA clock
- if:
properties:
compatible:
contains:
const: qcom,kuno-system-noc
then:
properties:
clocks:
items:
- description: IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,kuno-aggre-noc
- qcom,kuno-system-noc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,kuno-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
clk_virt: interconnect-0 {
compatible = "qcom,kuno-clk-virt";
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre_noc: interconnect@1640000 {
compatible = "qcom,kuno-aggre-noc";
reg = <0x01640000 0x33400>;
clocks = <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
#interconnect-cells = <1>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
...

1
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
View File

@ -31,6 +31,7 @@ properties:
- items:
- enum:
- qcom,eliza-epss-l3
- qcom,milos-epss-l3
- qcom,sa8775p-epss-l3
- qcom,sc7280-epss-l3
- qcom,sc8280xp-epss-l3

32
drivers/interconnect/core.c
View File

@ -423,6 +423,17 @@ static void devm_icc_release(struct device *dev, void *res)
icc_put(*(struct icc_path **)res);
}
/**
* devm_of_icc_get() - get a path handle from a DT node based on name
* @dev: device pointer for the consumer device
* @name: interconnect path name
*
* This function is the resource managed version of of_icc_get(). The path
* is released with icc_put() automatically when @dev is unbound.
*
* Return: icc_path pointer on success or ERR_PTR() on error. NULL is returned
* when the API is disabled or the "interconnects" DT property is missing.
*/
struct icc_path *devm_of_icc_get(struct device *dev, const char *name)
{
struct icc_path **ptr, *path;
@ -786,12 +797,33 @@ static int __icc_enable(struct icc_path *path, bool enable)
path->reqs[0].peak_bw);
}
/**
* icc_enable() - enable a path
* @path: interconnect path
*
* Mark all requests on the path as enabled and reapply the bandwidth that
* was last set with icc_set_bw().
* Passing a NULL @path is a no-op and returns 0.
*
* Return: 0 on success, or an appropriate error code otherwise.
*/
int icc_enable(struct icc_path *path)
{
return __icc_enable(path, true);
}
EXPORT_SYMBOL_GPL(icc_enable);
/**
* icc_disable() - disable a path
* @path: interconnect path
*
* Mark all requests on the path as disabled, so that they no longer count
* towards the aggregated bandwidth, and reapply the constraints. The
* requested bandwidth is kept and restored by icc_enable().
* Passing a NULL @path is a no-op and returns 0.
*
* Return: 0 on success, or an appropriate error code otherwise.
*/
int icc_disable(struct icc_path *path)
{
return __icc_enable(path, false);

2
drivers/interconnect/mediatek/Makefile
View File

@ -3,4 +3,4 @@
obj-$(CONFIG_INTERCONNECT_MTK_DVFSRC_EMI) += icc-emi.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8183) += mt8183.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8195) += mt8195.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8195) += mt8196.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8196) += mt8196.o

57
drivers/interconnect/qcom/Kconfig
View File

@ -2,6 +2,7 @@
config INTERCONNECT_QCOM
tristate "Qualcomm Network-on-Chip interconnect drivers"
depends on ARCH_QCOM || COMPILE_TEST
default ARCH_QCOM
help
Support for Qualcomm's Network-on-Chip interconnect hardware.
@ -14,6 +15,7 @@ config INTERCONNECT_QCOM_ELIZA
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on Eliza-based
platforms.
@ -24,6 +26,7 @@ config INTERCONNECT_QCOM_GLYMUR
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on glymur-based
platforms.
@ -31,8 +34,10 @@ config INTERCONNECT_QCOM_GLYMUR
config INTERCONNECT_QCOM_HAWI
tristate "Qualcomm HAWI interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on hawi-based
platforms.
@ -43,13 +48,28 @@ config INTERCONNECT_QCOM_KAANAPALI
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on kaanapali-based
platforms.
config INTERCONNECT_QCOM_KUNO
tristate "Qualcomm Kuno interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
depends on ARM || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on kuno-based
platforms. The interconnect provider collects and aggregates the
consumer bandwidth requests to satisfy constraints placed on the
Network-on-Chip performance states.
config INTERCONNECT_QCOM_MAILI
tristate "Qualcomm MAILI interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
@ -72,6 +92,7 @@ config INTERCONNECT_QCOM_MSM8916
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM if ARM64
help
This is a driver for the Qualcomm Network-on-Chip on msm8916-based
platforms.
@ -100,6 +121,7 @@ config INTERCONNECT_QCOM_MSM8953
depends on QCOM_SMD_RPM
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on msm8953-based
platforms.
@ -110,6 +132,7 @@ config INTERCONNECT_QCOM_MSM8974
depends on QCOM_SMD_RPM
depends on ARM || COMPILE_TEST
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on msm8974-based
platforms.
@ -130,6 +153,7 @@ config INTERCONNECT_QCOM_MSM8996
depends on QCOM_SMD_RPM
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on msm8996-based
platforms.
@ -137,8 +161,10 @@ config INTERCONNECT_QCOM_MSM8996
config INTERCONNECT_QCOM_NORD
tristate "Qualcomm Nord interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on Nord-based
platforms. The topology consists of several NoCs controlled by
@ -149,6 +175,7 @@ config INTERCONNECT_QCOM_OSM_L3
tristate "Qualcomm OSM L3 interconnect driver"
depends on INTERCONNECT_QCOM || COMPILE_TEST
depends on ARM64 || COMPILE_TEST
default ARCH_QCOM
help
Say y here to support the Operating State Manager (OSM) interconnect
driver which controls the scaling of L3 caches on Qualcomm SoCs.
@ -159,6 +186,7 @@ config INTERCONNECT_QCOM_QCM2290
depends on QCOM_SMD_RPM
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on qcm2290-based
platforms.
@ -169,6 +197,7 @@ config INTERCONNECT_QCOM_QCS404
depends on QCOM_SMD_RPM
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on qcs404-based
platforms.
@ -179,6 +208,7 @@ config INTERCONNECT_QCOM_QCS615
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on qcs615-based
platforms.
@ -189,6 +219,7 @@ config INTERCONNECT_QCOM_QCS8300
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Technologies, Inc. Network-on-Chip
on QCS8300-based platforms. The interconnect provider collects and
@ -201,6 +232,7 @@ config INTERCONNECT_QCOM_QDU1000
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on QDU1000-based
and QRU1000-based platforms.
@ -225,6 +257,7 @@ config INTERCONNECT_QCOM_SA8775P
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sa8775p-based
platforms.
@ -235,6 +268,7 @@ config INTERCONNECT_QCOM_SAR2130P
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on SAR2130P-based
platforms.
@ -245,6 +279,7 @@ config INTERCONNECT_QCOM_SC7180
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sc7180-based
platforms.
@ -255,6 +290,7 @@ config INTERCONNECT_QCOM_SC7280
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sc7280-based
platforms.
@ -265,6 +301,7 @@ config INTERCONNECT_QCOM_SC8180X
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sc8180x-based
platforms.
@ -275,6 +312,7 @@ config INTERCONNECT_QCOM_SC8280XP
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on SC8280XP-based
platforms.
@ -285,6 +323,7 @@ config INTERCONNECT_QCOM_SDM660
depends on ARM64 || COMPILE_TEST
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sdm660-based
platforms.
@ -295,6 +334,7 @@ config INTERCONNECT_QCOM_SDM670
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sdm670-based
platforms.
@ -305,6 +345,7 @@ config INTERCONNECT_QCOM_SDM845
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sdm845-based
platforms.
@ -315,6 +356,7 @@ config INTERCONNECT_QCOM_SDX55
depends on ARM || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sdx55-based
platforms.
@ -335,6 +377,7 @@ config INTERCONNECT_QCOM_SDX75
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sdx75-based
platforms.
@ -343,6 +386,8 @@ config INTERCONNECT_QCOM_SHIKRA
tristate "Qualcomm SHIKRA interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
depends on ARM64 || COMPILE_TEST
default ARCH_QCOM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on shikra-based
@ -354,6 +399,7 @@ config INTERCONNECT_QCOM_SM6115
depends on QCOM_SMD_RPM
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_SMD_RPM
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sm6115-based
platforms.
@ -364,6 +410,7 @@ config INTERCONNECT_QCOM_SM6350
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sm6350-based
platforms.
@ -374,6 +421,7 @@ config INTERCONNECT_QCOM_SM7150
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sm7150-based
platforms.
@ -384,6 +432,7 @@ config INTERCONNECT_QCOM_MILOS
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on Milos-based
platforms.
@ -394,6 +443,7 @@ config INTERCONNECT_QCOM_SM8150
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sm8150-based
platforms.
@ -404,6 +454,7 @@ config INTERCONNECT_QCOM_SM8250
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on sm8250-based
platforms.
@ -414,6 +465,7 @@ config INTERCONNECT_QCOM_SM8350
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on SM8350-based
platforms.
@ -424,6 +476,7 @@ config INTERCONNECT_QCOM_SM8450
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on SM8450-based
platforms.
@ -434,6 +487,7 @@ config INTERCONNECT_QCOM_SM8550
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on SM8550-based
platforms.
@ -444,6 +498,7 @@ config INTERCONNECT_QCOM_SM8650
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on SM8650-based
platforms.
@ -454,6 +509,7 @@ config INTERCONNECT_QCOM_SM8750
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on SM8750-based
platforms.
@ -464,6 +520,7 @@ config INTERCONNECT_QCOM_X1E80100
depends on ARM64 || COMPILE_TEST
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
default ARCH_QCOM
help
This is a driver for the Qualcomm Network-on-Chip on X1E80100-based
platforms.

2
drivers/interconnect/qcom/Makefile
View File

@ -8,6 +8,7 @@ qnoc-eliza-objs := eliza.o
qnoc-glymur-objs := glymur.o
qnoc-hawi-objs := hawi.o
qnoc-kaanapali-objs := kaanapali.o
qnoc-kuno-objs := kuno.o
qnoc-maili-objs := maili.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
@ -57,6 +58,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) += qnoc-eliza.o
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) += qnoc-hawi.o
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
obj-$(CONFIG_INTERCONNECT_QCOM_KUNO) += qnoc-kuno.o
obj-$(CONFIG_INTERCONNECT_QCOM_MAILI) += qnoc-maili.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o

59
drivers/interconnect/qcom/bcm-voter.c
View File

@ -3,7 +3,6 @@
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <asm/div64.h>
#include <linux/interconnect-provider.h>
#include <linux/list_sort.h>
#include <linux/module.h>
@ -14,6 +13,7 @@
#include <soc/qcom/tcs.h>
#include "bcm-voter.h"
#include "icc-common.h"
#include "icc-rpmh.h"
static LIST_HEAD(bcm_voters);
@ -47,17 +47,6 @@ static int cmp_vcd(void *priv, const struct list_head *a, const struct list_head
return bcm_a->aux_data.vcd - bcm_b->aux_data.vcd;
}
static u64 bcm_div(u64 num, u32 base)
{
/* Ensure that small votes aren't lost. */
if (num && num < base)
return 1;
do_div(num, base);
return num;
}
/* BCMs with enable_mask use one-hot-encoding for on/off signaling */
static void bcm_aggregate_mask(struct qcom_icc_bcm *bcm)
{
@ -99,20 +88,20 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
for (bucket = 0; bucket < QCOM_ICC_NUM_BUCKETS; bucket++) {
for (i = 0; i < bcm->num_nodes; i++) {
node = bcm->nodes[i];
temp = bcm_div(node->sum_avg[bucket] * bcm->aux_data.width,
node->buswidth * node->channels);
temp = qcom_bw_div(node->sum_avg[bucket] * le16_to_cpu(bcm->aux_data.width),
node->buswidth * node->channels);
agg_avg[bucket] = max(agg_avg[bucket], temp);
temp = bcm_div(node->max_peak[bucket] * bcm->aux_data.width,
node->buswidth);
temp = qcom_bw_div(node->max_peak[bucket] * le16_to_cpu(bcm->aux_data.width),
node->buswidth);
agg_peak[bucket] = max(agg_peak[bucket], temp);
}
temp = agg_avg[bucket] * bcm->vote_scale;
bcm->vote_x[bucket] = bcm_div(temp, bcm->aux_data.unit);
bcm->vote_x[bucket] = qcom_bw_div(temp, le32_to_cpu(bcm->aux_data.unit));
temp = agg_peak[bucket] * bcm->vote_scale;
bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
bcm->vote_y[bucket] = qcom_bw_div(temp, le32_to_cpu(bcm->aux_data.unit));
}
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
@ -261,6 +250,40 @@ void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm)
}
EXPORT_SYMBOL_GPL(qcom_icc_bcm_voter_add);
/**
* qcom_icc_bcm_get_bw - get current bcm vote
* @voter: voter used to query bcm
* @bcm: bcm to get current vote from
*/
void qcom_icc_bcm_get_bw(struct bcm_voter *voter,
struct qcom_icc_bcm *bcm)
{
struct tcs_cmd cmd = { .addr = bcm->addr };
int ret, i;
u64 x, y;
mutex_lock(&voter->lock);
ret = rpmh_read(voter->dev, &cmd);
if (ret) {
pr_err("Error sending AMC RPMH requests (%d)\n", ret);
goto out;
}
x = FIELD_GET(BCM_TCS_CMD_VOTE_X_MASK, cmd.data);
y = FIELD_GET(BCM_TCS_CMD_VOTE_Y_MASK, cmd.data);
/* For boot-up, fill the AMC vote in all buckets */
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
bcm->vote_x[i] = x;
bcm->vote_y[i] = y;
}
out:
mutex_unlock(&voter->lock);
}
EXPORT_SYMBOL_GPL(qcom_icc_bcm_get_bw);
/**
* qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms
* @voter: voter that needs flushing

1
drivers/interconnect/qcom/bcm-voter.h
View File

@ -13,6 +13,7 @@
#include "icc-rpmh.h"
struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name);
void qcom_icc_bcm_get_bw(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);
void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);
int qcom_icc_bcm_voter_commit(struct bcm_voter *voter);

18
drivers/interconnect/qcom/eliza.c
View File

@ -451,7 +451,7 @@ static struct qcom_icc_node qns_gem_noc_cnoc = {
.link_nodes = { &qnm_gemnoc_cnoc },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0x155000 },
.prio = 1,
@ -468,7 +468,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0x157000 },
.prio = 6,
@ -494,7 +494,7 @@ static struct qcom_icc_node chm_apps = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_gpu_qos = {
static const struct qcom_icc_qosbox qnm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x31000, 0xb1000 },
.prio = 0,
@ -511,7 +511,7 @@ static struct qcom_icc_node qnm_gpu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
.num_ports = 1,
.port_offsets = { 0x159000 },
.prio = 0,
@ -538,7 +538,7 @@ static struct qcom_icc_node qnm_mdsp = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0xb3000 },
.prio = 0,
@ -555,7 +555,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x35000, 0xb5000 },
.prio = 0,
@ -572,7 +572,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
.num_ports = 2,
.port_offsets = { 0x37000, 0xb7000 },
.prio = 0,
@ -590,7 +590,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_pcie_qos = {
static const struct qcom_icc_qosbox qnm_pcie_qos = {
.num_ports = 1,
.port_offsets = { 0x15b000 },
.prio = 2,
@ -688,7 +688,7 @@ static struct qcom_icc_node qnm_lpiaon_noc = {
.link_nodes = { &qns_lpass_ag_noc_gemnoc },
};
static struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x25000 },
.prio = 4,

9
drivers/interconnect/qcom/icc-common.h
View File

@ -7,6 +7,15 @@
#define __DRIVERS_INTERCONNECT_QCOM_ICC_COMMON_H__
#include <linux/interconnect-provider.h>
#include <linux/math64.h>
static inline u64 qcom_bw_div(u64 num, u32 base)
{
if (num && num < base)
return 1;
return div_u64(num, base);
}
struct icc_node_data *qcom_icc_xlate_extended(const struct of_phandle_args *spec,
void *data);

105
drivers/interconnect/qcom/icc-rpm.c
View File

@ -58,15 +58,32 @@ static int qcom_icc_set_qnoc_qos(struct icc_node *src)
struct qcom_icc_qos *qos = &qn->qos;
int rc;
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
QNOC_QOS_MCTL_DFLT_PRIO_MASK,
qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT);
if (rc)
return rc;
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
QNOC_QOS_MCTL_DFLT_PRIO_MASK,
qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT);
QNOC_QOS_MCTL_URGFWD_EN_MASK,
!!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT);
if (rc)
return rc;
if (!qos->aux_qos_port)
return 0;
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->aux_qos_port),
QNOC_QOS_MCTL_DFLT_PRIO_MASK,
qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT);
if (rc)
return rc;
return regmap_update_bits(qp->regmap,
qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->aux_qos_port),
QNOC_QOS_MCTL_URGFWD_EN_MASK,
!!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT);
}
@ -75,8 +92,9 @@ static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp,
struct qcom_icc_qos *qos,
int regnum)
{
u32 val;
u32 mask;
u32 val;
int ret;
val = qos->prio_level;
mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK;
@ -90,8 +108,17 @@ static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp,
mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK;
}
ret = regmap_update_bits(qp->regmap,
qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
mask, val);
if (ret)
return ret;
if (!qos->aux_qos_port)
return 0;
return regmap_update_bits(qp->regmap,
qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->aux_qos_port),
mask, val);
}
@ -102,7 +129,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src)
struct icc_provider *provider;
u32 mode = NOC_QOS_MODE_BYPASS;
u32 val = 0;
int i, rc = 0;
int i, rc;
qn = src->data;
provider = src->provider;
@ -116,8 +143,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src)
*/
if (mode != NOC_QOS_MODE_BYPASS) {
for (i = 3; i >= 0; i--) {
rc = qcom_icc_bimc_set_qos_health(qp,
&qn->qos, i);
rc = qcom_icc_bimc_set_qos_health(qp, &qn->qos, i);
if (rc)
return rc;
}
@ -126,8 +152,17 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src)
val = 1;
}
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port),
M_BKE_EN_EN_BMASK, val);
if (rc)
return rc;
if (!qn->qos.aux_qos_port)
return 0;
return regmap_update_bits(qp->regmap,
qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port),
qp->qos_offset + M_BKE_EN_ADDR(qn->qos.aux_qos_port),
M_BKE_EN_EN_BMASK, val);
}
@ -145,8 +180,24 @@ static int qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp,
if (rc)
return rc;
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
NOC_QOS_PRIORITY_P0_MASK, qos->prio_level);
if (rc)
return rc;
if (!qos->aux_qos_port)
return 0;
val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->aux_qos_port),
NOC_QOS_PRIORITY_P1_MASK, val);
if (rc)
return rc;
return regmap_update_bits(qp->regmap,
qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->aux_qos_port),
NOC_QOS_PRIORITY_P0_MASK, qos->prio_level);
}
@ -182,8 +233,17 @@ static int qcom_icc_set_noc_qos(struct icc_node *src)
/* How did we get here? */
}
rc = regmap_update_bits(qp->regmap,
qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
NOC_QOS_MODEn_MASK, mode);
if (rc)
return rc;
if (!qn->qos.aux_qos_port)
return 0;
return regmap_update_bits(qp->regmap,
qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.aux_qos_port),
NOC_QOS_MODEn_MASK, mode);
}
@ -298,25 +358,25 @@ static u64 qcom_icc_calc_rate(struct qcom_icc_provider *qp, struct qcom_icc_node
u64 agg_avg_rate, agg_peak_rate, agg_rate;
if (qn->channels)
agg_avg_rate = div_u64(qn->sum_avg[ctx], qn->channels);
agg_avg_rate = qcom_bw_div(qn->sum_avg[ctx], qn->channels);
else
agg_avg_rate = qn->sum_avg[ctx];
if (qn->ab_coeff) {
agg_avg_rate = agg_avg_rate * qn->ab_coeff;
agg_avg_rate = div_u64(agg_avg_rate, 100);
agg_avg_rate = qcom_bw_div(agg_avg_rate, 100);
}
if (qn->ib_coeff) {
agg_peak_rate = qn->max_peak[ctx] * 100;
agg_peak_rate = div_u64(agg_peak_rate, qn->ib_coeff);
agg_peak_rate = qcom_bw_div(agg_peak_rate, qn->ib_coeff);
} else {
agg_peak_rate = qn->max_peak[ctx];
}
agg_rate = max_t(u64, agg_avg_rate, agg_peak_rate);
return div_u64(agg_rate, qn->buswidth);
return qcom_bw_div(agg_rate, qn->buswidth);
}
/**
@ -402,7 +462,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
if (ret)
return ret;
/* Cache the rate after we've successfully commited it to RPM */
/* Cache the rate after we've successfully committed it to RPM */
qp->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate;
}
@ -412,7 +472,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
if (ret)
return ret;
/* Cache the rate after we've successfully commited it to RPM */
/* Cache the rate after we've successfully committed it to RPM */
qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate;
}
@ -583,8 +643,15 @@ int qnoc_probe(struct platform_device *pdev)
node->data = qnodes[i];
icc_node_add(node, provider);
for (j = 0; j < qnodes[i]->num_links; j++)
icc_link_create(node, qnodes[i]->links[j]);
for (j = 0; j < qnodes[i]->num_links; j++) {
ret = icc_link_create(node, qnodes[i]->links[j]);
if (ret) {
icc_nodes_remove(provider);
clk_bulk_disable_unprepare(qp->num_intf_clks,
qp->intf_clks);
goto err_disable_unprepare_clk;
}
}
/* Set QoS registers (we only need to do it once, generally) */
if (qnodes[i]->qos.ap_owned &&

6
drivers/interconnect/qcom/icc-rpm.h
View File

@ -30,7 +30,7 @@ enum qcom_icc_type {
* @resource_type: RPM resource type of the clock resource
* @clock_id: index of the clock resource of a specific resource type
* @branch: whether the resource represents a branch clock
*/
*/
struct rpm_clk_resource {
u32 resource_type;
u32 clock_id;
@ -77,6 +77,7 @@ struct qcom_icc_provider {
* @ap_owned: indicates if the node is owned by the AP or by the RPM
* @qos_mode: default qos mode for this node
* @qos_port: qos port number for finding qos registers of this node
* @aux_qos_port: optional QoS port in addition to @qos_port. Zero means "none".
* @urg_fwd_en: enable urgent forwarding
*/
struct qcom_icc_qos {
@ -86,6 +87,7 @@ struct qcom_icc_qos {
bool ap_owned;
int qos_mode;
int qos_port;
u16 aux_qos_port;
bool urg_fwd_en;
};
@ -167,7 +169,7 @@ int qnoc_probe(struct platform_device *pdev);
void qnoc_remove(struct platform_device *pdev);
bool qcom_icc_rpm_smd_available(void);
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u64 val);
int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, int ctx, u32 rate);
#endif

71
drivers/interconnect/qcom/icc-rpmh.c
View File

@ -136,6 +136,61 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
}
EXPORT_SYMBOL_GPL(qcom_icc_set);
static int qcom_icc_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
{
struct qcom_icc_node *qn = node->data;
u32 avg_max = 0;
u32 peak_max = 0;
u64 x, y;
int i;
if (!qn->num_bcms) {
*avg = INT_MAX;
*peak = INT_MAX;
return 0;
}
for (i = 0; i < qn->num_bcms; ++i) {
struct qcom_icc_bcm *bcm = qn->bcms[i];
/* Use AMC vote for boot-up */
x = bcm->vote_x[QCOM_ICC_BUCKET_AMC];
y = bcm->vote_y[QCOM_ICC_BUCKET_AMC];
/* Consider enable mask and convert to INT_MAX */
if (bcm->enable_mask) {
if (x & bcm->enable_mask)
avg_max = INT_MAX;
if (y & bcm->enable_mask)
peak_max = INT_MAX;
} else {
if (x) {
x *= le32_to_cpu(bcm->aux_data.unit);
do_div(x, bcm->vote_scale);
x *= qn->buswidth * qn->channels;
do_div(x, le16_to_cpu(bcm->aux_data.width));
avg_max = max(avg_max, x);
}
if (y) {
y *= le32_to_cpu(bcm->aux_data.unit);
do_div(y, bcm->vote_scale);
y *= qn->buswidth;
do_div(y, le16_to_cpu(bcm->aux_data.width));
peak_max = max(peak_max, y);
}
}
}
*avg = avg_max;
*peak = peak_max;
return 0;
}
/**
* qcom_icc_bcm_init - populates bcm aux data and connect qnodes
* @bcm: bcm to be initialized
@ -173,10 +228,7 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
return -EINVAL;
}
bcm->aux_data.unit = le32_to_cpu(data->unit);
bcm->aux_data.width = le16_to_cpu(data->width);
bcm->aux_data.vcd = data->vcd;
bcm->aux_data.reserved = data->reserved;
bcm->aux_data = *data;
INIT_LIST_HEAD(&bcm->list);
INIT_LIST_HEAD(&bcm->ws_list);
@ -255,6 +307,13 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
provider = &qp->provider;
provider->dev = dev;
provider->set = qcom_icc_set;
/*
* Programming the QoS registers below requires the NoC to be clocked,
* which during probe is only guaranteed by the INT_MAX initial votes
* the interconnect core applies when get_bw() is absent.
*/
if (!desc->config)
provider->get_bw = qcom_icc_get_bw;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate;
provider->xlate_extended = qcom_icc_xlate_extended;
@ -272,8 +331,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
if (IS_ERR(qp->voter))
return PTR_ERR(qp->voter);
for (i = 0; i < qp->num_bcms; i++)
for (i = 0; i < qp->num_bcms; i++) {
qcom_icc_bcm_init(qp->bcms[i], dev);
qcom_icc_bcm_get_bw(qp->voter, qp->bcms[i]);
}
for (i = 0; i < num_nodes; i++) {
qn = qnodes[i];

988
drivers/interconnect/qcom/kuno.c Normal file
View File

@ -0,0 +1,988 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/interconnect/qcom,kuno.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ahb2_phy = {
.name = "qhs_ahb2_phy",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_audio = {
.name = "qhs_audio",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_mxa = {
.name = "qhs_cpr_mxa",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_mxc = {
.name = "qhs_cpr_mxc",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_crypto_cfg = {
.name = "qhs_crypto_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_emac0_cfg = {
.name = "qhs_emac0_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie_rscc = {
.name = "qhs_pcie_rscc",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
.name = "qhs_pmu_wrapper_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qpic = {
.name = "qhs_qpic",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_spmi_vgi_coex = {
.name = "qhs_spmi_vgi_coex",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tme_cfg = {
.name = "qhs_tme_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_usb3 = {
.name = "qhs_usb3",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qss_anoc_throttle_cfg = {
.name = "qss_anoc_throttle_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qhs_lagg = {
.name = "qhs_lagg",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mccc_master = {
.name = "qhs_mccc_master",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node srvc_memnoc = {
.name = "srvc_memnoc",
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qup0_core_slave },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
.channels = 1,
.buswidth = 4,
.num_links = 2,
.link_nodes = { &qhs_lagg, &qhs_mccc_master },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &ebi },
};
static struct qcom_icc_node qnm_memnoc_cfg = {
.name = "qnm_memnoc_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &srvc_memnoc },
};
static struct qcom_icc_node qnm_memnoc_pcie = {
.name = "qnm_memnoc_pcie",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &xs_pcie_0 },
};
static struct qcom_icc_node xm_ipa2pcie = {
.name = "xm_ipa2pcie",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &xs_pcie_0 },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qnm_cnoc },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.channels = 1,
.buswidth = 16,
.num_links = 1,
.link_nodes = { &llcc_mc },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_memnoc_pcie },
};
static struct qcom_icc_node qhm_pcie_rscc = {
.name = "qhm_pcie_rscc",
.channels = 1,
.buswidth = 4,
.num_links = 34,
.link_nodes = { &qhs_ahb2_phy, &qhs_aoss,
&qhs_apss, &qhs_audio,
&qhs_clk_ctl, &qhs_cpr_cx,
&qhs_cpr_mxa, &qhs_cpr_mxc,
&qhs_crypto_cfg, &qhs_emac0_cfg,
&qhs_imem_cfg, &qhs_ipa,
&qhs_ipc_router, &qhs_mss_cfg,
&qhs_pcie0_cfg, &qhs_pdm,
&qhs_pmu_wrapper_cfg, &qhs_prng,
&qhs_qdss_cfg, &qhs_qpic,
&qhs_qup0, &qhs_sdc4,
&qhs_spmi_vgi_coex, &qhs_tcsr,
&qhs_tlmm, &qhs_tme_cfg,
&qhs_usb3, &qhs_vsense_ctrl_cfg,
&qns_ddrss_cfg, &qss_anoc_throttle_cfg,
&qxs_boot_imem, &qxs_imem,
&xs_qdss_stm, &xs_sys_tcu_cfg },
};
static struct qcom_icc_node qnm_memnoc_cnoc = {
.name = "qnm_memnoc_cnoc",
.channels = 1,
.buswidth = 8,
.num_links = 35,
.link_nodes = { &qhs_ahb2_phy, &qhs_aoss,
&qhs_apss, &qhs_audio,
&qhs_clk_ctl, &qhs_cpr_cx,
&qhs_cpr_mxa, &qhs_cpr_mxc,
&qhs_crypto_cfg, &qhs_emac0_cfg,
&qhs_imem_cfg, &qhs_ipa,
&qhs_ipc_router, &qhs_mss_cfg,
&qhs_pcie0_cfg, &qhs_pcie_rscc,
&qhs_pdm, &qhs_pmu_wrapper_cfg,
&qhs_prng, &qhs_qdss_cfg,
&qhs_qpic, &qhs_qup0,
&qhs_sdc4, &qhs_spmi_vgi_coex,
&qhs_tcsr, &qhs_tlmm,
&qhs_tme_cfg, &qhs_usb3,
&qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
&qss_anoc_throttle_cfg, &qxs_boot_imem,
&qxs_imem, &xs_qdss_stm,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_node qns_memnoc_cnoc = {
.name = "qns_memnoc_cnoc",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_memnoc_cnoc },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc },
};
static struct qcom_icc_node qnm_mdsp = {
.name = "qnm_mdsp",
.channels = 1,
.buswidth = 8,
.num_links = 3,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc,
&qns_pcie },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc },
};
static struct qcom_icc_node xm_apps0 = {
.name = "xm_apps0",
.channels = 1,
.buswidth = 16,
.num_links = 3,
.link_nodes = { &qns_llcc, &qns_memnoc_cnoc,
&qns_pcie },
};
static struct qcom_icc_node qns_pcie_memnoc = {
.name = "qns_pcie_memnoc",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_pcie },
};
static struct qcom_icc_node qns_memnoc_sf = {
.name = "qns_memnoc_sf",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_pcie_memnoc },
};
static struct qcom_icc_node qhm_cpucp = {
.name = "qhm_cpucp",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_memnoc_sf },
};
static struct qcom_icc_node qnm_aggre_noc = {
.name = "qnm_aggre_noc",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
.channels = 1,
.buswidth = 4,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qxm_mss_nav_ce = {
.name = "qxm_mss_nav_ce",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qxm_tme = {
.name = "qxm_tme",
.channels = 1,
.buswidth = 8,
.num_links = 2,
.link_nodes = { &qns_memnoc_sf, &xs_pcie_0 },
};
static struct qcom_icc_node qns_a1noc = {
.name = "qns_a1noc",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qnm_aggre_noc },
};
static struct qcom_icc_node qns_snoc_datapath = {
.name = "qns_snoc_datapath",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qnm_cnoc_datapath },
};
static struct qcom_icc_node qhm_audio = {
.name = "qhm_audio",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qpic = {
.name = "qhm_qpic",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.channels = 1,
.buswidth = 4,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_etr0 = {
.name = "xm_qdss_etr0",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_etr1 = {
.name = "xm_qdss_etr1",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_usb3 = {
.name = "xm_usb3",
.channels = 1,
.buswidth = 8,
.num_links = 1,
.link_nodes = { &qns_a1noc },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
.channels = 1,
.buswidth = 8,
.num_links = 36,
.link_nodes = { &qhs_ahb2_phy, &qhs_aoss,
&qhs_apss, &qhs_audio,
&qhs_clk_ctl, &qhs_cpr_cx,
&qhs_cpr_mxa, &qhs_cpr_mxc,
&qhs_crypto_cfg, &qhs_emac0_cfg,
&qhs_imem_cfg, &qhs_ipa,
&qhs_ipc_router, &qhs_mss_cfg,
&qhs_pcie0_cfg, &qhs_pcie_rscc,
&qhs_pdm, &qhs_pmu_wrapper_cfg,
&qhs_prng, &qhs_qdss_cfg,
&qhs_qpic, &qhs_qup0,
&qhs_sdc4, &qhs_spmi_vgi_coex,
&qhs_tcsr, &qhs_tlmm,
&qhs_tme_cfg, &qhs_usb3,
&qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
&qns_snoc_datapath, &qss_anoc_throttle_cfg,
&qxs_boot_imem, &qxs_imem,
&xs_qdss_stm, &xs_sys_tcu_cfg },
};
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = 0x8,
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
.enable_mask = 0x1,
.num_nodes = 39,
.nodes = { &qhm_pcie_rscc, &qnm_memnoc_cnoc,
&xm_qdss_dap, &qhs_ahb2_phy,
&qhs_aoss, &qhs_apss,
&qhs_audio, &qhs_clk_ctl,
&qhs_cpr_cx, &qhs_cpr_mxa,
&qhs_cpr_mxc, &qhs_crypto_cfg,
&qhs_emac0_cfg, &qhs_imem_cfg,
&qhs_ipa, &qhs_ipc_router,
&qhs_mss_cfg, &qhs_pcie0_cfg,
&qhs_pcie_rscc, &qhs_pdm,
&qhs_pmu_wrapper_cfg, &qhs_prng,
&qhs_qdss_cfg, &qhs_qpic,
&qhs_qup0, &qhs_sdc4,
&qhs_spmi_vgi_coex, &qhs_tcsr,
&qhs_tlmm, &qhs_tme_cfg,
&qhs_usb3, &qhs_vsense_ctrl_cfg,
&qns_ddrss_cfg, &qns_snoc_datapath,
&qss_anoc_throttle_cfg, &qxs_boot_imem,
&qxs_imem, &xs_qdss_stm,
&xs_sys_tcu_cfg },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.vote_scale = 1,
.num_nodes = 1,
.nodes = { &qup0_core_slave },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_llcc },
};
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
.enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qns_memnoc_cnoc, &qns_pcie },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_memnoc_sf },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &xm_pcie3_0 },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.num_nodes = 2,
.nodes = { &qns_a1noc, &qnm_aggre_noc },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.num_nodes = 1,
.nodes = { &qxm_mss_nav_ce },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.num_nodes = 1,
.nodes = { &xs_pcie_0 },
};
static struct qcom_icc_bcm * const aggre_noc_bcms[] = {
&bcm_ce0,
};
static struct qcom_icc_node * const aggre_noc_nodes[] = {
[MASTER_AUDIO] = &qhm_audio,
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_QPIC] = &qhm_qpic,
[MASTER_QUP_0] = &qhm_qup0,
[MASTER_CRYPTO] = &qxm_crypto,
[MASTER_IPA] = &qxm_ipa,
[MASTER_EMAC] = &xm_emac_0,
[MASTER_QDSS_ETR] = &xm_qdss_etr0,
[MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
[MASTER_SDCC_4] = &xm_sdc4,
[MASTER_USB3_0] = &xm_usb3,
[SLAVE_A1NOC_CFG] = &qns_a1noc,
};
static const struct qcom_icc_desc kuno_aggre_noc = {
.nodes = aggre_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre_noc_nodes),
.bcms = aggre_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre_noc_bcms),
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
&bcm_qup0,
};
static struct qcom_icc_node * const clk_virt_nodes[] = {
[MASTER_QUP_CORE_0] = &qup0_core_master,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
};
static const struct qcom_icc_desc kuno_clk_virt = {
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
};
static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
&bcm_cn0,
};
static struct qcom_icc_node * const cnoc_main_nodes[] = {
[MASTER_PCIE_RSCC] = &qhm_pcie_rscc,
[MASTER_GEM_NOC_CNOC] = &qnm_memnoc_cnoc,
[MASTER_QDSS_DAP] = &xm_qdss_dap,
[SLAVE_AHB2PHY] = &qhs_ahb2_phy,
[SLAVE_AOSS] = &qhs_aoss,
[SLAVE_APPSS] = &qhs_apss,
[SLAVE_AUDIO] = &qhs_audio,
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
[SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
[SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
[SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
[SLAVE_IPA_CFG] = &qhs_ipa,
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
[SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc,
[SLAVE_PDM] = &qhs_pdm,
[SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
[SLAVE_PRNG] = &qhs_prng,
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
[SLAVE_QPIC] = &qhs_qpic,
[SLAVE_QUP_0] = &qhs_qup0,
[SLAVE_SDCC_4] = &qhs_sdc4,
[SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
[SLAVE_TCSR] = &qhs_tcsr,
[SLAVE_TLMM] = &qhs_tlmm,
[SLAVE_TME_CFG] = &qhs_tme_cfg,
[SLAVE_USB3] = &qhs_usb3,
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
[SLAVE_SNOC_CNOC] = &qns_snoc_datapath,
[SLAVE_ANOC_THROTTLE_CFG] = &qss_anoc_throttle_cfg,
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
[SLAVE_IMEM] = &qxs_imem,
[SLAVE_QDSS_STM] = &xs_qdss_stm,
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
static const struct qcom_icc_desc kuno_cnoc_main = {
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
.num_bcms = ARRAY_SIZE(cnoc_main_bcms),
};
static struct qcom_icc_node * const dc_noc_nodes[] = {
[MASTER_CNOC_DC_NOC] = &qnm_cnoc,
[SLAVE_LAGG_CFG] = &qhs_lagg,
[SLAVE_MCCC_MASTER] = &qhs_mccc_master,
};
static const struct qcom_icc_desc kuno_dc_noc = {
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
};
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
};
static struct qcom_icc_node * const mc_virt_nodes[] = {
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI1] = &ebi,
};
static const struct qcom_icc_desc kuno_mc_virt = {
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
};
static struct qcom_icc_bcm * const mem_noc_bcms[] = {
&bcm_sh0,
&bcm_sh1,
};
static struct qcom_icc_node * const mem_noc_nodes[] = {
[MASTER_SYS_TCU] = &alm_sys_tcu,
[MASTER_MSS_PROC] = &qnm_mdsp,
[MASTER_GEM_NOC_CFG] = &qnm_memnoc_cfg,
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
[MASTER_APPSS_PROC] = &xm_apps0,
[SLAVE_LLCC] = &qns_llcc,
[SLAVE_GEM_NOC_CNOC] = &qns_memnoc_cnoc,
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
[SLAVE_SERVICE_GEM_NOC] = &srvc_memnoc,
};
static const struct qcom_icc_desc kuno_mem_noc = {
.nodes = mem_noc_nodes,
.num_nodes = ARRAY_SIZE(mem_noc_nodes),
.bcms = mem_noc_bcms,
.num_bcms = ARRAY_SIZE(mem_noc_bcms),
};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
&bcm_sn1,
};
static struct qcom_icc_node * const pcie_anoc_nodes[] = {
[MASTER_PCIE_0] = &xm_pcie3_0,
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_memnoc,
};
static const struct qcom_icc_desc kuno_pcie_anoc = {
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
};
static struct qcom_icc_bcm * const system_noc_bcms[] = {
&bcm_sn0,
&bcm_sn2,
&bcm_sn4,
&bcm_sn7,
};
static struct qcom_icc_node * const system_noc_nodes[] = {
[MASTER_CPUCP] = &qhm_cpucp,
[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
[MASTER_CNOC_SNOC] = &qnm_cnoc_datapath,
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
[MASTER_MSS_NAV] = &qxm_mss_nav_ce,
[MASTER_TME] = &qxm_tme,
[MASTER_IPA_PCIE] = &xm_ipa2pcie,
[SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
[SLAVE_PCIE_0] = &xs_pcie_0,
};
static const struct qcom_icc_desc kuno_system_noc = {
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,kuno-aggre-noc", .data = &kuno_aggre_noc },
{ .compatible = "qcom,kuno-clk-virt", .data = &kuno_clk_virt },
{ .compatible = "qcom,kuno-cnoc-main", .data = &kuno_cnoc_main },
{ .compatible = "qcom,kuno-dc-noc", .data = &kuno_dc_noc },
{ .compatible = "qcom,kuno-mc-virt", .data = &kuno_mc_virt },
{ .compatible = "qcom,kuno-mem-noc", .data = &kuno_mem_noc },
{ .compatible = "qcom,kuno-pcie-anoc", .data = &kuno_pcie_anoc },
{ .compatible = "qcom,kuno-system-noc", .data = &kuno_system_noc },
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qcom_icc_rpmh_probe,
.remove = qcom_icc_rpmh_remove,
.driver = {
.name = "qnoc-kuno",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
static int __init qnoc_driver_init(void)
{
return platform_driver_register(&qnoc_driver);
}
core_initcall(qnoc_driver_init);
static void __exit qnoc_driver_exit(void)
{
platform_driver_unregister(&qnoc_driver);
}
module_exit(qnoc_driver_exit);
MODULE_DESCRIPTION("Kuno NoC driver");
MODULE_LICENSE("GPL");

66
drivers/interconnect/qcom/milos.c
View File

@ -137,7 +137,7 @@ static struct qcom_icc_node srvc_pcie_aggre_noc;
static struct qcom_icc_node qns_gemnoc_gc;
static struct qcom_icc_node qns_gemnoc_sf;
static struct qcom_icc_qosbox qhm_qup1_qos = {
static const struct qcom_icc_qosbox qhm_qup1_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -154,7 +154,7 @@ static struct qcom_icc_node qhm_qup1 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
static const struct qcom_icc_qosbox xm_ufs_mem_qos = {
.num_ports = 1,
.port_offsets = { 0xf200 },
.prio = 2,
@ -171,7 +171,7 @@ static struct qcom_icc_node xm_ufs_mem = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
.num_ports = 1,
.port_offsets = { 0x10000 },
.prio = 2,
@ -188,7 +188,7 @@ static struct qcom_icc_node xm_usb3_0 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio = 2,
@ -205,7 +205,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qspi_qos = {
static const struct qcom_icc_qosbox qhm_qspi_qos = {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio = 2,
@ -222,7 +222,7 @@ static struct qcom_icc_node qhm_qspi = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup0_qos = {
static const struct qcom_icc_qosbox qhm_qup0_qos = {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio = 2,
@ -239,7 +239,7 @@ static struct qcom_icc_node qhm_qup0 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
static const struct qcom_icc_qosbox qxm_crypto_qos = {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio = 2,
@ -256,7 +256,7 @@ static struct qcom_icc_node qxm_crypto = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
static const struct qcom_icc_qosbox qxm_ipa_qos = {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio = 2,
@ -273,7 +273,7 @@ static struct qcom_icc_node qxm_ipa = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio = 2,
@ -290,7 +290,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio = 2,
@ -307,7 +307,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc1_qos = {
static const struct qcom_icc_qosbox xm_sdc1_qos = {
.num_ports = 1,
.port_offsets = { 0x1a000 },
.prio = 2,
@ -324,7 +324,7 @@ static struct qcom_icc_node xm_sdc1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
static const struct qcom_icc_qosbox xm_sdc2_qos = {
.num_ports = 1,
.port_offsets = { 0x19000 },
.prio = 2,
@ -404,7 +404,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie = {
.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xf1000 },
.prio = 1,
@ -421,7 +421,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xf3000 },
.prio = 6,
@ -447,7 +447,7 @@ static struct qcom_icc_node chm_apps = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_gpu_qos = {
static const struct qcom_icc_qosbox qnm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x31000, 0x71000 },
.prio = 0,
@ -464,7 +464,7 @@ static struct qcom_icc_node qnm_gpu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
.num_ports = 1,
.port_offsets = { 0xf5000 },
.prio = 0,
@ -491,7 +491,7 @@ static struct qcom_icc_node qnm_mdsp = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x73000 },
.prio = 0,
@ -508,7 +508,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x35000, 0x75000 },
.prio = 0,
@ -525,7 +525,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
.num_ports = 2,
.port_offsets = { 0x37000, 0x77000 },
.prio = 0,
@ -543,7 +543,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_pcie_qos = {
static const struct qcom_icc_qosbox qnm_pcie_qos = {
.num_ports = 1,
.port_offsets = { 0xf7000 },
.prio = 2,
@ -560,7 +560,7 @@ static struct qcom_icc_node qnm_pcie = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
.num_ports = 1,
.port_offsets = { 0xf9000 },
.prio = 0,
@ -577,7 +577,7 @@ static struct qcom_icc_node qnm_snoc_gc = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0xfb000 },
.prio = 0,
@ -620,7 +620,7 @@ static struct qcom_icc_node llcc_mc = {
.link_nodes = { &ebi },
};
static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0xa8000, 0xa9000 },
.prio = 0,
@ -637,7 +637,7 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
.num_ports = 1,
.port_offsets = { 0x2a000 },
.prio = 5,
@ -654,7 +654,7 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x2b000, 0x2c000 },
.prio = 0,
@ -671,7 +671,7 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_mdp_qos = {
static const struct qcom_icc_qosbox qnm_mdp_qos = {
.num_ports = 1,
.port_offsets = { 0xad000 },
.prio = 0,
@ -688,7 +688,7 @@ static struct qcom_icc_node qnm_mdp = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_video_qos = {
static const struct qcom_icc_qosbox qnm_video_qos = {
.num_ports = 1,
.port_offsets = { 0x30000 },
.prio = 0,
@ -737,7 +737,7 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.link_nodes = { &srvc_pcie_aggre_noc },
};
static struct qcom_icc_qosbox xm_pcie3_0_qos = {
static const struct qcom_icc_qosbox xm_pcie3_0_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 2,
@ -754,7 +754,7 @@ static struct qcom_icc_node xm_pcie3_0 = {
.link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_qosbox xm_pcie3_1_qos = {
static const struct qcom_icc_qosbox xm_pcie3_1_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -787,7 +787,7 @@ static struct qcom_icc_node qnm_aggre2_noc = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_apss_noc_qos = {
static const struct qcom_icc_qosbox qnm_apss_noc_qos = {
.num_ports = 1,
.port_offsets = { 0x1c000 },
.prio = 2,
@ -804,7 +804,7 @@ static struct qcom_icc_node qnm_apss_noc = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_cnoc_data_qos = {
static const struct qcom_icc_qosbox qnm_cnoc_data_qos = {
.num_ports = 1,
.port_offsets = { 0x1d000 },
.prio = 2,
@ -821,7 +821,7 @@ static struct qcom_icc_node qnm_cnoc_data = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qxm_pimem_qos = {
static const struct qcom_icc_qosbox qxm_pimem_qos = {
.num_ports = 1,
.port_offsets = { 0x1e000 },
.prio = 2,
@ -838,7 +838,7 @@ static struct qcom_icc_node qxm_pimem = {
.link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_qosbox xm_gic_qos = {
static const struct qcom_icc_qosbox xm_gic_qos = {
.num_ports = 1,
.port_offsets = { 0x1f000 },
.prio = 2,

3
drivers/interconnect/qcom/msm8976.c
View File

@ -454,7 +454,8 @@ static struct qcom_icc_node mas_oxili = {
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
.qos.areq_prio = 0,
.qos.prio_level = 0,
.qos.qos_port = 16, /* [16, 17] */
.qos.qos_port = 16,
.qos.aux_qos_port = 17,
.num_links = ARRAY_SIZE(mas_oxili_links),
.links = mas_oxili_links,
};

1
drivers/interconnect/qcom/msm8996.c
View File

@ -501,6 +501,7 @@ static struct qcom_icc_node mas_venus = {
.qos.areq_prio = 0,
.qos.prio_level = 0,
.qos.qos_port = 3,
.qos.aux_qos_port = 4,
.num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
.links = mas_mnoc_bimc_common_links
};

56
drivers/interconnect/qcom/sm6350.c
View File

@ -149,7 +149,7 @@ static struct qcom_icc_node qhm_a1noc_cfg = {
.link_nodes = { &srvc_aggre1_noc },
};
static struct qcom_icc_qosbox qhm_qup_0_qos = {
static const struct qcom_icc_qosbox qhm_qup_0_qos = {
.num_ports = 1,
.port_offsets = { 0xa000 },
.prio = 2,
@ -165,7 +165,7 @@ static struct qcom_icc_node qhm_qup_0 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_emmc_qos = {
static const struct qcom_icc_qosbox xm_emmc_qos = {
.num_ports = 1,
.port_offsets = { 0x7000 },
.prio = 2,
@ -181,7 +181,7 @@ static struct qcom_icc_node xm_emmc = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
static const struct qcom_icc_qosbox xm_ufs_mem_qos = {
.num_ports = 1,
.port_offsets = { 0x8000 },
.prio = 4,
@ -205,7 +205,7 @@ static struct qcom_icc_node qhm_a2noc_cfg = {
.link_nodes = { &srvc_aggre2_noc },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 2,
@ -221,7 +221,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup_1_qos = {
static const struct qcom_icc_qosbox qhm_qup_1_qos = {
.num_ports = 1,
.port_offsets = { 0x9000 },
.prio = 2,
@ -236,7 +236,7 @@ static struct qcom_icc_node qhm_qup_1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
static const struct qcom_icc_qosbox qxm_crypto_qos = {
.num_ports = 1,
.port_offsets = { 0x6000 },
.prio = 2,
@ -252,7 +252,7 @@ static struct qcom_icc_node qxm_crypto = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
static const struct qcom_icc_qosbox qxm_ipa_qos = {
.num_ports = 1,
.port_offsets = { 0x7000 },
.prio = 2,
@ -268,7 +268,7 @@ static struct qcom_icc_node qxm_ipa = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -284,7 +284,7 @@ static struct qcom_icc_node xm_qdss_etr = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
static const struct qcom_icc_qosbox xm_sdc2_qos = {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio = 2,
@ -300,7 +300,7 @@ static struct qcom_icc_node xm_sdc2 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 2,
@ -356,7 +356,7 @@ static struct qcom_icc_node qup1_core_master = {
.link_nodes = { &qup1_core_slave },
};
static struct qcom_icc_qosbox qnm_npu_qos = {
static const struct qcom_icc_qosbox qnm_npu_qos = {
.num_ports = 2,
.port_offsets = { 0xf000, 0x11000 },
.prio = 0,
@ -372,7 +372,7 @@ static struct qcom_icc_node qnm_npu = {
.link_nodes = { &qns_cdsp_gemnoc },
};
static struct qcom_icc_qosbox qxm_npu_dsp_qos = {
static const struct qcom_icc_qosbox qxm_npu_dsp_qos = {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio = 0,
@ -495,7 +495,7 @@ static struct qcom_icc_node qhm_cnoc_dc_noc = {
&qhs_gemnoc },
};
static struct qcom_icc_qosbox acm_apps_qos = {
static const struct qcom_icc_qosbox acm_apps_qos = {
.num_ports = 2,
.port_offsets = { 0x2f100, 0x2f000 },
.prio = 0,
@ -512,7 +512,7 @@ static struct qcom_icc_node acm_apps = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox acm_sys_tcu_qos = {
static const struct qcom_icc_qosbox acm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0x35000 },
.prio = 6,
@ -539,7 +539,7 @@ static struct qcom_icc_node qhm_gemnoc_cfg = {
&qhs_mdsp_ms_mpu_cfg },
};
static struct qcom_icc_qosbox qnm_cmpnoc_qos = {
static const struct qcom_icc_qosbox qnm_cmpnoc_qos = {
.num_ports = 1,
.port_offsets = { 0x2e000 },
.prio = 0,
@ -556,7 +556,7 @@ static struct qcom_icc_node qnm_cmpnoc = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 1,
.port_offsets = { 0x30000 },
.prio = 0,
@ -573,7 +573,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x34000 },
.prio = 0,
@ -590,7 +590,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
.num_ports = 1,
.port_offsets = { 0x32000 },
.prio = 0,
@ -606,7 +606,7 @@ static struct qcom_icc_node qnm_snoc_gc = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x31000 },
.prio = 0,
@ -622,7 +622,7 @@ static struct qcom_icc_node qnm_snoc_sf = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox qxm_gpu_qos = {
static const struct qcom_icc_qosbox qxm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x33080 },
.prio = 0,
@ -655,7 +655,7 @@ static struct qcom_icc_node qhm_mnoc_cfg = {
.link_nodes = { &srvc_mnoc },
};
static struct qcom_icc_qosbox qnm_video0_qos = {
static const struct qcom_icc_qosbox qnm_video0_qos = {
.num_ports = 1,
.port_offsets = { 0xf000 },
.prio = 2,
@ -671,7 +671,7 @@ static struct qcom_icc_node qnm_video0 = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_cvp_qos = {
static const struct qcom_icc_qosbox qnm_video_cvp_qos = {
.num_ports = 1,
.port_offsets = { 0xe000 },
.prio = 5,
@ -687,7 +687,7 @@ static struct qcom_icc_node qnm_video_cvp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qxm_camnoc_hf_qos = {
static const struct qcom_icc_qosbox qxm_camnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0xa000, 0xb000 },
.prio = 3,
@ -703,7 +703,7 @@ static struct qcom_icc_node qxm_camnoc_hf = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qxm_camnoc_icp_qos = {
static const struct qcom_icc_qosbox qxm_camnoc_icp_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 5,
@ -719,7 +719,7 @@ static struct qcom_icc_node qxm_camnoc_icp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qxm_camnoc_sf_qos = {
static const struct qcom_icc_qosbox qxm_camnoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x9000 },
.prio = 3,
@ -735,7 +735,7 @@ static struct qcom_icc_node qxm_camnoc_sf = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qxm_mdp0_qos = {
static const struct qcom_icc_qosbox qxm_mdp0_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 3,
@ -822,7 +822,7 @@ static struct qcom_icc_node qnm_gemnoc = {
&xs_qdss_stm },
};
static struct qcom_icc_qosbox qxm_pimem_qos = {
static const struct qcom_icc_qosbox qxm_pimem_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 2,
@ -839,7 +839,7 @@ static struct qcom_icc_node qxm_pimem = {
&qxs_imem },
};
static struct qcom_icc_qosbox xm_gic_qos = {
static const struct qcom_icc_qosbox xm_gic_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 3,

70
drivers/interconnect/qcom/sm8650.c
View File

@ -154,7 +154,7 @@ static const struct regmap_config icc_regmap_config = {
.fast_io = true,
};
static struct qcom_icc_qosbox qhm_qspi_qos = {
static const struct qcom_icc_qosbox qhm_qspi_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -171,7 +171,7 @@ static struct qcom_icc_node qhm_qspi = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup1_qos = {
static const struct qcom_icc_qosbox qhm_qup1_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 2,
@ -196,7 +196,7 @@ static struct qcom_icc_node qxm_qup02 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc4_qos = {
static const struct qcom_icc_qosbox xm_sdc4_qos = {
.num_ports = 1,
.port_offsets = { 0xe000 },
.prio = 2,
@ -213,7 +213,7 @@ static struct qcom_icc_node xm_sdc4 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
static const struct qcom_icc_qosbox xm_ufs_mem_qos = {
.num_ports = 1,
.port_offsets = { 0xf000 },
.prio = 2,
@ -230,7 +230,7 @@ static struct qcom_icc_node xm_ufs_mem = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
.num_ports = 1,
.port_offsets = { 0x10000 },
.prio = 2,
@ -247,7 +247,7 @@ static struct qcom_icc_node xm_usb3_0 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio = 2,
@ -264,7 +264,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup2_qos = {
static const struct qcom_icc_qosbox qhm_qup2_qos = {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio = 2,
@ -281,7 +281,7 @@ static struct qcom_icc_node qhm_qup2 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
static const struct qcom_icc_qosbox qxm_crypto_qos = {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio = 2,
@ -298,7 +298,7 @@ static struct qcom_icc_node qxm_crypto = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
static const struct qcom_icc_qosbox qxm_ipa_qos = {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio = 2,
@ -323,7 +323,7 @@ static struct qcom_icc_node qxm_sp = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio = 2,
@ -340,7 +340,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio = 2,
@ -357,7 +357,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
static const struct qcom_icc_qosbox xm_sdc2_qos = {
.num_ports = 1,
.port_offsets = { 0x19000 },
.prio = 2,
@ -448,7 +448,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie = {
.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xbf000 },
.prio = 1,
@ -465,7 +465,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xc1000 },
.prio = 6,
@ -482,7 +482,7 @@ static struct qcom_icc_node alm_sys_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = {
static const struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xc5000 },
.prio = 1,
@ -508,7 +508,7 @@ static struct qcom_icc_node chm_apps = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_gpu_qos = {
static const struct qcom_icc_qosbox qnm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x31000, 0x71000 },
.prio = 0,
@ -525,7 +525,7 @@ static struct qcom_icc_node qnm_gpu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
.num_ports = 1,
.port_offsets = { 0xb5000 },
.prio = 0,
@ -552,7 +552,7 @@ static struct qcom_icc_node qnm_mdsp = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x73000 },
.prio = 0,
@ -569,7 +569,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x35000, 0x75000 },
.prio = 0,
@ -586,7 +586,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
.num_ports = 2,
.port_offsets = { 0x37000, 0x77000 },
.prio = 0,
@ -604,7 +604,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_pcie_qos = {
static const struct qcom_icc_qosbox qnm_pcie_qos = {
.num_ports = 1,
.port_offsets = { 0xb7000 },
.prio = 2,
@ -621,7 +621,7 @@ static struct qcom_icc_node qnm_pcie = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0xbb000 },
.prio = 0,
@ -639,7 +639,7 @@ static struct qcom_icc_node qnm_snoc_sf = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_ubwc_p_qos = {
static const struct qcom_icc_qosbox qnm_ubwc_p_qos = {
.num_ports = 1,
.port_offsets = { 0xc3000 },
.prio = 1,
@ -656,7 +656,7 @@ static struct qcom_icc_node qnm_ubwc_p = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox xm_gic_qos = {
static const struct qcom_icc_qosbox xm_gic_qos = {
.num_ports = 1,
.port_offsets = { 0xb9000 },
.prio = 4,
@ -705,7 +705,7 @@ static struct qcom_icc_node llcc_mc = {
.link_nodes = { &ebi },
};
static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x28000, 0x29000 },
.prio = 0,
@ -722,7 +722,7 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
.num_ports = 1,
.port_offsets = { 0x2a000 },
.prio = 4,
@ -739,7 +739,7 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x2b000, 0x2c000 },
.prio = 0,
@ -756,7 +756,7 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_mdp_qos = {
static const struct qcom_icc_qosbox qnm_mdp_qos = {
.num_ports = 2,
.port_offsets = { 0x2d000, 0x2e000 },
.prio = 0,
@ -781,7 +781,7 @@ static struct qcom_icc_node qnm_vapss_hcp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_qos = {
static const struct qcom_icc_qosbox qnm_video_qos = {
.num_ports = 2,
.port_offsets = { 0x30000, 0x31000 },
.prio = 0,
@ -798,7 +798,7 @@ static struct qcom_icc_node qnm_video = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
.num_ports = 1,
.port_offsets = { 0x32000 },
.prio = 4,
@ -815,7 +815,7 @@ static struct qcom_icc_node qnm_video_cv_cpu = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_cvp_qos = {
static const struct qcom_icc_qosbox qnm_video_cvp_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x34000 },
.prio = 0,
@ -832,7 +832,7 @@ static struct qcom_icc_node qnm_video_cvp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
.num_ports = 1,
.port_offsets = { 0x35000 },
.prio = 4,
@ -873,7 +873,7 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.link_nodes = { &srvc_pcie_aggre_noc },
};
static struct qcom_icc_qosbox xm_pcie3_0_qos = {
static const struct qcom_icc_qosbox xm_pcie3_0_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 3,
@ -890,7 +890,7 @@ static struct qcom_icc_node xm_pcie3_0 = {
.link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_qosbox xm_pcie3_1_qos = {
static const struct qcom_icc_qosbox xm_pcie3_1_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -923,7 +923,7 @@ static struct qcom_icc_node qnm_aggre2_noc = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_apss_noc_qos = {
static const struct qcom_icc_qosbox qnm_apss_noc_qos = {
.num_ports = 1,
.port_offsets = { 0x1c000 },
.prio = 2,

8
drivers/interconnect/qcom/smd-rpm.c
View File

@ -20,7 +20,7 @@ static struct qcom_smd_rpm *icc_smd_rpm;
struct icc_rpm_smd_req {
__le32 key;
__le32 nbytes;
__le32 value;
__le64 value;
};
bool qcom_icc_rpm_smd_available(void)
@ -29,12 +29,12 @@ bool qcom_icc_rpm_smd_available(void)
}
EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_available);
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u64 val)
{
struct icc_rpm_smd_req req = {
.key = cpu_to_le32(RPM_KEY_BW),
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(val),
.nbytes = cpu_to_le32(sizeof(u64)),
.value = cpu_to_le64(val),
};
return qcom_rpm_smd_write(icc_smd_rpm, ctx, rsc_type, id, &req,

1
drivers/interconnect/samsung/exynos.c
View File

@ -98,6 +98,7 @@ static void exynos_generic_icc_remove(struct platform_device *pdev)
struct exynos_icc_priv *priv = platform_get_drvdata(pdev);
icc_provider_deregister(&priv->provider);
dev_pm_qos_remove_request(&priv->qos_req);
icc_nodes_remove(&priv->provider);
}

89
include/dt-bindings/interconnect/qcom,kuno.h Normal file
View File

@ -0,0 +1,89 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_KUNO_H
#define MASTER_SYS_TCU 0
#define MASTER_LLCC 1
#define MASTER_AUDIO 2
#define MASTER_CPUCP 3
#define MASTER_PCIE_RSCC 4
#define MASTER_QDSS_BAM 5
#define MASTER_QPIC 6
#define MASTER_QUP_0 7
#define MASTER_ANOC_SNOC 8
#define MASTER_CNOC_DC_NOC 9
#define MASTER_CNOC_SNOC 10
#define MASTER_MSS_PROC 11
#define MASTER_GEM_NOC_CFG 12
#define MASTER_GEM_NOC_CNOC 13
#define MASTER_GEM_NOC_PCIE_SNOC 14
#define MASTER_ANOC_PCIE_GEM_NOC 15
#define MASTER_SNOC_SF_MEM_NOC 16
#define MASTER_QUP_CORE_0 17
#define MASTER_CRYPTO 18
#define MASTER_IPA 19
#define MASTER_MSS_NAV 20
#define MASTER_TME 21
#define MASTER_APPSS_PROC 22
#define MASTER_EMAC 23
#define MASTER_IPA_PCIE 24
#define MASTER_PCIE_0 25
#define MASTER_QDSS_DAP 26
#define MASTER_QDSS_ETR 27
#define MASTER_QDSS_ETR_1 28
#define MASTER_SDCC_4 29
#define MASTER_USB3_0 30
#define SLAVE_EBI1 31
#define SLAVE_AHB2PHY 32
#define SLAVE_AOSS 33
#define SLAVE_APPSS 34
#define SLAVE_AUDIO 35
#define SLAVE_CLK_CTL 36
#define SLAVE_RBCPR_CX_CFG 37
#define SLAVE_RBCPR_MXA_CFG 38
#define SLAVE_RBCPR_MXC_CFG 39
#define SLAVE_CRYPTO_0_CFG 40
#define SLAVE_EMAC_CFG 41
#define SLAVE_IMEM_CFG 42
#define SLAVE_IPA_CFG 43
#define SLAVE_IPC_ROUTER_CFG 44
#define SLAVE_LAGG_CFG 45
#define SLAVE_MCCC_MASTER 46
#define SLAVE_CNOC_MSS 47
#define SLAVE_PCIE_0_CFG 48
#define SLAVE_PCIE_RSC_CFG 49
#define SLAVE_PDM 50
#define SLAVE_PMU_WRAPPER_CFG 51
#define SLAVE_PRNG 52
#define SLAVE_QDSS_CFG 53
#define SLAVE_QPIC 54
#define SLAVE_QUP_0 55
#define SLAVE_SDCC_4 56
#define SLAVE_SPMI_VGI_COEX 57
#define SLAVE_TCSR 58
#define SLAVE_TLMM 59
#define SLAVE_TME_CFG 60
#define SLAVE_USB3 61
#define SLAVE_VSENSE_CTRL_CFG 62
#define SLAVE_A1NOC_CFG 63
#define SLAVE_DDRSS_CFG 64
#define SLAVE_LLCC 65
#define SLAVE_GEM_NOC_CNOC 66
#define SLAVE_SNOC_MEM_NOC_SF 67
#define SLAVE_MEM_NOC_PCIE_SNOC 68
#define SLAVE_ANOC_PCIE_GEM_NOC 69
#define SLAVE_SNOC_CNOC 70
#define SLAVE_ANOC_THROTTLE_CFG 71
#define SLAVE_QUP_CORE_0 72
#define SLAVE_BOOT_IMEM 73
#define SLAVE_IMEM 74
#define SLAVE_SERVICE_GEM_NOC 75
#define SLAVE_PCIE_0 76
#define SLAVE_QDSS_STM 77
#define SLAVE_TCU 78
#endif